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| amd geode? cs5535 companion device data book amd geode? cs5535 companion device data book february 2005 publication id: 31506b
2 amd geode? cs5535 companion device data book - ? 2005 advanced micro devices, inc. all rights reserved. the contents of this document are pr ovided in connection with advanced micro devices, inc. (?amd?) products. amd make s no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to s pecifications and produ ct descriptions at any time without notice. no license, whet her express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in amd?s standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of mer- chantability, fitness for a particular purpose, or infringement of any intellectual property right. amd?s products are not designed, intend ed, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd?s product could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice. contacts www.amd.com trademarks amd, the amd arrow logo, and combinations th ereof, and geode, geodelink, webpad, and virtual system architecture are trademar ks of advanced micro devices, inc. microsoft is a registered trademark of microsoft corporation in the united states and/or other jurisdictions. other product names used in this publication are fo r identification purposes only and may be trademarks of their respective companies. amd geode? cs5535 companion device data book 3 contents 31506b contents list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.0 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 1.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.0 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1 geodelink? pci south bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.2 geodelink? control processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.3 ata-5 controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4 universal serial bus controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5 audio codec 97 (ac97) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2.6 diverse device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.7 geodelink? interface unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.8 low voltage detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.9 processor support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.0 signal definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1 ball assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.0 global concepts and featur es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.1 geodelink? architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 4.2 msr addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.3 typical geodelink? device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.4 embedded pci adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.5 clock considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.6 reset considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.7 memory and i/o map overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 4.8 standard geodelink? device msrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.9 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.10 component revision id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4 amd geode? cs5535 companion device data book contents 31506b 5.0 module functional descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.1 geodelink? interface unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.2 geodelink? pci south bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 5.3 ac97 audio codec controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.4 ata-5 controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.5 universal serial bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.6 diverse integration logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.7 programmable interval timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.8 programmable interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 5.9 direct memory access module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 5.10 keyboard emulation logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.11 system management bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5.12 uart and ir port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 5.13 low pin count port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 5.14 real-time clock features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 5.15 general purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.16 multi-function general purpose timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 5.17 power management control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 5.18 flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 5.19 geodelink? control processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 5.20 tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 6.0 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 6.1 geodelink? interface unit register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 6.2 geodelink? pci south bridge register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 6.3 ac97 audio codec controller register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 6.4 ata-5 controller register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 62 6.5 usb controller register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 76 6.6 diverse integration logic register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 6.7 floppy port register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 6.8 programmable interval timer register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 6.9 programmable interrupt controller register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 6.10 keyboard emulation logic register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 6.11 system management bus register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 6.12 uart and ir port register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 6.13 direct memory access register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 6.14 low pin count register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 35 6.15 real-time clock register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8 6.16 gpio subsystem register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 6.17 multi-function general purpose timer register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 483 6.18 power management controller register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 6.19 flash controller register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 6.20 geodelink? control processor register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 amd geode? cs5535 companion device data book 5 contents 31506b 7.0 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 7.1 general specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 7.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 7.3 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 7.4 power supply sequence requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 7.5 low voltage detect (lvd) parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 7.6 skip parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 8.0 package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 appendix a support documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 a.1 order information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 a.2 data book revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 6 amd geode? cs5535 companion device data book contents 31506b amd geode? cs5535 companion device data book 7 list of figures 31506b list of figures figure 1-1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 2-1. typical webpad? system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 2-2. thin client application system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 figure 3-1. typical signal groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 3-2. 208-pbga ball assignment diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 4-1. simplified gliu with generic geodelink? devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 4-2. geodelink? architecture asmi and error routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 4-3. amd geode? cs5535 companion device geodelink? architecture topology . . . . . . . . 58 figure 4-4. typical geodelink? device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 4-5. geodelink? device with embedded pci bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 4-6. reset logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 4-7. direct asmi behavioral model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 4-8. in-direct asmi behavioral model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 5-1. module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 5-2. glpci_sb block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 5-3. acc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 5-4. ac link slot scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 5-5. ac link output frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 5-6. ac link input frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 5-7. acc prd table example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 5-8. usb core block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 5-9. usb host controller fsm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 5-10. diverse logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 5-11. i/o space lbar - fixed target size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 5-12. i/o space lbar - variable target size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 5-13. memory space lbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 5-14. pit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 5-15. pit counter latch command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 5-16. pit read-back command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 5-17. pit status byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 5-18. pic subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 5-19. cascading 8259as for lpic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 5-20. pic 8259a block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 5-21. dma module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 5-22. kel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 5-23. smb block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 5-24. smb bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 5-25. smb start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 5-26. smb data transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 5-27. smb acknowledge cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 5-28. smb complete data transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 5-29. smb byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 figure 5-30. smb page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 figure 5-31. smb current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 figure 5-32. smb random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 8 amd geode? cs5535 companion device data book list of figures 31506b figure 5-33. smb sequential reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 5-34. uart/ir overview diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 5-35. uart serial data stream format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 5-36. real dongle interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 5-37. virtual dongle interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 figure 5-38. lpc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 5-39. start of cycle timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 figure 5-40. abort mechanism timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 figure 5-41. dma cycle timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 figure 5-42. start frame waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 5-43. irq frame waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 5-44. stop frame waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 5-45. fwh read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 5-46. fwh write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 5-47. rtc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 figure 5-48. recommended external component connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 5-49. gpio configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 figure 5-50. mfgpt top level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 5-51. mfgpt block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 5-52. mfgpt bit reverse logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 figure 5-53. pmc power management elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 74 figure 5-54. pmc system sleep sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 5-55. pmc system wakeup sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 figure 5-56. flash controller nand read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 figure 5-57. nor flash basic timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 figure 5-58. nor flash with wait states timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 figure 5-59. nand flash command/address timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 figure 5-60. nand data timing with no wait states and no prefetch (for the first data read) . . . . . . . 190 figure 5-61. nand data timing with wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 figure 5-62. glcp block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 figure 5-63. tap controller, boundary scan block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 figure 5-64. tap controller and parallel scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 figure 5-65. tap controller and tapscan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 97 figure 6-1. uart register bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 figure 6-2. dma control signals routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 figure 7-1. clock reference definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 figure 7-2. ac reference timing and test definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 figure 7-3. output reference timing and test definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 1 figure 7-4. input reference timing and test definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 figure 7-5. ide data in timing non-ultradma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 figure 7-6. ide ultradma data out timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 figure 7-7. ide ultradma data in timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 figure 7-8. usb output parameter definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 figure 7-9. usb input parameter definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 figure 7-10. usb differential input sensitivity range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 figure 7-11. lvd electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 figure 7-12. skip electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 figure 8-1. 208-terminal pbga package (body size: 23x23x2.13 mm; pitch: 1.27 mm) . . . . . . . . . . . 575 amd geode? cs5535 companion device data book 9 list of tables 31506b list of tables table 3-1. abbreviations/definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 3-2. ball assignments: sorted by ball number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 3-3. ball assignments: sorted alphabetically by signal name . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 3-4. buffer type characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 3-5. boot options selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 3-6. divil_ball_opt (msr 51400015h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 3-7. ide and flash ball multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 3-8. gpio options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 3-9. gpiox available functions descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 4-1. msr routing conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 4-2. msr addresses from amd geode? gx processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 4-3. clock sources and clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 4-4. register space map except diverse device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 4-5. diverse device register space map except legacy i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 4-6. legacy i/o: 000h-4ffh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 4-7. gld_msr_cap bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 table 4-8. standard gld_msr_smi format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 4-9. gld_msr_smis summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 4-10. msr power management model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 table 4-11. sleep driven pci signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 4-12. sleep driven ide signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 5-1. gliu port connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 5-2. gliu descriptors reserved for geodelink? devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 5-3. cis serial bits assignment and descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 table 5-4. audio bus master descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 5-5. slotreq to output slot mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 table 5-6. physical region descriptor (prd) format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 table 5-7. pcm data format (byte and channel ordering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 5-8. physical region descriptor format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 5-9. udma/66 signal definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 5-10. special cycle decodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 5-11. 8254 pit register ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 5-12. irq map - primary and lpc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 5-13. irq map - unrestricted sources y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 5-14. irq map - unrestricted sources z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 5-15. 8259a pic i/o addresses and i/o data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 16 table 5-16. dma source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 5-17. kel mixed environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 5-18. comparison of smb, i2 c, and access.bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 5-19. smb native registers map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 5-20. uart/ir controller native register bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 table 5-21. real dongle interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 5-22. cycle types supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 5-23. cycle field definitions: target memory, i/o, and dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 5-24. host initiated cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 10 amd geode? cs5535 companion device data book list of tables 31506b table 5-25. dma initiated cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 5-26. irq data frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 5-27. fwh read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 5-28. fwh write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 5-29. external component recommended specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 5-30. effect on feature bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 5-31. 16-bit gpio control register example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 5-32. mfgpt prescaler clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 5-33. mfgpt pulse density modulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 5-34. supported acpi power management states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 5-35. pm events and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 5-36. ecc parity/bit address relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 table 5-37. nand flash external timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 5-38. tap controller instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 5-39. tap controller instruction bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 6-1. standard geodelink? device msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 6-2. p2d descriptor msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 6-3. gliu specific msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 table 6-4. iod descriptor msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 6-5. standard geodelink? device msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 table 6-6. glpci_sb specific msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 table 6-7. pci configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 table 6-8. standard geodelink? device msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 table 6-9. acc native registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 table 6-10. standard geodelink? device msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 table 6-11. atac specific msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 table 6-12. atac native registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 table 6-13. standard geodelink? device msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 table 6-14. usb specific msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 table 6-15. usb embedded pci configuration registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 table 6-16. usb host controller native registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 table 6-17. standard geodelink? device msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 table 6-18. divil specific msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 table 6-19. floppy port specific msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 table 6-20. pit specific msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 table 6-21. pit native registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 table 6-22. pic specific msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 table 6-23. pic native registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 table 6-24. kel specific msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 table 6-25. kel native registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 table 6-26. kel legacy registers emulated summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 table 6-27. smb native registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 table 6-28. uart/ir controller specific msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 table 6-29. uart/ir controller native registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 table 6-30. secondary id encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 table 6-31. register bank summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 table 6-32. bank 0 register bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 table 6-33. eir non-extended mode interrupt priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 88 table 6-34. bit settings for parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 table 6-35. bank select encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 table 6-36. bank 1 bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 table 6-37. bits cleared on fallback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 table 6-38. baud generator divisor settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 table 6-39. bank 2 bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 table 6-40. dma threshold levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 amd geode? cs5535 companion device data book 11 list of tables 31506b table 6-41. bank 3 bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 table 6-42. bank 4 bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 table 6-43. bank 5 bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 table 6-44. bank 6 bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 table 6-45. bank 7 bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 table 6-46. ceir, low speed demodulator (rxhsc = 0) (frequency ranges in khz) . . . . . . . . . . . . 411 table 6-47. consumer ir high speed demodulator (rxh sc = 1) (frequency ranges in khz) . . . . . . 411 table 6-48. sharp-ir demodulator (frequency ranges in khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 table 6-49. modulation carrier pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 table 6-50. ceir carrier frequency encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 table 6-51. ir receive input selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 table 6-52. dma specific msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 table 6-53. dma native registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 table 6-54. lpc specific msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 table 6-55. rtc specific msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 table 6-56. rtc native registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 table 6-57. gpio low/high bank feature bit registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 table 6-58. gpio input conditioning function registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 table 6-59. gpio interrupt and pme mapper registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 table 6-60. low bank atomic register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 table 6-61. low bank atomic bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 table 6-62. high bank atomic register map format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 55 table 6-63. high bank atomic bit descriptions format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 55 table 6-64. mfgpt specific msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 table 6-65. mfgpt native registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 table 6-66. pmc specific msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 table 6-67. acpi registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 table 6-68. pm support registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 table 6-69. flash controller specific msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9 table 6-70. flash controller native registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 0 table 6-71. standard geodelink? device msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 table 6-72. glpc specific msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 table 6-73. clock mapping / operational settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 table 7-1. electro static discharge (esd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 table 7-2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 table 7-3. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6 table 7-4. current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 table 7-5. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 table 7-6. other usb dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 table 7-7. clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 table 7-8. reset and test timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 table 7-9. pci, susp#, suspa#, and reset_out# timing parameters . . . . . . . . . . . . . . . . . . . . . 554 table 7-10. ide register, pio, and multiword dma timing parameters . . . . . . . . . . . . . . . . . . . . . . . . 555 table 7-11. ide ultradma data out timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 table 7-12. ide ultradma data in timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 table 7-13. flash timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 table 7-14. usb timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 table 7-15. smb timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 table 7-16. ac97 codec timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563 table 7-17. lpc timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 table 7-18. power management and processor control timing parameters . . . . . . . . . . . . . . . . . . . . . 565 table 7-19. miscellaneous signals except uart timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 566 table 7-20. uart timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 table 7-21. gpio signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 table 7-22. mfgpt signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 12 amd geode? cs5535 companion device data book list of tables 31506b table 7-23. jtag timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 table 7-24. lvd parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 table 7-25. skip parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 table a-1. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 table a-2. edits to current revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578 amd geode? cs5535 companion device data book 13 1 overview 31506b *the amd geode gx 533@1.1w processor operates at 400 mhz, the amd geode gx 500@1.0w processor operates at 366 mhz, and the amd geode gx 466@0.9w processor operates at 333 mhz. model numbers reflect performance as described here: http://www.amd.com/connectivityso lutions/geodegxbenchmark. 1.0 overview 1.1 general description the amd geode? cs5535 companion device is designed to work with an integrated processor north bridge compo- nent such as an amd geode? gx processor (i.e., geode gx 533@1.1w processor*, g eode gx 500@1.0w proces- sor*, and geode gx 466@0.9w processor*). together, the geode gx processor and geode cs5535 companion device provide a system-level solution well suited for the high-performance and low-power needs of a host of infor- mation appliances that include digital set-top boxes, per- sonal access devices, and thin client applications. the internal architecture has been greatly simplified over previous amd geode companion devices by use of a sin- gle, high-performance modular structure based on geodelink? architecture. this architecture yields high internal speed (over 4 gb/s) data movement and extremely versatile internal power management. the geodelink architecture is transparent to application software. commu- nication with the geode gx proc essor is over a 33/66 mhz pci bus. the cs5535 incorporates many i/o functions, including those found in typical superi/o chips, simplifying many system designs. since the graphics subsystem is entirely contained in the geode gx processor, system interconnect is simplified. the device cont ains state-of-the-art power management that enables syst ems, especially battery powered systems, to signific antly reduce power consump- tion. figure 1-1. block diagram geodelink? pci south bridge amd geode? gx processor interface pci geodelink? control processor (glcp) test/reset interface ac97 controller external audio ata-5 controller usb controller #1 usb controller #2 33 or 66 mhz flash interface 82xx pc legacy mfgp timers rtc & cmos ram uart (2) & ir (1) smb controller lpc port power mgmnt external i/o external usb ports 1-1 & 1-2 external usb ports 2-1 & 2-2 geodelink? interface unit external ide/flash gpio diverse integration logic (divil) diverse device (dd) low voltage detect (lvd) system power voltages power good for power on reset (por) (glpci_sb) (gliu) (usbc1) (usbc2) (acc) (atac) 14 amd geode? cs5535 companion device data book overview 31506b audio is supported by an internal controller, designed to connect to multiple ac97 compatible codecs. an ir (infra- red) port supports all popular ir communication protocols. the ir port is shared with one of two industry-standard serial ports that can reach speeds of 115.2 kbps. an lpc (low pin count) port is provided to facilitate connections to a superi/o should additional expansion, such as a floppy drive, be necessary, and/or to an lpc rom for the system bios. the hard disk controller is an ata-5 compatible bus mas- tering ide controller; includes support for two ata-compli- ant devices on one channel. two dual-port usbs (universal serial buses, usb specification v1.1 compliant) provide four ports with both low and full-speed capabilities for plug & play expansion for a variety of consumer periph- eral devices such as a keyboard, mouse, printer, and digi- tal camera. a battery-backed rtc (real-time clock) keeps track of time and provides calendar functions. a suite of 82xx devices provide the legacy pc functionality required by most designs, including two pics (programma- ble interrupt controllers), o ne pit (programmable interval timer) with three channels, and dma (direct memory access) functions. the geode cs5535 companion device contains eight mfgpts (mul ti-function general purpose timers) that can be used for a variety of functions. a num- ber of gpios (general purpose input/outputs) are provided, and are assigned to system functions on power-up (i.e., lpc port); each of these may be reassigned and given dif- ferent i/o characteristics such as debounce, edge-trigger- ing, etc. state-of-the-art power management features are attained with the division of the device into two internal power domains. the gpios and multi-f unction timers are distrib- uted into each of the two domains to allow these to act as wakeup sources for the device. in addition to full acpi (advanced configuration power interface) compliance and support of industry-standard wakeup and sleep modes, the device automatically disables clocks from internal blocks when they are not being used. 1.2 features general features designed for use with amd?s geode gx processor 208-terminal pbga (plastic ball grid array) package 3.3v i/o and 1.2v or 1.5v (nominal) core operation low power operation: 150 mw typ in working state working and standby power domains ieee 1149.1 compliant tap and boundary scan geodelink? pci bridge (south bridge) provides a pci interface for geodelink devices: ? pci specification v2.2 compliant ? 32-bit, 33/66 mhz operation ? transaction fifos (first in/first out) ? bus master or slave ? converts selected pci co nfiguration bus cycles to internal msr (model specific register) cycles ? capable of handling in-bound transactions immedi- ately after reset - no setup ? mapping of pci virtual configuration space to msr space is done completely in virtual system architec- ture? (vsa) code ? serialized processor control interface geodelink? control processor susp#/supa# handshake with power management logic provides sleep control of all geodelink devices system software debug support using built-in ?logic analyzer? with: ? 8192-bit capture memory ? capture memory can be organized wide or narrow ? ?analyzer? can be connected to thousands of possible internal nodes ? synchronous operation with geode gx processor geodelink control processor ? jtag interface and system bus interfaces ? for debug use, able to conduct any geodelink trans- action via the jtag interface ? manufacturing test support ata-5 controller 66 mb per second ide controller in udma mode per the ata-5 specification 3.3v interface legacy and enhanced pio (programmable i/o), mdma (multi dma), and udma (ultra dma) modes one channel with two devices multiplexed with flash interface flash interface multiplexed with ide interface connects to array of industry standard nand flash and/or nor flash nor optional execute-in-place boot source nand optional file system general purpose isa bus slave-like devices supported with configurable chip selects hardware support for smartmedia type ecc (error correcting code) calculation off loading software inten- sive algorithm amd geode? cs5535 companion device data book 15 overview 31506b usb controllers 1 and 2 two independent host usb controllers; doubles the throughput of a single controller each controller has two ports; total of four ports usb specification v1.1 compliant, with external crimp protection diodes ohci (open host controller interface) specification v1.0 compliant supports wakeup events second generation proven core design over-current and power control support geodelink master burst reads and writes audio codec 97 (ac97) controller ac97 specification v2.1 compliant interface to multiple audio codecs: serial in, seri al out, sync out, bit clock in legacy ?pc beep? support eight-channel buffered geodelink mastering interface asmi and irq support multiple codec support surround sound support diverse device 82xx legacy devices: ? two 8259a-equivalent pics: ? shadow registers allow reading of internal registers ? one 8254-equivalent pit ? two 8237a-equivalent dma controllers: ? 8-bit dma supported (only) ? serial ports 1 and 2: ? port 1 is shared with an ir port ? 16550a and 16450 software compatible ? shadow register support for write-only bit monitoring ? uart data rates up to 115.2 kbps ir (infrared) communication port: ? shared with serial port 1 ? 16550a and 16450 software compatible ? shadow register support for write-only bit monitoring ? consumer-ir (tv-remote) mode ? data rate up to 115.2 kbps (sir) ? hp-sir (same as sir above) ? selectable internal or external modulation/demodula- tion (sharp-ir) ? ask-ir option of sharp-ir ? dask-ir option of sharp-ir ? consumer remote control supports rc-5, rc-6, nec, rca, and recs 80 system management bus (smb) controller: ? compatible with intel system management bus, phillips i 2 c, and access.bus ? bus master and slave operation lpc (low pin count) port: ? based on intel lpc interface specification v1.0 ? serial irq support ? serial dma support (8-bit only) ? boot source typically off external lpc ? supports firmware hub protocol ? external bus masters not supported general purpose i/os (gpios): ? programmable: in, out, i/o, open-drain, pull- up/down, and invert ? parallel bit read and write ? individual bit access eliminates read-modify-write cycles ? input conditioning functions (icf): ? input debounce/filter ? input event counter ? input edge detect multi-function general purpose timers (mfgpts): ? eight mfgpts - two are multiplexed with gpios for external usage ? two mfgpts are powered by standby power and can be used as wakeups ? watchdog timer generates reset, irq, asmi, or nmi ? pulse width modulation (pwm) ? pulse density modulation (pdm) ? blink real-time clock (rtc) with cmos ram: ? battery backed-up century calendar in days, day of the week, date of month, m onths, years and century, with automatic leap-year adjustment ? battery backed-up time of day in seconds, minutes, and hours that allows a 12 or 24 hour format and adjustments for daylight savings time ? bcd or binary format for time keeping ? ds1287, mc146818, and pc87911 compatibility ? selective lock mechanisms for the rtc ram ? real-time alarm ?v bat or v standby power sources with automatic switching between them ? 242 bytes of battery-backed cmos ram in two banks 16 amd geode? cs5535 companion device data book overview 31506b power management controller: ? acpi (advanced configuration power interface) specification v2.0 compliant timer and register set ? supports apm (advanced power management) and legacy pm ? pme (power management event) from gpios and/or on-chip sources ? working, sleep, and standby states ? wakeup circuits powered by standby power rails while rest of component and system powered off ? automatic clock-off gating reduces power to inactive blocks ? flexible power supply controls including on/off and sleep button inputs ? generic sleep output controls ? acpi-compliant four second fail-safe off ? low-voltage detect function for battery-powered applications ? suspend/acknowledge handshake with geode gx processor ? system over-temperature support ? low voltage detect (lvd) provides power on reset (por) as well as continuous voltage monitoring for automatic system reset on a low voltag e condition geodelink? interface unit 64-bit, 66 mhz operation transparent to applications software and bios due to pci vsm (virtual system module) implementation non-blocking arbitration and routing of request and data packets programmable routing descriptors programmable use and activi ty monitors that generate optional asmis (asynchronous system management interrupts) for legacy power management purposes programmable ssmi (synchronous system manage- ment interrupt) generators for selected range of addresses; intended for virtual device emulation (future support, if needed) ata-5 controller, gliu, and diverse device are the only ssmi sources amd geode? cs5535 companion device data book 17 2 architecture overview 31506b 2.0 architecture overview the amd geode? cs5535 companion device provides interfaces for all the common peripherals of an information appliance, plus offers expansion for additional needs, if required. featuring a 33/66 mhz pci interface to the amd geode gx processor, the geode cs5535 companion device is internally connected using the geodelink? packet architecture. this architecture supports multiple simultaneous transactions and is totally transparent to all application software. geodelink architecture related oper- ations are managed via model specific registers (msrs) that are detailed in sectio n 4.1.6 "address spaces and msrs" on page 58. as shown in figure 1-1 on page 13, the geode cs5535 companion device is implemented with one geodelink interface unit (gliu) that connects to the: geodelink pci south bridge geodelink control processor ata-5 controller (ide controller multiplexed with flash interface) universal serial bus 1 controller with ports 1-1 and 1-2 universal serial bus 2 controller with ports 2-1 and 2-2 audio codec 97 (ac97) controller diverse device: ? legacy dma, timer, and interrupt (82xx pc legacy) ? uarts (2) and ir (1) port (shared with uart1) ? system management bus (smb) controller ? low pin count (lpc) controller ? general purpose i/o (gpio) with input conditioning functions (icf) ? multi-function general purpose timers (mfgpts) ? flash interface (multiplexed with ide interface) ? real-time clock (rtc) with cmos ram ? power management controller (pmc) the low voltage detect (lvd) circuit is not a geodelink device, but is connected to the power management con- troller for voltage monitoring support. 2.1 geodelink? pci south bridge the geodelink pci south bridge (glpci_sb) provides a pci interface for the geode cs5535 companion device. it acts as a pci master or slave in providing pci transactions to and from the geode cs5535 companion device and the pci bus. a special serial interface to the geode gx pro- cessor, the cpu interface serial (cis), is provided that assists in the transfer of information between the geode cs5535 companion device and the geode gx processor. the interface is complaint to pci specification v2.2 and may operate at up to 66 mhz. optional bus signals perr#, serr#, lock#, and clkrun are not imple- mented. within a pci burst, zero wait state operation is achieved. the pci interface supports programmable idsel selection, and can handle inbound transactions immediately after system reset. 2.2 geodelink? control processor the geodelink control processor is responsible for debug support and monito rs system clocks in support of pmc operations. the glcp interfaces with a jtag compatible test access port (tap) controller that is ieee 1149.1 compliant. during debug, it can be used to pass geodelink packets to/from the geodelink interface unit (gliu). it is also used to sup- 18 amd geode? cs5535 companion device data book architecture overview 31506b 2.3 ata-5 controller the geode cs5535 companion de vice integrates a fully- buffered, ata-5 compliant (udma/66) ide interface. the ide interface supports one channel, which in turn supports two devices that can operate in pio modes 1 to 4, mdma modes 0 to 2, or udma/66 modes 0 to 4. this interface is shared with the flash interface, using the same balls. the interface usage, immediately after reset, is defined by the boot options selected (see table 3-5 "boot options selection" on page 34). after reset, the interface may be dynamically altered using the ball options msr (see table 3-6 on page 34). the ide interface provides a va riety of features to optimize system performance, including 32-bit disk access, post write buffers, bus master, mdma, look-ahead read buffer, and prefetch mechanism. the ide interface timing is completely programmable. tim- ing control covers the command active and recover pulse widths, and command block register accesses. the ide data transfer speed for each device on each channel can be independently programmed allowing high-speed ide peripherals to coexist on the same channel as older, com- patible devices. the geode cs5535 companion device also provides a software accessible buffered re set signal to the ide drive. the ide_rst# signal is driven low during reset to the geode cs5535 companion device and can be driven low or high as needed for device-power-off conditions. 2.4 universal serial bus controllers the geode cs5535 companion device provides four usb ports, controlled by two independent controllers (usbc1 and usbc2) for 2x enhanced system performance. there are two ports associated with each controller for a total of four. separate power and ground pins for the transceivers are provided to accommodat e various system designs and provide superior noise immunity. each pair of ports has an associated power control line, and there is a common over- current sense line for all four ports, compatible with the national semiconductor lm3526 dual-port usb power switch. the controllers are openhost controller interface (ohci) v1.0 compliant, and the ports adhere to the usb v1.1 specification, with exte rnal crimp protection diodes. 2.5 audio codec 97 (ac97) controller the audio subsection of the geode cs5535 companion device consists of three 32-b it stereo-buffered bus masters (two for output, one for input) and five 16-bit mono-buffered bus masters (three for output, two for input), whose func- tion is to transport audio da ta between system memory and external ac97 codecs. this arrangement is capable of producing multi-channel 5.1 surround sound (left, center, right, left rear, right rear, and low frequency effects). the codec interface is ac97 v2.1 compliant and contains serial in (x2), serial out, sync out, and bit clock allowing support for any ac97 codec with sample rate conversion (src). additionally, the interface supports the industry- standard 16-bit pulse co de modulated (pcm) format. 2.6 diverse device a suite of 82xx devices provide all the legacy pc function- ality required by most designs, including two programma- ble interrupt controllers (pics), one programmable interval timer (pit) with three channels, and direct memory access (dma) functions. the geode cs5535 companion device contains eight multi- function general purpose tim- ers (mfgpts) that can be used for a variety of functions. a number of general-purpose input/outputs (gpios) are provided, and are assigned to system functions on power- up (i.e., lpc port); each of these may be reassigned and given different i/o characteristics such as debounce, edge- triggering, and so forth. the diverse integration logic (divil) holds the devices together and provides overall control and management via msrs. 2.6.1 legacy dma the geode cs5535 companion device dma controller consists of two cascaded 8237 a-type dma controllers that together support four 8-bit ch annels. the dma controller is used to provide high speed transfers between internal chip sources. it has full 32-bit address range support via high- page registers. an internal mapper allows routing of any of seven internal dma sources to the four 8-bit dma chan- nels. amd geode? cs5535 companion device data book 19 architecture overview 31506b 2.6.2 programmable interval timer, legacy timer the programmable interval timer (pit) generates pro- grammable time intervals from the divided clock of an external clock input. the pit is an 8254-style timer that contains three 16-bit independently programmable counters. a 14.318 mhz external clock signal (from a crys- tal oscillator or a clock chip) is divided by 12 to generate 1.19 mhz for the clocking reference of all three counters. 2.6.3 programmable interrupt controller, legacy interrupt the programmable interrupt controller (pic) consists of two 8259a-compatible programmable interrupt controllers connected in cascade mode through interrupt number two. request mask capability and edge-level controls are pro- vided for each of the 15 channels along with a 15-level pri- ority controller. the pic devi ces support all x86 modes of operation except special fully nested mode. an irq mapper takes up to 62 discrete interrupt request (irq) inputs and maps or mask s them to the 15 pic inputs and to one asmi (asynchronous system management interrupt). all 62 inputs are individually maskable and sta- tus readable. in addition to the above 8259a features, there are shadow registers to obtain the values of legacy 8259a registers that have not been historically readable. 2.6.4 keyboard emulation logic, legacy support interface the ps2 keyboard emulation logic (kel) provides a vir- tual 8042 keyboard controller interface that may be used to map non-legacy keyboard and mouse sources to this tradi- tional interface. flexible keyboard emulation logic allows ps2 keyboard emulation traditionally used for usb legacy keyboard emulation. for example, usb sources may be ?connected? to this interface via smm (system manage- ment mode) software. it also allows mixed environments with one lpc legacy device and one usb device. 2.6.5 universal asynchronous receiver transmitter and ir port two universal asynchronous receiver transmitters (uarts) provide a system interface to the industry stan- dard serial interface consisting of the basic transmit and receive signals. one of the uarts can be coupled with infrared logic and be connected to an infrared sensor. the uarts are both 16550a and 16450 software-compati- ble and contain shadow register support for write-only bit monitoring. the ports have data rates up to 115.2 kbps. serial port 1 can be configured as an infrared communica- tions port that supports sharp-ir, consumer-ir, and hp- sir as well as many popular consumer remote-control pro- tocols. 2.6.6 system management bus controller the system management bus (smb) controller provides a system interface to the industry standard smb. the smb allows easy interfacing to a wide range of low-cost memory and i/o devices, including: eeproms, srams, timers, adc, dac, clock chips, and peripheral drivers. these lines are shared with two gpios and must be configured as smb ports in order for this interface to be functional. the smb is a two-wire synchronous serial interface com- patible with the system manage ment bus physical layer. the smb controller can be c onfigured as a bus master or slave, and can maintain bidirectional communication with both multiple master and slave devices. as a slave device, the smb controller may issue a request to become the bus master. 2.6.7 low pin count port this port provides a system interface to the industry stan- dard low pin count (lpc) bus. the controller can convert an internal local bus memory or i/o cycle to an external lpc cycle. it receives serial irqs from the lpc and con- verts them to parallel form so they can be routed to the irq mapper. lastly, it interacts with legacy dma logic to per- form dma between on-chip or off-chip dma devices. the lpc interface is based on the intel?s low pin count (lpc) interface specification v1.0. in addition to the required signals/pins specified in the intel specification, it also supports two optional signals: lpc_drq# - lpc dma request lpc_serirq - lpc serial encoded irq the lpc interface supports memory, i/o, dma, and intel?s firmware hub interfaces. 2.6.8 general purpose i/os with input conditioning functions (icf) there are 32 gpios in the geode cs5535 companion device, 28 are externally available, that offer a variety of user-selectable configurations including accessing auxil- iary functions within the chip, and input conditioning such as debounce and edge detect. register access is config- ured in such a way as to avoid read-modify-write opera- tions; each gpio may be directly and independently configured. several groups of gpios are multiplexed between the lpc controller, the smb controller, access to the uarts and mfgpts, and power management controls including sys- tem power and sleep buttons. six of the gpios are in the standby power domain, giving them increased versatility as wakeup event sources when only standby power is applied. a gpio interrupt and power management event (pme) mapper can map any subset of gpios to the pics (eight interrupts available) or power management subsystem (eight events available). 20 amd geode? cs5535 companion device data book architecture overview 31506b versatile input filtering is available for each gpio input. each preliminary input is optionally connected to a digital filter circuit that is optionally followed by an event counter. lastly followed by an edge detector that together provide eight different icfs (input c onditioning functions), plus an auto-sense feature for determin ing the initial condition of the pin. 2.6.9 multi-function general purpose timers this module contains eight multi-function general pur- pose timers (mfgpts), six are in the normal v dd working power domain, while the other two are in the standby power domain. the timers are very versatile and can be configured to provide a watchdog timer (trigger gpio out- put, interrupt or reset), perform pulse width modulation (pwm) or pulse density modulation (pdm), create blink (low frequency pulse for led), generate gpio outputs, or act as general purpose timers. each mfgpt operates independently and has the follow- ing features: 32 khz or 14.318 mhz clock selectable by software (applies to mfgpt0 to mfgpt5, in working power domain, only). mfgpt6 and mfgpt7, in standby power domain, use 32 khz clock. programmable input clock prescaler divisor to divide input clock by 2 i , where i = 0 to 15. provide outputs for generating reset (limited to mfgpt0 to mfgpt5), irqs, nmi, and asmis (indirectly through pics). 2.6.10 flash interface the geode cs5535 companion device has a flash device interface that supports popular nor flash and inexpen- sive nand flash devices. this interface is shared with the ide interface (ata-5 controller (atac)), using the same balls. nor or nand flash may co-exist with ide devices using pio (programmed i/o) mode. the 8-bit interface supports up to four ?lanes? of byte-wide flash devices through use of four independent chip selects, and allows for booting from the array. hardware support is present for smartmedia-type ecc (error correction code) calcula- tions, off-loading software from having to support this task. all four independent chip selects may be used as general purpose chip selects to support other isa-like slave devices. up to 1 kb of address space (without external latches) may be supported using these signals. 2.6.11 real-time clock with cmos ram the geode cs5535 companion device maintains a real- time clock for system use. the clock is powered by an external battery and so continues to keep accurate time even when system power is removed. the clock can be set to make automatic daylight savings time changes in the spring and fall without user intervention. there are sepa- rate registers for seconds, minutes, hours, days (both day of the week and day of the month), months, and years. alarms can be set for any time within the range of these registers, which have a 100-year capability. the clock uses an external 32 khz oscillator or crystal as the timing ele- ment. the same battery that keeps the clock continuously pow- ered also provides power to a block of 242 bytes of cmos ram, used for storing non-volatile system parameters. 2.6.12 power management controller the geode cs5535 companion device has state-of-the-art power management capabilities designed into every mod- ule. independent clock controls automatically turn clocks off to sections of the chip that are not being used, saving considerable power. in addition, the chip supports full sleep and wakeup states with multiple methods of induce- ment. a suite of external signals support power manage- ment of devices on the s ystem board. legacy power management (pm), advanced power management (apm), and advanced configuration and power interface (acpi) techniques and requirements are supported. the gpio subsystem can be configured to transmit any of several wakeup events into the system. the geode cs5535 companion device is divided into two main power domains: working and standby, plus circuits such as the real-time clock and cmos ram that are bat- tery-backed. most of the geode cs5535 companion device is in the working power domain, except for gpio[31:24] and mfgpt[7:6]. this allows these devices to be used for wakeup events or output controls. 2.7 geodelink? interface unit the geodelink interface unit (gliu) makes up the internal bus derived from the geodelink architecture. it has eight ports, one of which is dedicated to itself, leaving seven for use by internal geodelink devices. figure 1-1 "block dia- gram" on page 13 shows this device as the central element of the architecture, though it s presence is basically trans- parent to the end user. 2.8 low voltage detect the low voltage detect (lvd) circuit monitors: standby i/o voltage, standby core voltage, and working core volt- age. working i/o voltage is not monitored and is assumed to track with working core voltage. the lvd monitors these voltages to provide working and standby power- good signals (resets) for the respective working and standby power domains. additionally, the pmc monitors the working power-good signal to shut-down and/or re-start the system as appropriate. amd geode? cs5535 companion device data book 21 architecture overview 31506b 2.9 processor support as previously stated, the geode cs5535 companion device was designed to interface with the geode gx pro- cessor. figure 2-1 and figure 2-2 on page 22 show typical block diagrams for a webpad? system and thin client application based on the geode gx processor and geode cs5535 companion device. figure 2-1. typical webpad? system block diagram usb port 2 usb port 3 amd geode? amd geode? cs5535 pci1211 tps2211 cardbus socket padcard connector cpld sdram sodimm ce optional cardbus controller pci lpc bus lpc xpressrom compact flash ide lvds tft lcd dstn lcd microcontroller 2-wire uart i/f ac97 audio amp mic in internal mic touchscreen interface headphone usb power switch usb port 3 usb port 2 power section ac cube charger liion battery two-phase sync. triple regulator controller 5v/3.3v ac adapter or battery power clock generator for all clocks companion device gx processor regulator codec and over-current protection 22 amd geode? cs5535 companion device data book architecture overview 31506b figure 2-2. thin client application system block diagram sdram ethernet compact flash amd geode? amd geode? cs5535 usb power switch ac97 clocks crt dstn or tft headphones server memory bus 2-wire i/f pci bus rgb out digital rgb lpc bus ide usb 4 ports dc to dc gx processor v cc 3v v cc core v cc 5v companion device amp codec regulator regulator regulator and over-current protection controller flash/rom amd geode? cs5535 companion device data book 23 3 signal definitions 31506b 3.0 signal definitions this section defines the signals and describes the external interface of the amd geode? cs5535 companion device. signal multiplexing has been utilized to a high degree. for example, the ide and flash interfaces are multiplexed on the same balls. configuration is dependent upon the boot options selected (see table 3-5 "boot options selection" on page 34). if flash is selected, the user has the option of using nor and/or nand flash devices. the gpios are configurable (e.g., any gpio input can be mapped to an interrupt, asmi, or pme). figure 3-1 shows the signals organized in typical functional groups - not all possible multiplexing is shown. where signals are multiplexed, the primary signal name is listed first and is separated by a plus sign (+). a slash (/) in a signal name means that the function is always enabled and available (i.e., time multiplexed). figure 3-1. typical signal groups mhz66_clk reset_work# reset_stand# mhz48_clk khz32_xci khz32_xco mhz14_clk system interface signals ad[31:0] c/be[3:0]# pa r frame# devsel# irdy# trdy# stop# req# gnt# pci interface signals usb_pwr_en1 usb_pwr_en2 usb_oc_sens# usb1_1_datpos usb1_1_datneg usb1_2_datpos usb1_2_datneg usb2_1_datpos usb2_1_datneg usb2_2_datpos usb2_2_datneg usb interface ac_s_out+bos1 ac_s_in ac_s_sync+bos0 lpc interface signals reset_out# working susp#/cis suspa# irq13 v bat v ss_vbat1 v ss_vbat2 lv d _ e n # pci_clk av ss_usb av dd_usb lpc_clk lpc_ad[3:0]+gpio[19:16] lpc_drq#+gpio20 lpc_serirq+gpio21 lpc_frame#+gpio22 signals audio codec 97 interface signals ac_clk amd geode? cs5535 (continued on next page) companion device 24 amd geode? cs5535 companion device data book signal definitions 31506b figure 3-1. typical signal groups (continued) ide_cs0#+flash_cs0#+ce0# ide_cs1#+flash_cs1#+ce1# ide_ior0#+flash_re# ide_iow0#+flash_we# ide_ad0+flash_ad25/ad[0]+cle ide_rdy0+flash_iochrdy+rdy/busy# ide_dreq0#+flash_cs2#+ce2# ide_dack0#+flash_cs3#+ce3# gpio2+ide_irq0 ide/flash signals ide_data[7:0]+flash_ad[17:10]/io[7:0] gpio14+smb_clk gpio15+smb_data gpio1+ac_beep ide_ad[2:1]+flash_ad[27:26]/ad[2:1] ide_data[14:8]+flash_ad[24:18]/ad[9:3] ide_data15+flash_ale interface gpio10+thrm_alrm# ide_reset# gpio11+slp_clk_en#+mfgpt_c2 gpio24+work_aux gpio25+low_bat#+mfgpt7_c2 gpio28+pwr_but# gpio0 ( pci_inta# ) gpio3+uart2_rx ( ddc_scl ) gpio4+uart2_tx ( ddc_sda ) gpio5+mfgpt1_rs+mfgpt0_c1 gpio6+mfgpt0_rs+mfgpt1_c1+mfgpt2_c2 gpio7+mfgpt2_c1+sleep_x ( pci_intb# ) gpio8+uart1_tx+uart1_ir_tx gpio9+uart1_rx+uart1_ir_rx gpio26+mfgpt7_rs ( pme# ) gpio27+mfgpt7_c1+32khz gpios and ?recommended? usage tck tms tdi tdo t_debug_in t_debug_out lvd_test test_mode func_test v core [total of 8] v core_vsb [total of 1] v io [total of 14] v io_vsb [total of 1] v ss [total of 18] nc [total of 19] debug and interface signals manufacturing power, ground, and no connects gpio12+ac_s_in2+sleep_y gpio13+sleep_but amd geode? cs5535 companion device note: bold-italicized signal names in parenthesis denote a ?r ecommended? use for a specific gpio. see table 3-8 "gpio options" on page 47 for additional details. amd geode? cs5535 companion device data book 25 signal definitions 31506b 3.1 ball assignments as illustrated in figure 3-1 on page 23, the geode cs5535 companion device is configurable. boot options and regis- ter programming are used to set various modes of opera- tion and specific signals on specific balls. this section describes the ball assignments and interface options: figure 3-2 "208-pbga ball assignment diagram" on page 26: ? top view looking through package. table 3-2 "ball assignments: sorted by ball number" on page 27: ? primary signal name is listed first. ? includes a column labeled buffer type . see section 3.1.1 "buffer types" on page 33 for details. ? includes a column labeled configuration with refer- ences to: ? bos[1:0] - see section 3.1.2 "boot options" on page 34. ? ball opt msr - see section 3.1.3 "ball options" on page 34. ? in_aux1, out_aux1, and out_aux2 - see section 3.2.8 "gpios" on page 47. table 3-3 "ball assignments: sorted alphabetically by signal name" on page 31: ? quick-reference list, sorted alphabetically with primary signal listed first. the tables in this section use several abbreviations. table 3-1 lists the mnemonics and their meanings. table 3-1. abbreviations/definitions mnemonic definition a analog av ss analog ground connection av dd analog power connection gnd ground i input i/o bidirectional o output od open-drain ball opt msr model specific register ball options: a regist er is used to configure balls with multiple functions. refer to section 3.1.3 "ball options" on page 34 for further details. pd pull-down resistor pwr power pu pull-up resistor ts tri-state v core 1.2v or 1.5v core power working connection v core_vsb 1.2v or 1.5v core power standby connection v io 3.3v i/o power working connection v io_vsb 3.3v i/o power standby connection v ss ground # the ?#? symbol at the end of a signal name indicate s that the active, or asserted state occurs when the signal is at a low voltage level. when ?#? is no t present after the signal name, the signal is asserted when at a high voltage level. / a ?/? in a signal name indicates the function is always enabled (i.e., time multiplexed - available when needed). + a ?+? in a signal name indicates the function is availa ble on the ball, but that either strapping options or register programming is required to select the desired function. 26 amd geode? cs5535 companion device data book signal definitions 31506b figure 3-2. 208-pbga ball assignment diagram b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 17 gpio11 nc v bat khz32i rst# tstm v core gpio28 gpio25 mhz66 ide_a0 ide_a1 ide_rdy ide_dq# nc ide_d1 ide_d12 nc v ss_vbat2 khz32o nc nc v io_vsb gpio26 rstsd# lvdtst ide_cs0# ide_ a2 gpio2 ide_ior# ide_d0 ide_d13 ide_d14 ide_d4 mhz14 gpio7 gpio10 v ss_vbat1 wrkg rstwrk# lvden# gpio27 gpio24 ide_c s1# nc ide_dk0# ide_iow# ide_d15 ide_d3 ide_d2 ide_d11 gpio9 gpio6 gpio5 v io v ss v io v ss v core v io v core v ss v io v ss v io ide_d10 ide_d5 ide_d9 gpio3 gpio4 gpio8 v ss v ss ide_d7 ide_d6 ide_d8 gpio15 gpio13 ftst v io v io av ss_usb ide_rst# av dd_usb lpc_dq# lpc_sq gpio14 v ss v ss usb2_2n nc usb2_2p lcp_clk lpc_a0 lpc_frm# v core v core usb2_1n nc usb2_1p lpc_a2 lpc_a1 gpio12 v ss v ss av ss_usb nc av dd_usb lpc_a3 irq13 gpio1 v core v core usb1_1p nc usb1_1n ac_sin ac_sout ac_ssync v ss v ss usb1_2p nc usb1_2n ac_clk dbugi dbugo v io v io av ss_usb nc av dd_usb suspa# tck tms v ss v ss usb_pw2e usb_oc# mhz48 tdi tdo susp# v io v ss v io v ss v core v io v core v ss v io v ss v io ad4 ad7 usb_pw1e gnt# gpio0 nc ad28 ad26 c/be3# ad21 ad18 nc irdy# devsel# ad15 ad12 ad9 ad2 ad6 ad0 req# nc ad30 ad27 ad25 ad23 ad20 ad17 c/be2# trdy# stop# ad14 ad11 ad8 ad3 ad5 ad1 ad31 nc ad29 pci_clk ad24 ad22 ad19 ad16 frame# par c/be1# ad13 ad10 c/be0# nc nc nc a b c d e f g h j k l m n p r t u a b c d e f g h j k l m n p r t u 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 17 b note: signal names have been abbreviated in th is figure due to space constraints. = gnd terminal = pwr terminal = multiplexed signal b = bos (boot option select) (top view - looking through package) amd geode? cs5535 companion device amd geode? cs5535 companion device data book 27 signal definitions 31506b table 3-2. ball assignments: sorted by ball number ball no. signal name (note 1) type buffer type (note 2) configuration a1 gpio11 i/o q7 slp_clk_en# o out_aux1 mfgpt1_c2 o out_aux2 a2 nc --- --- a3 v bat wire bare_wire_ bp a4 khz32_xci wire bare_wire a5 reset_out# o q7 a6 test_mode wire bare_wire a7 v core_vsb pwr --- a8 gpio28 i/o q7 pwr_but# i in_aux1 a9 gpio25 i/o q7 low_bat# i in_aux1 mfgpt7_c2 o out_aux2 a10 mhz66_clk i q3 a11 ide_ad0 o ide bos[1:0] = 00 or 11 flash_ad25/ad0 o bos[1:0] = 10 flash_cle o a12 ide_ad1 o ide bos[1:0] = 00 or 11 flash_ad26/ad1 o bos[1:0] = 10 a13 ide_rdy0 i ide bos[1:0] = 00 or 11 flash_iochrdy i bos[1:0] = 10 flash_rdy/busy# i a14 ide_dreq0 i ide bos[1:0] = 00 or 11 flash_cs2# o bos[1:0] = 10 flash_ce2# o a15 ide_data1 i/o ide bos[1:0] = 00 or 11 flash_ad11/io1 i/o bos[1:0] = 10 a16 nc --- --- a17 ide_data12 i/o ide bos[1:0] = 00 or 11 flash_ad22/ad7 o bos[1:0] = 10 b1 nc --- --- b2 v ss_vbat2 agnd avss_usb b3 khz32_xco wire bare_wire b4 nc --- --- b5 nc --- --- b6 v io_vsb pwr --- b7 gpio26 i/o q7 mfgpt7_rs i in_aux1 b8 reset_stand# i bare_wire b9 lvd_test wire (o) bare_wire b10 ide_cs0# o ide bos[1:0] = 00 or 11 flash_cs0# o bos[1:0] = 10 flash_ce0# o b11 ide_ad2 o ide bos[1:0] = 00 or 11 flash_ad27/ad2 o bos[1:0] = 10 b12 gpio2 i/o ide ide_irq0 i in_aux1 b13 ide_ior0# o ide bos[1:0] = 00 or 11 flash_re# o bos[1:0] = 10 b14 ide_data0 i/o ide bos[1:0] = 00 or 11 flash_ad10/io0 i/o bos[1:0] = 10 b15 ide_data14 i/o ide bos[1:0] = 00 or 11 flash_ad24/ad9 o bos[1:0] = 10 b16 ide_data13 i/o ide bos[1:0] = 00 or 11 flash_ad23/ad8 o bos[1:0] = 10 b17 ide_data4 i/o ide bos[1:0] = 00 or 11 flash_ad14/io4 i/o bos[1:0] = 10 c1 mhz14_clk i q7 c2 gpio7 i/o pci mfgpt2_c1 o out_aux1 sleep_x o out_aux2 c3 gpio10 i/o q7 thrm_alrm# i in_aux1 c4 v ss_vbat1 agnd avss_usb c5 working o smb c6 reset_work# i q7 c7 lvd_en# wire bare_wire c8 gpio27 i/o q7 mfgpt7_c1 o out_aux1 32khz o out_aux2 c9 gpio24 i/o smb work_aux o out_aux1 c10 ide_cs1# o ide bos[1:0] = 00 or 11 flash_cs1# o bos[1:0] = 10 flash_ce1# o c11 nc --- --- c12 ide_dack0# o ide bos[1:0] = 00 or 11 flash_cs3# o bos[1:0] = 10 flash_ce3# o c13 ide_iow0# o ide bos[1:0] = 00 or 11 flash_we# o bos[1:0] = 10 c14 ide_data15 i/o ide bos[1:0] = 00 or 11 flash_ale o bos[1:0] = 10 c15 ide_data2 i/o ide bos[1:0] = 00 or 11 flash_ad12/io2 i/o bos[1:0] = 10 c16 ide_data3 i/o ide bos[1:0] = 00 or 11 flash_ad13/io3 i/o bos[1:0] = 10 ball no. signal name (note 1) type buffer type (note 2) configuration 28 amd geode? cs5535 companion device data book signal definitions 31506b c17 ide_data11 i/o ide bos[1:0] = 00 or 11 flash_ad21/ad6 o bos[1:0] = 10 d1 gpio9 i/o q7 uart1_rx i in_aux1 uart1_ir_rx i d2 gpio6 i/o q7 mfgpt0_rs i in_aux1 mfgpt1_c1 o out_aux1 mfgpt2_c2 o out_aux2 d3 gpio5 i/o q7 mfgpt1_rs i in_aux1 mfgpt0_c1 o out_aux1 d4 v io pwr --- d5 v ss gnd --- d6 v io pwr --- d7 v ss gnd --- d8 v core pwr --- d9 v io pwr --- d10 v core pwr --- d11 v ss gnd --- d12 v io pwr --- d13 v ss gnd --- d14 v io pwr --- d15 ide_data5 i/o ide bos[1:0] = 00 or 11 flash_ad15/io5 i/o bos[1:0] = 10 d16 ide_data10 i/o ide bos[1:0] = 00 or 11 flash_ad20/ad5 o bos[1:0] = 10 d17 ide_data9 i/o ide bos[1:0] = 00 or 11 flash_ad19/ad4 o bos[1:0] = 10 e1 gpio3 i/o smb uart2_rx i in_aux1 e2 gpio4 i/o smb uart2_tx o out_aux1 e3 gpio8 i/o q7 uart1_tx o out_aux1 uart1_ir_tx o out_aux2 e4 v ss gnd --- e14 v ss gnd --- e15 ide_data6 i/o ide bos[1:0] = 00 or 11 flash_ad16/io6 i/o bos[1:0] = 10 e16 ide_data7 i/o ide bos[1:0] = 00 or 11 flash_ad17/io7 i/o bos[1:0] = 10 e17 ide_data8 i/o ide bos[1:0] = 00 or 11 flash_ad18/ad3 o bos[1:0] = 10 ball no. signal name (note 1) type buffer type (note 2) configuration f1 gpio15 i/o smb smb_data i/o in_aux1 and out_aux1 f2 gpio13 i/o q7 sleep_but i in_aux1 f3 func_test i smb f4 v io pwr --- f14 v io pwr --- f15 ide_reset# o ide f16 av ss_usb agnd avss_usb f17 av dd_usb apwr avdd_usb g1 lpc_drq# i pci ball opt msr [6,4] = 1,1 gpio20 i/o ball opt msr [6] = 0 g2 lpc_serirq i/o pci ball opt msr [6,5] = 1,1 gpio21 i/o ball opt msr [6] = 0 mfgpt2_rs i in_aux1 g3 gpio14 i/o smb smb_clk i/o in_aux1 and out_aux1 g4 v ss gnd --- g14 v ss gnd --- g15 nc --- --- g16 usb2_2_datneg i/o bare_wire g17 usb2_2_datpos i/o bare_wire h1 lpc_clk i q7 h2 lpc_ad0 i/o pci ball opt msr [6] = 1 gpio16 i/o ball opt msr [6] = 0 h3 lpc_frame# o pci ball opt msr [6] = 1 gpio22 i/o ball opt msr [6] = 0 h4 v core pwr --- h14 v core pwr --- h15 nc --- --- h16 usb2_1_datneg i/o bare_wire h17 usb2_1_datpos i/o bare_wire j1 lpc_ad2 i/o pci ball opt msr [6] = 1 gpio18 i/o ball opt msr [6] = 0 j2 lpc_ad1 i/o pci ball opt msr [6] = 1 gpio17 i/o ball opt msr [6] = 0 j3 gpio12 i/o q7 ac_s_in2 i in_aux1 sleep_y o out_aux2 j4 v ss gnd --- j14 v ss gnd --- ball no. signal name (note 1) type buffer type (note 2) configuration table 3-2. ball assignments: sorted by ball number (continued) amd geode? cs5535 companion device data book 29 signal definitions 31506b j15 nc --- --- j16 av ss_usb agnd avss_usb j17 av dd_usb apwr avdd_usb k1 lpc_ad3 i/o pci ball opt msr [6] = 1 gpio19 i/o ball opt msr [6] = 0 k2 irq13 i q7 k3 gpio1 i/o q7 default ac_beep o out_aux1 mfgpt0_c2 o out_aux2 k4 v core pwr --- k14 v core pwr --- k15 nc --- --- k16 usb1_1_datpos i/o bare_wire k17 usb1_1_datneg i/o bare_wire l1 ac_s_in i q7 l2 ac_s_out o q7 bos1 i l3 ac_s_sync o q7 bos0 i l4 v ss gnd --- l14 v ss gnd --- l15 nc --- --- l16 usb1_2_datpos i/o bare_wire l17 usb1_2_datneg i/o bare_wire m1 ac_clk i q7 m2 t_debug_in i q5 m3 t_debug_out o q5 m4 v io pwr --- m14 v io pwr --- m15 nc --- --- m16 av ss_usb agnd avss_usb m17 av dd_usb apwr avdd_usb n1 suspa# i q7 n2 tck i q7 n3 tms i q7 n4 vss gnd --- n14 vss gnd --- n15 usb_oc_sens# i q7 n16 usb_pwr_en2 o q7 n17 mhz48_clk i q3 p1 tdi i q5 p2 tdo o, ts q5 p3 susp# o q3 cis o p4 v io pwr --- p5 v ss gnd --- p6 v io pwr --- p7 v ss gnd --- p8 v core pwr --- ball no. signal name (note 1) type buffer type (note 2) configuration p9 v io pwr --- p10 v core pwr --- p11 v ss gnd --- p12 v io pwr --- p13 v ss gnd --- p14 v io pwr --- p15 ad7 i/o pci p16 ad4 i/o pci p17 usb_pwr_en1 o q7 r1 gnt# i pci r2 gpio0 i/o pci r3 nc --- --- r4 ad28 i/o pci r5 ad26 i/o pci r6 c/be3# i/o pci r7 ad21 i/o pci r8 ad18 i/o pci r9 nc --- --- r10 irdy# i/o pci r11 devsel# i/o pci r12 ad15 i/o pci r13 ad12 i/o pci r14 ad9 i/o pci r15 ad6 i/o pci r16 ad2 i/o pci r17 ad0 i/o pci t1 req# o pci t2 nc --- --- t3 ad30 i/o pci t4 ad27 i/o pci t5 ad25 i/o pci t6 ad23 i/o pci t7 ad20 i/o pci t8 ad17 i/o pci t9 c/be2# i/o pci t10 trdy# i/o pci t11 stop# i/o pci t12 ad14 i/o pci t13 ad11 i/o pci t14 ad8 i/o pci t15 ad5 i/o pci t16 ad3 i/o pci t17 ad1 i/o pci u1 ad31 i/o pci u2 nc --- --- u3 ad29 i/o pci u4 pci_clk i q3 u5 ad24 i/o pci u6 ad22 i/o pci u7 ad19 i/o pci u8 ad16 i/o pci ball no. signal name (note 1) type buffer type (note 2) configuration table 3-2. ball assignments: sorted by ball number (continued) 30 amd geode? cs5535 companion device data book signal definitions 31506b u9 frame# i/o pci u10 par i/o pci u11 c/be1# i/o pci u12 ad13 i/o pci u13 ad10 i/o pci u14 c/be0# i/o pci ball no. signal name (note 1) type buffer type (note 2) configuration u15 nc --- --- u16 nc --- --- u17 nc --- --- note 1. the primary signal name is listed first. note 2. see table 3-4 "buffer type characteristics" on page 33 for buffer type definitions. ball no. signal name (note 1) type buffer type (note 2) configuration table 3-2. ball assignments: sorted by ball number (continued) amd geode? cs5535 companion device data book 31 signal definitions 31506b table 3-3. ball assignments: sorted alphabetically by signal name signal name ball no. 32khz c8 ac_beep k3 ac_clk m1 ac_s_in l1 ac_s_in2 j3 ac_s_out l2 ac_s_sync l3 ad0 r17 ad1 t17 ad2 r16 ad3 t16 ad4 p16 ad5 t15 ad6 r15 ad7 p15 ad8 t14 ad9 r14 ad10 u13 ad11 t13 ad12 r13 ad13 u12 ad14 t12 ad15 r12 ad16 u8 ad17 t8 ad18 r8 ad19 u7 ad20 t7 ad21 r7 ad22 u6 ad23 t6 ad24 u5 ad25 t5 ad26 r5 ad27 t4 ad28 r4 ad29 u3 ad30 t3 ad31 u1 av dd_usb f17, j17, m17 av ss_usb f16, j16, m16 bos0 l3 bos1 l2 c/be0# u14 c/be1# u11 c/be2# t9 c/be3# r6 cis p3 devsel# r11 flash_ad10/io0 b14 flash_ad11/io1 a15 flash_ad12/io2 c15 flash_ad13/io3 c16 flash_ad14/io4 b17 flash_ad15/io5 d15 flash_ad16/io6 e15 flash_ad17/io7 e16 flash_ad18/ad3 e17 flash_ad19/ad4 d17 flash_ad20/ad5 d16 flash_ad21/ad6 c17 flash_ad22/ad7 a17 flash_ad23/ad8 b16 flash_ad24/ad9 b15 flash_ad25/ad0 a11 flash_ad26/ad1 a12 flash_ad27/ad2 b11 flash_ale c14 flash_ce0# b10 flash_ce1# c10 flash_ce2# a14 flash_ce3# c12 flash_cle a11 flash_cs0# b10 flash_cs1# c10 flash_cs2# a14 flash_cs3# c12 flash_iochrdy a13 flash_rdy/busy# a13 flash_re# b13 flash_we# c13 frame# u9 func_test f3 gnt# r1 gpio0 r2 gpio1 k3 gpio2 b12 gpio3 e1 gpio4 e2 gpio5 d3 gpio6 d2 gpio7 c2 gpio8 e3 gpio9 d1 gpio10 c3 gpio11 a1 gpio12 j3 gpio13 f2 gpio14 g3 gpio15 f1 gpio16 h2 signal name ball no. gpio17 j2 gpio18 j1 gpio19 k1 gpio20 g1 gpio21 g2 gpio22 h3 gpio24 c9 gpio25 a9 gpio26 b7 gpio27 c8 gpio28 a8 ide_ad0 a11 ide_ad1 a12 ide_ad2 b11 ide_cs0# b10 ide_cs1# c10 ide_dack0# c12 ide_data0 b14 ide_data1 a15 ide_data2 c15 ide_data3 c16 ide_data4 b17 ide_data5 d15 ide_data6 e15 ide_data7 e16 ide_data8 e17 ide_data9 d17 ide_data10 d16 ide_data11 c17 ide_data12 a17 ide_data13 b16 ide_data14 b15 ide_data15 c14 ide_dreq0# a14 ide_ior0# b13 ide_iow0# c13 ide_irq0 b12 ide_rdy0 a13 ide_reset# f15 irdy# r10 irq13 k2 khz32_xci a4 khz32_xco b3 low_bat# a9 lpc_ad0 h2 lpc_ad1 j2 lpc_ad2 j1 lpc_ad3 k1 lpc_clk h1 lpc_drq# g1 lpc_frame# h3 lpc_serirq g2 signal name ball no. lv d _ e n # c 7 lvd_test b9 mfgpt0_c1 d3 mfgpt0_c2 k3 mfgpt0_rs d2 mfgpt1_c1 d2 mfgpt1_c2 a1 mfgpt1_rs d3 mfgpt2_c1 c2 mfgpt2_c2 d2 mfgpt2_rs g2 mfgpt7_c1 c8 mfgpt7_c2 a9 mfgpt7_rs b7 mhz14_clk c1 mhz48_clk n17 mhz66_clk a10 nc (total of 19) a2, a16, b1, b4, b5, c11, g15, h15, j15, k15, l15, m15, r3, r9, t2, u2, u15, u16, u17 pa r u 1 0 pci_clk u4 pwr_but# a8 req# t1 reset_out# a5 reset_stand# b8 reset_work# c6 sleep_but f2 sleep_x c2 sleep_y j3 slp_clk_en# a1 smb_clk g3 smb_data f1 stop# t11 susp# p3 suspa# n1 t_debug_in m2 t_debug_out m3 tck n2 tdi p1 signal name ball no. 32 amd geode? cs5535 companion device data book signal definitions 31506b tdo p2 test_mode a6 thrm_alrm# c3 tms n3 trdy# t10 uart1_ir_rx d1 uart1_ir_tx e3 uart1_rx d1 uart1_tx e3 uart2_rx e1 uart2_tx e2 usb_oc_sens# n15 usb_pwr_en1 p17 usb_pwr_en2 n16 usb1_1_datneg k17 usb1_1_datpos k16 usb1_2_datneg l17 usb1_2_datpos l16 usb2_1_datneg h16 usb2_1_datpos h17 usb2_2_datneg g16 usb2_2_datpos g17 vbat a3 v core (total of 8) d8, d10, h4, h14, k4, k14, p8, p10 v core_vsb a7 signal name ball no. v io (total of 14) d4, d6, d9, d12, d14, f4, f14, m4, m14, p4, p6, p9, p12, p14 v io_vsb b6 signal name ball no. v ss (total of 18) d5, d7, d11, d13, e4, e14, g4, j4, l4, n4, n14, p5, p7, p11, p13 signal name ball no. v ss_vbat1 c4 v ss_vbat2 b2 work_aux c9 working c5 signal name ball no. table 3-3. ball assignments: sorted alphabetically by signal name (continued) amd geode? cs5535 companion device data book 33 signal definitions 31506b 3.1.1 buffer types table 3-2 "ball assignments: sorted by ball number" on page 27 includes a column labeled ?buffer type?. the details of each buffer type list ed in this column are given in table 3-4. the column headings in table 3-4 are identified as follows: ts: indicates whether the buffer may be put into the tri- state mode. note some pins that have buffer types that allow tri-state may never actually enter the tri-state mode in practice, since they may be inputs or provide other signals that are always driven. to determine if a particular signal can be put in the tri-state mode, consult the indi- vidual signal descriptions in section 3.2 "signal descrip- tions" on page 36. od: indicates if the buffer is open-drain, or not. open-drain outputs may be wire ored t ogether and require a discrete pull-up resistor to operate properly. 5vt: indicates if the buffer is 5-volt tolerant, or not. if it is 5- volt tolerant, then 5 volt ttl signals may be safely applied to this pin. backdrive protected: indicates that the buffer may have active signals applied even when the geode cs5535 com- panion device is powered down. pu/pd: indicates if an internal, programmable pull-up or pull-down resistor may be present. current high/low (ma): this column gives the current source/sink capacities when the voltage at the pin is high, and low. the high and low values are separated by a ?/? and values given are in milli-amps (ma). rise/fall @ load: this column indicates the rise and fall times for the different buffer types at the load capacitance indicated. these measuremen ts are given in two ways: rise/fall time between the 20%-80% voltage levels, or, the rate of change the buffer is capable of, in volts-per-nano- second (v/ns). see section 7.3 "ac characteristics" on page 550 for details. note the presence of several ?wire? type buffers in this table. signals identified as one of the wire-types are not driven by a buffer, hence no rise/fall time or other measure- ments are given; these are marked ?na? in table 3-4. the wire-type connection indicates a direct connection to inter- nal circuits such as power, ground, and analog signals. table 3-4. buffer type characteristics name ts od 5vt backdrive protected pu/pd current high/low (ma) rise/fall @ load q3 x x 24/24 3 ns @ 50 pf q5 x x 24/24 5 ns @ 50 pf q7 x x 24/24 7 ns @ 50 pf pci x 0.5/1.5 1-4 v/ns @ 10 pf ide x 16/16 1.25 v/ns @ 40 pf smb x x x rise: 1 s @ 400 pf fall: 300 ns @ 400 pf bare_wire na na na na na bare_wire_bp na na x na na na avdd_usb na na na na na avss_usb na na na na na 34 amd geode? cs5535 companion device data book signal definitions 31506b 3.1.2 boot options two balls on the device, l2 and l3, the boot options select balls (bos[1:0]), serve to specify the location of the boot device as the system under goes a full reset. since boot devices may reside in flash or on an ide device, the ide/flash interface is necessarily selected as operating in one of the two modes by the boot options. after reset, the function of these interfaces may be changed with the ball options msr (see section 3.1.3 "ball options"). both these balls are multiplexed with other functions (as identi- fied in section 3.2.7 "audio codec 97 interface" on page 45) and function as bos[1: 0] only when reset_out# is asserted. table 3-5 indicates how these two balls should be configured to select the desired boot device. both balls contain an internal pull-up, active only during reset, so if a ball is required to be high during this time, it may be left unconnected. if a ball is desired to be low during reset, a pull-down (i.e., not a hard tie to ground) should be added. during reset, both balls? output drivers are in the tri- state mode. 3.1.3 ball options table 3-6 shows the ball options msr (divil msr 51400015h), through which the function of certain groups of multiplexed balls may be dynamically changed after the reset period ends. specifically, the functions lpc/gpio and ide/flash groups are selected, and certain individual balls, as specified in th e msr, are controlled. table 3-5. boot options selection bos1 (ball l2) bos0 (ball l3) description 00 boot from memory device on the lpc bus. ide pins come up connected to ide control- ler (see section 3.2.3 "ide/flash inte rface signals" on page 40 and table 3-6 "divil_ball_opt (msr 51400015h)"). 01 reserved. 10 boot from nor flash on the ide bus. ide pins come up connected to flash controller (see section 3.2.3 "ide/flash interfac e signals" on page 40 and table 3-6 "divil_ball_opt (msr 51400015h)"). nor flash, rom, or other random access de vices must be connected to ?flash_cs_3?. 11 boot from firmware hub on the lpc bus. ide pins come up connected to ide control- ler (see section 3.2.3 "ide/flash inte rface signals" on page 40 and table 3-6 "divil_ball_opt (msr 51400015h)"). table 3-6. divil_ball_opt (msr 51400015h) bit name description 31:12 rsvd reserved. reads always return 0. writes have no effect; by convention, always write 0. 11:10 sec_boot_loc secondary boot location. determines which chip select asserts for addresses in the range f00f0000h to f00f 3fffh. defaults to the same value as boot option: 00: lpc rom. 01: reserved . 10: flash. 11: firmware hub. 9:8 boot_op_ latched (ro) latched value of boot option (read only). for values, see table 3-5 "boot options selection". 7 rsvd reserved. reads return value written. by convention, always write 0. defaults low. amd geode? cs5535 companion device data book 35 signal definitions 31506b 6 pin_opt_lall all lpc pin option selection. 0: all lpc pins become gpios including lpc_drq# and lpc_serirq. ball h3 functions as gpio22 ball h2 functions as gpio16 ball j2 functions as gpio17 ball j1 functions as gpio18 ball k1 functions as gpio19 ball g1 functions as gpio20 ball g2 functions as gpio21 1: all lpc pins are controlled by t he lpc controller except lpc_drq# and lpc_serirq use are determined by bits [5:4]. (default) ball h3 functions as lpc_frame# ball h2 functions as lpc_ad0 ball j2 functions as lpc_ad1 ball j1 functions as lpc_ad2 ball k1 functions as lpc_ad3 when this bit is low, there is an im plied high for the lpc_disable_mem and lpc_disable_io bits in divil_leg _io (divil msr 51400014h[25:24]). 5 pin_opt_lirq lpc_serirq or gpio21 pin option selection. 0: ball g2 is gpio21. 1: ball g2 functions as lpc_serirq. (default) 4 pin_opt_ldrq lpc_drq# or gpio20 pin option selection. 0: ball g1 is gpio20. 1: ball g2 functions as lpc_drq#. (default) 3:2 pri_boot_loc [1:0] primary boot location. determines which chip select asserts for addresses at or above f0000000h, except those in the range specified by sec_boot_loc (bits [11:10]). defaults to the same value as boot option. 00: lpc rom. 01: reserved . 10: flash. 11: firmware hub. 1 rsvd reserved. reads return value written. by convention, always write 0. defaults low. 0 pin_opt_ide ide or flash controller pin function selection. 0: all ide pins associated with flash co ntroller. default if bos[1:0] = 10. 1: all ide pins associated with ide contro ller. default if bos[1:0] = 00 or 11. ide_irq0 is multiplexed with gpio2; therefore, this bit has no affect with regards to programming ide_irq0. see table 3-5 "boot options selection" for bos[1:0] pro- gramming values. table 3-6. divil_ball_opt (msr 51400015h) (continued) bit name description 36 amd geode? cs5535 companion device data book signal definitions 31506b 3.2 signal descriptions information in the tables that follow may have duplicate inform ation in multiple tables. multiple references all contain identi - cal information. 3.2.1 system interface signals signal name ball no. type description mhz66_clk a10 i 66 mhz clock. this is the main system clock. it is also used by the ide interface. mhz48_clk n17 i usb clock. the 48 mhz clock for the uarts and smb controller. mhz14_clk c1 i 14.31818 mhz timer clock. the input clock for power management functions and the programmable interval timer (pit). khz32_xci a4 wire 32 khz input. this input is used for the re al-time clock (rtc), gpios, mfgpts, and power management functions. this input may come from either an external oscillator or one side of a 32.768 khz crystal. if an external oscillator is used, it should be pow- ered by v io_vsb . external oscillators often do not power up cleanly, causing the standby logic to fail to reset properly. if used, it is required that reset_stand# be used to reset the standby logic after the external oscillator has stabilized. this can be as long as one second. khz32_xco b3 wire 32 khz input 2. this input is to be connected to the other side of the crystal oscillator connected to khz32_xci, if used. leave open (not connected) if an oscillator (not a cr ystal) is connected to khz32_xci. reset_work# c6 i reset working power domain. this signal, when asserted, is the master reset for all geode cs5535 companion device interfaces that are in the working power domain. see section 4.9.1 "power domains" on page 80 for a description of the working power domain. reset_work# must be asserted for at least 10 ns in order to be properly recognized. if lvd_en# is enabled (tied low) use of this input is not required. see the lvd_en# signal description for further details. reset_stand# b8 i reset standby power domain. this signal, when asserted, is the master reset for all geode cs5535 companion device interfaces that are in the standby power domain. see section 4.9.1 "power domains" on page 80 for a description of the standby power domain. to ensure the skip feature is disabled, pwr_but# must be high before reset_stand# is de-asserted. see pwr_but# description in table 3-9 "gpiox available functions descriptions" starting on page 49 for details on the skip feature.? if lvd_en# is enabled (tied low) use of this input is not required. see the lvd_en# discussion in this table. tie directly to v io_vsb if not used. reset_out# a5 o reset output. this is the main system re set signal. reset_out# is de-asserted synchronously with the low-to-high edge of pci_clk. the de-assertion is delayed from internal reset by up to 32 seconds, with an 8 ms default value, using a programmable counter driven by the 32 khz clock. note this counter def ault is established by reset_stand# and is not affected by reset_work# . therefore, the delay value may be changed and the system reset with the new value. working c5 o working state. when high, indicates the chip is in the working state. this signal is intended to be used to control power to off-chip devices in a system. open-drain. external pull-up required. amd geode? cs5535 companion device data book 37 signal definitions 31506b susp# p3 o suspend. this signal goes low in response to events as determined by the power management logic. it requests the geode gx processor to enter the suspend state. this is the default state for this ball at reset. not used in normal operation. cis o cpu interface serial. a 20-bit serial status word is output on this ball, synchronized to pci_clk. data changes on the rising edge and is sta- ble on the falling edge of pci_clk. this word is output whenever one of the internally-monitored signals changes states. see section 5.2.14 "cpu interface serial (cis)" on page 87 for details. used in nor- mal operation. suspa# n1 i suspend acknowledge. this input signal is driven low by the geode gx processor when it has successfully entered the suspend state. irq13 k2 i interrupt request level 13. floating point error. connect directly to irq13 of the geode gx processor. v bat a3 wire real-time clock battery back-up. battery voltage on this ball keeps the real-time clock and cmos ram circuits continuously powered. if not used, tie to ground. 2.4-3.6v, typical 3.0v. 10 a max. 5 a typical. this ball incorporates a reverse bias protection diode on-chip. there is no need for an external diode. v ss_vbat1 c4 agnd real-time clock battery grounds 1 and 2 v ss_vbat2 b2 lvd_en# c7 wire low voltage detect enable. lvd_en# enables/disables the on-chip low voltage detection circuit. when disabled, the external subsystem must assert reset_stand# as standby power is applied and must assert reset_work# as working power is applied. when lvd is enabled, use of these two resets are optional. generally, reset_stand# would be tied high (not used) while reset_work# would be tied to a reset output that is typically available from the power supply. however, a system could just have a simple regulator circuit and also tie reset_work# high. tie to v ss to enable. tie to v io_vsb to disable. 3.2.1 system interface signals (continued) signal name ball no. type description 38 amd geode? cs5535 companion device data book signal definitions 31506b 3.2.2 pci interface signals signal name (note 1) ball no. type description pci_clk u4 i pci clock. 33 or 66 mhz. ad[31:0] u1, t3, u3, r4, t4, r5, t5, u5, t6, u6, r7, t7, u7, r8, t8, u8, r12, t12, u12, r13, t13, u13, r14, t14, p15, r15, t15, p16, t16, r16, t17, r17 i/o pci address/data. ad[31:0] is a physical address during the first clock of a pci transaction; it is the data during subsequent clocks. when the geode cs5535 companion device is a pci master, ad[31:0] are outputs during the address and wr ite data phases, and are inputs during the read data phase of a transaction. when the geode cs5535 companion devi ce is a pci slave, ad[31:0] are inputs during the address and wr ite data phases, and are outputs during the read data phase of a transaction. c/be[3:0]# r6, t9, u11, u14 i/o pci bus command and byte enables. during the address phase of a pci transaction, when frame# is active, c/be[3:0]# define the bus command. during the data phase of a transaction, c/be[3:0]# are the data byte enables. c/be[3:0]# are outputs when the geode cs5535 companion device is a pci master and inputs when it is a pci slave. pa r u 1 0 i / o pci parity. par is the parity signal driven to maintain even parity across ad[31:0] and c/be[3:0]#. the geode cs5535 companion device drives par one clock after the address phase and one clock after each completed data phase of write transactions as a pci master. it also drives par one clock after each completed data phase of read transactions as a pci slave. frame# u9 i/o pci cycle frame. frame# is asserted to indicate the start and dura- tion of a transaction. it is de-asserted on the final data phase. frame# is an input when the geode cs5535 companion device is a pci slave. normally connected to a 10k to15k ? external pull-up. this signal is in tri-state mode after reset. devsel# r11 i/o pci device select. devsel# is asserted by a pc i slave, to indicate to a pci master and subtractive decoder that it is the target of the current transaction. as an input, devsel# indicates a pci slave has responded to the cur- rent address. as an output, devsel# is asserted one cycle after the assertion of frame# and remains asserted to the end of a transaction as the result of a positive decode. devse l# is asserted four cycles after the assertion of frame# if devsel# has not been asserted by another pci device when the geode cs5535 companion device is pro- grammed to be the subtractive decode agent. normally connected to a 10k to15k ? external pull-up. this signal is in tri-state mode after reset. amd geode? cs5535 companion device data book 39 signal definitions 31506b irdy# r10 i/o pci initiator ready. irdy# is driven by the master to indicate valid data on a write transaction, or that it is ready to receive data on a read transaction. when the geode cs5535 companion device is a pci slave, irdy# is an input that can delay the beginning of a write transaction or the com- pletion of a read transaction. wait cycles are inserted until both irdy# and trdy# are asserted together. normally connected to a 10k to15k ? external pull-up. this signal is in tri-state mode after reset. trdy# t10 i/o pci target ready. trdy# is asserted by a pci slave to indicate it is ready to complete the current data transfer. trdy# is an input that indicates a pci slave has driven valid data on a read or a pci slave is ready to accept data from the geode cs5535 companion device on a write. trdy# is an output that indicate s the geode cs5535 companion device has placed valid data on ad[31: 0] during a read or is ready to accept the data from a pci master on a write. wait cycles are inserted until both irdy# and trdy# are asserted together. normally connected to a 10k to15k ? external pull-up. this signal is in tri-state mode after reset. stop# t11 i/o pci stop. as an input, stop# indicates th at a pci slave wants to ter- minate the current transfer. the transfe r is either aborted or retried. stop# is also used to end a burst. as an output, stop# is asserted with trdy# to indicate a target dis- connect, or without trdy# to indicate a target retry. the geode cs5535 companion device asserts stop# during any cache line crossings if in single transfer dma mode or if busy. normally connected to a 10k to15k ? external pull-up. this signal is in tri-state mode after reset. req# t1 o pci bus request. the geode cs5535 companion device asserts req# to gain ownership of the pci bus. the req# and gnt# signals are used to arbitrate for the pci bus. req# should connect to the req2 # of the geode gx processor and function as the highest-priority pci master. gnt# r1 i pci bus grant. gnt# is asserted by an ar biter that indicates to the geode cs5535 companion device that access to the pci bus has been granted. gnt# should connect to gnt2# of the geode gx processor and func- tion as the highest-priority pci master. note 1. use reset_out# for pci reset. for smi, pme, inta#, and intb# function s, see table 3-8 "gpio options" on page 47. 3.2.2 pci interface signals (continued) signal name (note 1) ball no. type description 40 amd geode? cs5535 companion device data book signal definitions 31506b 3.2.3 ide/flash interface signals the ide and flash interface signals are mu ltiplexed together on the same balls as shown in table 3-7. section 3.2.3.1 pro- vides the names and functions of these signals when the inte rface is in the ide mode and section 3.2.3.2 when in flash mode (nor flash/gpcs and nand flash modes). table 3-7. ide and flash ball multiplexing ball no. ide mode nor flash/gpcs mode nand flash mode address phase data phase b11, a12 ide_ad[2:1] flash _ad[27:26] flash_ad[2:1] --- a11 ide_ad0 flash_ad25 flash_ad0 flash_cle b15, b16, a17, c17, d16, d17, e17 ide_data[14:8] flash_ad[24:18] flash_ad[9:3] --- e16, e15, d15, b17, c16, c15, a15, b14 ide_data[7:0] flash_ad[17:10 ] flash_io[7:0] flash_io[7:0] c14 ide_data15 flash_ale flash_ale b10 ide_cs0# flash_cs0# flash_ce0# c10 ide_cs1# flash_cs1# flash_ce1# b13 ide_ior0# flash_re# flash_re# c13 ide_iow0# flash_we# flash_we# a14 (note 1) note 1. ball a14 is the only ball that changes direction from ide to flash (input when in ide mode, output when in flash mode). if this interface is to be switched between ide a nd flash modes, then ball a14 needs an external pull-up to keep it high during ide mode. ide_dreq0 flash_cs2# flash_ce2# c12 ide_dack0# flash_cs3# (boot flash chip select) flash_ce3# a13 ide_rdy0 flash_iochrdy flash_rdy/busy# 3.2.3.1 ide inte rface signals signal name ball no. type description ide_irq0 b12 i ide interrupt request channel 0. this signal is required for all ide applications that use ide dma modes. it is available on gpio2, which must be configured in the in_aux1 mode. if an ide application will not use ide dma modes, or if the flash interface will be used instead of the ide interface, then this signal may be used as gpio2. ide_reset# f15 o ide reset. an internal reset that is th e functional ?or? of inputs reset_work# and reset_stand#. it may also be controlled directly via a msr 51300010h (see section 6.4.2.2 "reset decode (atac_reset)" on page 269). this si gnal resets all the devices that are attached to the ide interface. ide_ad[2:0] b11, a12, a11 o ide address bits. these address bits are used to access a register or data port in a device on the ide bus. amd geode? cs5535 companion device data book 41 signal definitions 31506b ide_data[15:0] c14, b15, b16, a17, c17, d16, d17, e17, e16, e15, d15, b17, c16, c15, a15, b14 i/o ide data lines. ide_data[15:0] transfers data to/from the ide devices. ide_ior0# b13 o ide i/o read. this output is asserted on read accesses to corre- sponding ide port addresses. when in ultra dma/33 mode, this signal is redefined: ide_hdma_rdy. host dma ready for ultra dma data-in bursts. ide_hdma_ds. host dma data strobe for ultra dma data-out bursts. ide_iow0# c13 o ide i/o write. this output is asserted on write accesses to corre- sponding ide port addresses. when in ultra dma/33 mode, this signal is redefined: ide_stop - stop ultra dma data burst. ide_cs0# b10 o ide chip select 0. this chip select signal is used to select the com- mand block registers in ide device 0. ide_cs1# c10 o ide chip select. this chip select signal is used to select the com- mand block registers in ide device 1. ide_dreq0 a14 i dma request. the dreq input is used to request a dma transfer from the geode cs5535 companion device. the direction of the trans- fers are determined by the ide_ior0# and ide_iow0# signals. note: ball a14 is the only ball that changes direction from ide to flash (input when in ide mode, output when in flash mode). if this interface is to be switched between ide and flash modes, the ide interface must only use pio mode and ball a14 requires a pull-up resistor to keep flash_cs3# high when in ide mode. ide_dack0# c12 o dma acknowledge. the dack# output acknowledges the ide_dreq0 request to initiate dma transfers. ide_rdy0 a13 i i/o ready. when de-asserted, this signal extends the transfer cycle of any host register access when the de vice is not ready to respond to the data transfer request. when in ultra dma/33 mode, this signal is redefined: ide_ddma_ds - device dma data strobe for ultra dma data-in bursts. ide_ddma_rdy - device dma ready for ultra dma data-out bursts. 3.2.3.1 ide interface signals (continued) signal name ball no. type description 42 amd geode? cs5535 companion device data book signal definitions 31506b 3.2.3.2 flash controller interface signal name ball no. type description nor flash / gpcs mode flash_cs[3:0]# c12, a14, c10, b10 o chip selects. combine with flash_re#/we# strobes to access external nor flash devices or some simple devices such as a uart. cs3# is dedicated to a boot flash device. note: ball a14 is the only ball that changes direction from ide to flash (input when in ide mode, output when in flash mode). if this interface is to be switched between ide and flash modes, the ide interface must only use pio mode and ball a14 requires a pull-up resistor to keep flash_cs3# high when in ide mode. flash_re# b13 o read enable strobe. this signal is asserted during read operations from the nor array. flash_we# c13 o write enable strobe. this signal is asserted during write operations to the nor array. flash_ale c14 o address latch enable. controls external latch (e.g., 74x373) for latching the higher address bits in address phase. flash_ad[27:26]/ ad[2:1], flash_ad25/ ad0, flash_ad[24:18]/ ad[9:3] b11, a12, a11, b15, b16, a17, c17, d16, d17, e17 o address bus. during the address phase, address [27:18] is put on the bus. during the data phase, address [9:0] is put on the bus. flash_ad[17:10]/ io[7:0] e16, e15, d15, b17, c16, c15, a15, b14 i/o multiplexed address and i/o bus. during the address phase, nor address [17:10] are placed on these lin es. during the data phase, it is the nor i/o data bus. flash_iochrdy a13 i i/o channel ready. when a device on the bus wants to extend its current cycle, it pulls this signal low to insert the wait state. nand flash mode flash_ce[3:0]# c12, a14, c10, b10 o chip enables. these signals remain low during a nand cycle. note: ball a14 is the only ball that changes direction from ide to flash. needs external pull-up for flash use. flash_re# b13 o read enable strobe. this signal is asserted during read operations from the nand array. flash_we# c13 o write enable strobe. this signal is asserted during write operations to the nand array. flash_ale c14 o address latch enable. level signal to indicate an address byte is writing to the nand flash device. flash_cle a11 o command latch enable. indicates a command byte is being written to the device. flash_io[7:0] e16, e15, d15, b17, c16, c15, a15, b14 i/o i/o bus. i/o bus for nand flash devices. command, address, and data are sent on this bus. this bus is actively driven to zero with or without an lpc_clk from and after reset. flash_rdy/busy# a13 i ready/busy#. nand flash pulls this signal low to indicate it is busy with an internal operation. no furt her action is accepted except read status. amd geode? cs5535 companion device data book 43 signal definitions 31506b 3.2.4 usb interface signal name ball no. type description usb_pwr_en1 p17 o usb power enable 1. this signal is intended to be used to enable an external usb power source for port 1, such as the national semicon- ductor lm3526. usb_pwr_en1 is an active high signal. if low, it indicates that the external usb power source for port 1 is turned off. defaults off from reset. usb_pwr_en2 n16 o usb power enable 2. this signal is intended to be used to enable an external usb power source for port 2, such as the national semicon- ductor lm3526. usb_pwr_en2 is an active high signal. if low, it indicates that the external usb power source for port 2 is turned off. defaults off from reset. usb_oc_sens# n15 i usb over current sense. this signal is the logical or or wired-or from all external usb power supply devices, such as the national semiconductor lm3526, and is shared by usb1 and usb2 (all four ports). when pulled low it causes both usb_pwr_en1 and usb_pwr_en2 to de-assert and generate an interrupt. tie high if not used. usb1_1_datpos k16 i/o usb port 1_1 data positive. this is the positive differential side of the usb data for port 1_1. (note 1, note 2.) usb1_1_datneg k17 i/o usb port 1_1 data negative. this is the negative differential side of the usb data for port 1_1. (note 1, note 2.) usb1_2_datpos l16 i/o usb port 1_2 data positive. this is the positive differential side of the usb data for port 1_2. (note 1, note 2.) usb1_2_datneg l17 i/o usb port 1_2 data negative. this is the negative differential side of the usb data for port 1_2. (note 1, note 2.) usb2_1_datpos h17 i/o usb port 2_1 data positive. this is the positive differential side of the usb data for port 2_1. (note 1, note 2.) usb2_1_datneg h16 i/o usb port 2_1 data negative. this is the negative differential side of the usb data for port 2_1. (note 1, note 2.) usb2_2_datpos g17 i/o usb port 2_2 data positive. this is the positive differential side of the usb data for port 2_2. (note 1, note 2.) usb2_2_datneg g16 i/o usb port 2_2 data negative. this is the negative differential side of the usb data for port 2_2. (note 1, note 2.) av ss_usb f16, j16, m16 agnd usb analog circuit ground. total of three ground balls for the usb transceivers. most applications should connect this to signal ground. av dd_usb f17, j17, m17 apwr usb analog circuit power. total of three power balls for the usb transceivers. most applications should connect this to v io . note 1. use external 27 ? series resistor on output. from reset, these outputs are in tri-state. at board level, a 15 k ? pull-down resistor is required per the usb specification. note 2. external clamping diodes may be needed to meet over voltage requirements. 44 amd geode? cs5535 companion device data book signal definitions 31506b 3.2.5 system management bus (smb) interface signal name ball no. type description smb_clk g3 i/o smb clock. this is the clock for the syst em management bus. it is ini- tiated by the master of the current transaction. data is sampled during the high state of the clock. an external pull-up resistor is required. shared with gpio14. set gpio14 to in_aux1 and out_aux1 modes simultaneously to use as smb_clk. see table 3-8 "gpio options" on page 47. external voltage applied to this ball should not exceed v io . smb_data f1 i/o smb data. this is the bidirectional data line for the system manage- ment bus. data may change during the low state of the smb clock and should remain stable during the high state. an external pull-up resistor is required. shared with gpio15. set gpio15 to in_aux1 and out_aux1 modes simultaneously to use as smb_data. see table 3-8 "gpio options" on page 47. external voltage applied to this ball should not exceed v io . 3.2.6 low pin count (lpc) interface signal name (note 1) ball no. type description lpc_clk h1 i lpc clock. 33 mhz lpc bus shift clock. lpc_ad[3:0] k1, j1, j2, h2 i/o lpc address/data bus. this is the 4-bit lpc bus. address, control, and data are transferred on this bus between the geode cs5535 com- panion device and lpc devices. an external pull-up of 100 k ? is required on these balls (if used in lpc mode) to maintain a high level when the signals are in tri-state mode. from reset, these signals are not driven. lpc_ad3 is shared with gpio19. lpc_ad2 is shared with gpio18. lpc_ad1 is shared with gpio17. lpc_ad0 is shared with gpio16. see table 3-8 "gpio options" on page 47 for further details. lpc_drq# g1 i lpc dma request . this is the lpc dma re quest signal. peripherals requiring service pull it low and then place a serially-encoded requested channel number on this line to initiate a dma transfer. if the device wakes up from sleep, at least six lpc_clks must occur before this input is asserted. shared with gpio20. see table 3- 8 "gpio options" on page 47. tie high if selected as lpc_drq# but not used. amd geode? cs5535 companion device data book 45 signal definitions 31506b lpc_serirq g2 i/o lpc encoded irq . this is the lpc serial interrupt request line, used to report isa-style interrupt requests. it may be activated by either the geode cs5535 companion device or an lpc peripheral. an external pull-up of 100 k ? is required if this ball is used in lpc mode to maintain a high level when the signal is in tri-state. from reset, this signal is not driven. if the device wakes up from sleep, at least six lpc_clks must occur before this input is asserted if operating in quiet mode. shared with gpio21. see tabl e 3-8 "gpio options" on page 47. lpc_frame# h3 o lpc frame . this signal provides the active-low lpc frame signal used to start and stop transfers on the lpc bus. shared with gpio22. see tabl e 3-8 "gpio options" on page 47. note 1. all lpc signals, except lpc_clk are shared on gpio balls (see table 3-8 "gpio options" on page 47). the ge- ode cs5535 companion device powers up with this group of balls set to the lpc mode; to use them as gpios they must be explicitly reprogrammed. the lpc signals may be switched to gpios use via msr 51400015h (see sec- tion 6.6.2.11 "ball options contro l (divil_ball_opts)" on page 335). use reset_out# for lpc reset. use any gpio assigned as a pme for the lpc pme. use any gpio assigned as an smi for the lpc smi. use general sleep and standby controls (sleep_x, ball c2 and sleep_y, ball j3) in place of lpc_pd# for lpc power-down. 3.2.6 low pin count (lpc) interface signal name (note 1) ball no. type description 3.2.7 audio codec 97 interface signal name (note 1) ball no. type description ac_clk m1 i audio bit clock . the serial bit clock from the codec. the frequency of the bit clock is 12.288 mhz and is derived from the 24.576 mhz crystal input to the external audio codec. not required if audio not used; tie low. ac_s_out l2 o audio controller serial data out . this output transmits audio data to the codec. this data stream contains both control data and the dac audio data. the data is sent on the rising edge of the ac_clk. connect to the audio codec?s serial data input pin. bos1 i boot options select bit 1. during system reset, this ball is the msb of the 2-bit boot option (balls l2 and l3) and is used to determine the loca- tion of the system boot device. it should be pulled low if required by table 3-5 "boot options selection" on page 34, otherwise, an internal pull-up, asserted during reset, will pull it high. during reset, the ball output drivers are held in tri-state mode, and the ball is sampled on the rising edge of reset_out# (i.e., when external reset is de-asserted). after reset, this signal defaults low (off). ac_s_in l1 i audio controller serial data input. this input receives serial data from the audio codec. this data stream contains both control data and adc audio data. this input data is sampled on the falling edge of ac_clk.connect to the audio codec?s serial data output pin. 46 amd geode? cs5535 companion device data book signal definitions 31506b ac_s_sync l3 o audio controller sync. this is a 48 khz sync pulse that signifies the beginning of a serial transfer on ac_s_out, ac_s_in, and ac_s_in2. ac_s_sync is synchronous to the rising edge of ac_clk. connect to the audio codec?s sync pin. bos0 i boot options select bit 0. during system reset, this ball is the lsb of the 2-bit boot option (balls l2 and l3), used to determine the location of the system boot device. it should be pulled low if required by table 3-5 "boot options selection" on page 34, otherwise, an internal pull up, asserted during reset, will pull it high. during reset, the ball drivers are held in tri-state mode, and the ball is sampled on the rising edge of reset_out# (i.e., when external reset is de-asserted). after reset, this signal defaults low (off). ac_beep k3 o legacy pc/at speaker beep . connect to codec?s pc_beep. this function is only available when gpio1 is programmed to out_aux1. see table 3-8 "gpio options" on page 47. ac_s_in2 j3 i audio controller serial data input 2. this input receives serial data from a second codec. this data stream contains both control data and adc audio data. this input data is sampled on the falling edge of ac_clk. if the codec?s ready bit is set in this stream (slot 0, bit 15), then it is functionally ored with ac_s_in. connect to a second codec?s serial data output. this function is only available when gpio12 is programmed to in_aux1. see table 3-8 "gpio options" on page 47. note 1. use reset_out # for ac97 reset. 3.2.7 audio codec 97 interface (continued) signal name (note 1) ball no. type description amd geode? cs5535 companion device data book 47 signal definitions 31506b 3.2.8 gpios table 3-8 gives the dedicated functions associated with each gpio. these functions may be invoked by configuring the associated gpio to the in_aux1, out_aux1, or out_aux2 m odes. (the functions themselves are described in table 3- 9 "gpiox available functions descriptions" on page 49.) the column ?recommended use? is a guideline for system designers to assign gpio functionality. any gpio input can be mapped to an interrupt, asmi, or pme. details of configur- ing the gpios are given in section 6.16 "gpio subsystem register descriptions" on page 450. all gpios have selectable pull-up and/or pull-down resistors available on the output, except for those indicated by note 3 in the ?weak pu/pd? col- umn of table 3-8. table 3-8. gpio options gpio ball no. power domain buffer type post reset recommended use function programming options weak pu/pd i/o config in_aux1 out_aux1 note 1 note 1. see section 6.16.2.5 on page 458 for ball configuration. out_aux2 note 2 note 2. see section 6.16.2.6 on page 459 for ball configuration. gpio0 r2 w pci (note 3) note 3. no internal pull-up/down available. if not used, tie low. disabled pci_inta# (note 4) gpio1 k3 w q7 pu disabled --- ac_beep mfgpt0_c2 gpio2 b12 w ide (note 3) disabled --- ide_irq0 gpio3 e1 w smb (note 3) disabled ddc_scl (note 5) uart2 rx gpio4 e2 w smb (note 3) disabled ddc_sda (note 5) uart2 tx gpio5 d3 w q7 auto- sense (note 6) disabled --- mfgpt1_rs mfgpt0_c1 gpio6 d2 w q7 auto- sense (note 6) disabled --- mfgpt0_rs mfgpt1_c1 mfgpt2_c2 gpio7 c2 w pci (note 3) disabled pci_intb# (note 4) mfgpt2_c1 sleep_x gpio8 e3 w q7 pu disabled --- uart1_tx uart1_ir_tx gpio9 d1 w q7 pu disabled --- uart1_rx or uart1_ir_rx gpio10 c3 w q7 pu disabled --- (note 7) thrm_alrm# gpio11 a1 w q7 pu disabled --- slp_clk_en# mfgpt1_c2 gpio12 j3 w q7 pd disabled --- ac_s_in2 sleep_y gpio13 f2 w q7 pu disabled --- (note 7) sleep_but gpio14 g3 w smb (note 3) disabled --- (note 8) smb_clk_in smb_clk_out gpio15 f1 w smb (note 3) disabled --- (note 8) smb_data_in smb_data_out gpio16 h2 w pci (note 3) lpc (note 9) lpc_ad0 gpio17 j2 w pci (note 3) lpc (note 9) lpc_ad1 gpio18 j1 w pci (note 3) lpc (note 9) lpc_ad2 gpio19 k1 w pci (note 3) lpc (note 9) lpc_ad3 gpio20 g1 w pci (note 3) lpc (note 9) lpc_drq# gpio21 g2 w pci (note 3) lpc (note 9) lpc_serirq mfgpt2_rs gpio22 h3 w pci (note 3) lpc (note 9) lpc_frame# gpio24 c9 s smb (note 3) disabled --- work_aux gpio25 a9 s q7 pu/pd disabled --- low_bat# mfgpt7_c2 gpio26 b7 s q7 pu/pd disabled pme# (note 10) mfgpt7_rs gpio27 c8 s q7 pu/pd disabled --- mfgpt7_c1 32khz gpio28 a8 s q7 pu/pd input enabled (note 11) pwr_but# (note 12) pwr_but# (note 13) 48 amd geode? cs5535 companion device data book signal definitions 31506b note 4. any gpio can be used as an interrupt input without restrict ion. these particular gpios have pci i/o buffer types for com plete pci bus compatibility. however, such stri ct compatibility is generally not required. note 5. applications incorporating a crt often require support fo r the display data channel (ddc) serial interface. these partic ular gpios have open collector smb i/o buffer types required by the ddc interface specification. the ddc protocol supplied by amd is provided via software implementation and defaults to these gp ios. however, any design not needing strict ddc electrical sup- port can use other gpios. lastly, applications not incorporat ing ddc use at all may use these gpios without restriction. note 6. see section 5.15.5.6 "auto-sense" on page 165 for an explanation of auto-sense. note 7. internal signal is active high. us e gpio invert for active low external. note 8. when both in_aux1 and aux_outx are enabled, i/o direct ion on this ball is controlled by the smb controller. note 9. defaults to lpc use. use ba ll options msr (see table 3-6 on page 34) to switch this ball to gpio control. note 10. any gpio can be used as a power management event (pme) wakeup input without restriction. pmes are supported for both sl eep and standby wakeup. however, if standby wakeup is desired, a gpio on the standby power domain must be used. only gpio[24:28] are supplied via the standby powe r rail and are typically used as follows: gpio24 - auxiliary working power control gpio25 - low battery alarm gpio26 - pme gpio27 - mfgpt setup to provide a blink gpio28 - power button depending on application use, the pme function could be moved to gpio[24:27]. if only external pme wakeup from sleep is re- quired, the pme function could be moved to gpio[0:23]. lastly, the pme function coul d simply not be used, making more gpios available for other uses. note 11. gpioh_in_en (gpio offset a0h) and gpio h_in_aux1_sel (gpio offset b4h) are enabled. note 12. reset default. note 13. if the gpio28 function is desired, the power button func tionality in the pmc must be disabled before the in_aux1 functi on is dis- abled. amd geode? cs5535 companion device data book 49 signal definitions 31506b 3.2.8.1 gpio functions and recommended usage functions listed in table 3-9 are functions that may be assigned to specific gpio balls. the ?ball no.? column gives the ball that must be used if this function is selected, and the ?gpiox? column gives t he gpio that the function is associated with. table 3-9. gpiox available functions descriptions function name ball no. gpio[x] type description 32khz c8 gpio27 o 32 khz clock. when invoked, this ball produces a buffered output of the 32 khz clock provided on khz32_xci and khz32_xco (balls a4 and b3, respectively). this option is invoked by selecting the out_aux2 option of gpio27. note that since gpio27 is in the standby power domain, the 32 khz clock output will continue in sleep and standby states. ac_beep k3 gpio1 o legacy pc/at speaker beep . connect to codec?s pc_beep. ddc_scl e1 gpio3 i/o ddc serial clock. this is a ?recommended use? for gpio3, because this is one of the few gpios that have a high drive capac- ity, open-drain output. the serial clock function must be imple- mented in software to support ddc monitors. there is no dedicated ddc clock function within the geode cs5535 compan- ion device. ddc_sda e2 gpio4 i/o ddc serial data. this is a ?recommended use? for gpio4, because this is one of the few gpios that have a high drive capac- ity, open-drain output. the serial data function must be imple- mented in software to support ddc monitors. there is no dedicated ddc data function within the geode cs5535 compan- ion device. low_bat# a9 gpio25 i low battery detect. this is a ?recommended use? for gpio25 in battery-powered systems. it is in voked by setting gpio25 to the in_aux1 mode. the signal is intended to be driven low by an external circuit when the battery voltage falls below a preset value (determined by the external circuit). it could be used to generate a pme (interrupt) - connected to lowbat function in the power man- agement controller that would then de-assert working and work_aux, if no software action is taken within a programmable time. mfgpt0_c1 d3 gpio5 o multi-function general purpos e counter #0 - compare 1 out. an output from the counter that , when asserted, indicates the counter has reached the conditi ons set up in the counter?s compare 1 registers. mfgpt0_c2 k3 gpio1 o multi-function general purpos e counter #0 - compare 2 out. an output from the counter that , when asserted, indicates the counter has reached the conditi ons set up in the counter?s compare 2 registers. mfgpt0_rs d2 gpio6 i multi-function general purpose counter #0 - restart. an input to the counter that causes it to be reset to initial conditions and then to resume counting. mfgpt1_c1 d2 gpio6 o multi-function general purpos e counter #1 - compare 1 out. an output from the counter that , when asserted, indicates the counter has reached the conditi ons set up in the counter?s compare 1 registers. mfgpt1_c2 a1 gpio11 o multi-function general purpos e counter #1 - compare 2 out. an output from the counter that , when asserted, indicates the counter has reached the conditi ons set up in the counter?s compare 2 registers. 50 amd geode? cs5535 companion device data book signal definitions 31506b mfgpt1_rs d3 gpio5 i multi-function general purpose counter #1 - restart. an input to the counter that causes it to be reset to initial conditions and then to resume counting. mfgpt2_c1 c2 gpio7 o multi-function general purpos e counter #2 - compare 1 out. an output from the counter that , when asserted, indicates the counter has reached the conditi ons set up in the counter?s compare 1 registers. mfgpt2_c2 d2 gpio6 o multi-function general purpos e counter #2 - compare 2 out. output from the counter that, when asserted, indicates the counter has reached the conditions set up in the counter?s compare 2 registers. mfgpt2_rs g2 gpio21 i multi-function general purpose counter #2 - restart. an input to the counter that causes it to be reset to initial conditions and then to resume counting. mfgpt7_c1 c8 gpio27 o multi-function general purpos e counter #7 - compare 1 out. an output from the counter that , when asserted, indicates the counter has reached the conditi ons set up in the counter?s compare 1 registers. mfgpt7_c2 a9 gpio25 o multi-function general purpos e counter #7 - compare 2 out. an output from the counter that , when asserted, indicates the counter has reached the conditi ons set up in the counter?s compare 2 registers. mfgpt7_rs b7 gpio26 i multi-function general purpose counter #7 - restart. an input to the counter that causes it to be reset to initial conditions and then to resume counting. pci_inta# r2 gpio0 i pci interrupt a. this is a ?recommended use? for gpio0, because this gpio has a pci-compatible output type. pci_intb# c2 gpio7 i pci interrupt b. this is a ?recommended use? for gpio7, because this gpio has a pci-compatible output type. pme# b7 gpio26 i power management event. this is a ?recommended use? for gpio26. by mapping this gpio (or any other) to the pme# func- tion, the geode cs5535 companion device may be awakened from a sleep state when the mapped ball (in the recommended case, ball b7) is pulled low. table 3-9. gpiox available functions descriptions (continued) function name ball no. gpio[x] type description amd geode? cs5535 companion device data book 51 signal definitions 31506b pwr_but# a8 gpio28 i power button. this gpio can be mapped to the pmc ?button- push? event, that may be used to implement the power on and the four-second-delay power off functions. note that gpio28 comes up in the in_aux1 mode after reset, enabling this feature. any power button change on this input must be at least two khz32_xci edges (approximately 62 s) in duration to be cor- rectly detected. if spurious transitions smaller than this are possi- ble, then use on-chip gpio input filter function to insure proper operation. additionally, the rise or fall time on this input must be less than 10 s. if transition times longer than this are possible, then use the on-chip gpio input f ilter function to insure proper operation. from the first power-up of the standby power domain under which no filter is enabled, spurious transitions on the first high-to-low power button push are acceptable as long as the input is eventu- ally low at least two khz32_xci edges. additionally, transition times as slow as 1 ms are accept able for the first push. note that these relaxed requirements work bec ause this input is effectively a ?don?t care? at the hardware level after the first power-up until soft- ware enables use of the power button. before enabling use, the software can setup the gpio filt er or other functions as needed. per the discussion of the skip feature in section 5.17 "power management control" on page 172, this input may be tied to ground in order for the system to come on immediately when standby and working power are available. specifically, systems that do not incorporate a power button should tie this input to ground. one side effect of the skip feature, is that the platform design must insure that this input is not low when standby power is applied if the skip feature is not desired. specifically, systems that incorpo- rate use of a power button must insure that this input ramps to a high no more than 1 s behind v io_vsb ramp-up. failure to quickly establish a high on this input during power up could result in a spurious skip. see section 7.6 "skip parameter" on page 573 for ac timing. ac_s_in2 j3 gpio12 i audio controller serial data input 2. this input receives serial data from a second codec. this data stream contains both control data and adc audio data. this input data is sampled on the falling edge of ac_clk. if the codec?s ready bit is set in this stream (slot 0, bit 15), then it is functio nally ored with ac_sdata_in1. con- nect to second codec?s serial data output. slp_clk_en# a1 gpio11 o sleep clock enable. this signal is a control that is intended to be connected to the external system clock generator chip. the intended use is, when high, the clock generator runs; when low, the clock generator turns off. from reset, a pull-up makes this gpio high. the active state of this signal indicates that the geode cs5535 companion device is in the sleep state. sleep_but f2 gpio13 i sleep button. this gpio can be mapped to a pme ?button-push? type event and used to request the system software to put the sys- tem to sleep. table 3-9. gpiox available functions descriptions (continued) function name ball no. gpio[x] type description 52 amd geode? cs5535 companion device data book signal definitions 31506b sleep_x c2 gpio7 o sleep x. this general purpose power control output becomes active as the geode cs5535 companion device enters and exits various power management modes. it may be used by external devices to control their power states synchronous with power state changes in the geode cs5535 companion device. it may be con- figured as active high or active low. sleep_y j3 gpio12 o sleep y. this general purpose power control output becomes active as the geode cs5535 companion device enters and exits various power management modes. it may be used by external devices to control their power states synchronous with power state changes in the geode cs5535 companion device. it may be con- figured as active high or active low. smb_clk_in g3 gpio14 i smb clock in / smb clock out. this is the clock for the smb. in order to use it properly, the asso ciated gpio (gpio14) should be set to in_aux1 and out_aux1 simultaneously. the smb con- troller determines the direction (in or out) of the associated ball. smb_clk_out o smb_data_in f1 gpio15 i smb data in / smb data out. this is the data line for the smb. in order to use it properly, the asso ciated gpio (gpio15) should be set to in_aux1 and out_aux1 simultaneously. the smb con- troller determines the direction (in or out) of the associated ball. smb_data_out o thrm_alrm# c3 gpio10 i thermal alarm . when connected to an external thermal monitor, this input can act as a thermal fail-safe to shut down power by sig- nalling the power management controller to de-assert working and work_aux. set gpio10 to the in_aux1 mode to enable this feature. ide_irq0 b12 gpio2 i ide interrupt. indicates the external ide device has completed the dma operation. uart1_ir_tx e3 gpio8 o uart1 infrared transmit. this signal is the data output (tx) from the infrared mode of uart1. it is available when gpio8 is switched to the out_aux2 mode uart1_rx d1 gpio9 i uart1 receive or uart1 infrared receive. this signal is the data input (rx) to the uart1. it acts as the input in both ir and conventional modes of uart1. it is available when gpio9 is switched to the in_aux1 mode. uart1_ir_rx i uart1_tx e3 gpio8 o uart1 transmit. this signal is the data output (tx) from the con- ventional mode of uart1. it is available when gpio8 is switched to the out_aux1 mode. uart2_rx e1 gpio3 i uart2 receive. this signal is the data input (rx) to the uart2. it acts as the input of uart2. it is available when gpio3 is switched to the in_aux1 mode. uart2_tx e2 gpio4 o uart2 transmit. this signal is the data output (tx) from the con- ventional mode of uart2. it is available when gpio4 is switched to the out_aux1 mode. work_aux c9 gpio24 o working auxiliary. this output is intended to be used to control external power sources to all de vices except memory (which is intended to be controlled by working). work_aux de-asserts in synchronism with working. table 3-9. gpiox available functions descriptions (continued) function name ball no. gpio[x] type description amd geode? cs5535 companion device data book 53 signal definitions 31506b 3.2.9 debug and manufacturing test interface signal name ball no. type description tck n2 i jtag test clock. tms n3 i jtag test mode select. tdi p1 i jtag test data in. tdo p2 o, ts jtag test data out. from reset, this output is in tri-state mode. it is only enabled and driven when commanded to output or pass- through data per jtag standards. t_debug_in m2 i test debug input. input to the geodelink control processor (glcp) from the geode gx processor. t_debug_out m3 o test debug out. output from the geodelink control processor (glcp) to the geode gx processor. lvd_test b9 o low voltage detect test. manufacturing test only. no operational use. make no connection. test_mode a6 i test mode. manufacturing test only. no operational use. tie low. func_test f3 i functional test. manufacturing test only. no operational use. tie low. 54 amd geode? cs5535 companion device data book signal definitions 31506b 3.2.10 power, ground, and no connects signal name (note 1) ball no. type description v core d8, d10, h4, h14, k4, k14, p8, p10 pwr 1.2v or 1.5v (nominal) core power working connection (total of 8) v core_vsb a7 pwr 1.2v or 1.5v (nominal) core power standby connection v io d4, d6, d9, d12, d14, f4, f14, m4, m14, p4, p6, p9, p12, p14 pwr 3.3v (nominal) i/o power connection (total of 14) v io_vsb b6 pwr 3.3v (nominal) i/o power standby connection v ss d5, d7, d11, d13, e4, e14, g4, g14, j4, j14, l4, l14, n4, n14, p5, p7, p11, p13 gnd ground connection (total of 18) nc a2, a16, b1, b4, b5, c11, g15, h15, j15, k15, l15, m15, r3, r9, t2, u2, u15, u16, u17 --- no connection (total of 19). these lines must be left disconnected. connecting any or these lines to a pull-up/down resistor, an active sig- nal, power, or ground could cause unexpected results and possible malfunctions. note 1. for module specific power and ground signals see: section 3.2.1 "system interface signals" on page 36. section 3.2.4 "usb interface" on page 43. amd geode? cs5535 companion device data book 55 4 global concepts and features 31506b 4.0 global concepts and features 4.1 geodelink? architecture overview the information in this section provides a basic under- standing of the architecture used to internally connect geodelink? devices. the actual existence of architecture is generally invisible to the user and the system program- mer. amd core bios software provides all geodelink ini- tialization and support, including related model specific registers (msrs). additionally, this software provides a virtual pci configuration space that abstracts the architec- ture to industry standard interfaces. from this interface, all geodelink devices appear in one pci multi-function con- figuration space header on the external pci bus. 4.1.1 introduction this component is based on the geodelink packet archi- tecture. it consists of a set of geodelink devices and a geodelink control processor (glcp) connected through the geodelink interface unit (gliu). a simplified view of a gliu connected with three generic geodelink devices is illustrat ed in figure 4-1. the follow- ing points are relevant: all outputs from a geodelink device to the gliu are registered. all outputs from the gliu to a geodelink device are registered. furthermore, there are dedicated output registers for each geodelink device. geodelink device inputs from the gliu need not be registered, but they are buffered at the interface. all connections between the geodelink devices and gliu are dedicated point-to-point connections with one source and one load. there are no buses in tri-state mode. the gliu itself is a geodelink device and is always port 0. figure 4-1. simplified gliu with generic geodelink? devices ro ro ro hs hs hs do do do geodelink? device 1 geodelink device 2 geodelink device 3 p2d arb data mux gliu ri ri ri di di di ro - request out do - data out ri - request in di - data in hs - handshake p2d - physical to device descriptors arb - arbiter 56 amd geode? cs5535 companion device data book global concepts and features 31506b the gliu implements the ?bus?. transactions between geodelink devices and gliu are conducted with packets. the gliu accepts request packets from masters and routes them to slaves. similarly, slave response packets are routed back to the master. the bus is non-blocking. several requests can be pending, but order is guaranteed. broadcasts are not allowed. all packets have one source and one destination. 4.1.2 routing the physical to device (p2d) descriptors control the rout- ing of the packets. the descriptors are initialized by soft- ware at system setup. they establish the address map to be used by the system. they associate a memory or i/o address range with a gliu port. when a request packet arrives from a request out (ro) port, the address and other attributes in the packet are used to look up the destination port. if the port request in (ri) is available, the request is passed. if there are multiple requests, priorities are used to establish which requestor and destination port utilize the transfer cycle. a transfer from an ro to an ri takes one clock edge. 4.1.3 response packets earlier in this section, it was indicated that an ro can be used to present a write data packet or a read response packet. the use and need of a read response packet for a read request is obvious. however, there is also an optional write response packet. this tells the requestor that the write has completed. this is used to hold a processor i/o write instruction until the response is received, that is, i/o writes are never posted. memory writes are always posted. the response packet is also used to generate synchro- nous system management in terrupts (ssmis). system management mode (smm) is used for hardware emulation and other traps. an ssmi can be generated by a geodelink device or via special gliu descriptors. when the response arrives back at the processor, interface cir- cuits generate an smi to invo ke the smm software. lastly, all response packets contain an exception flag that can be set to indicate an error. amd geode? cs5535 companion device data book 57 global concepts and features 31506b 4.1.4 asmi and error two additional signals are needed to complete this geodelink architecture overview: asynchronous system management interrupt (asmi) and error. each geodelink device outputs these asmi and error signals. an asmi is much like a legacy interrupt, except it invokes the smm handler. as the name suggests, an asmi is an asynchronous event, while an ssmi is synchronous to the instruction that generated it. the error signal simply indicates some type of unexpected error has occurred. a device asserts this signal when an unexpected error occurs. in a normal operating system, this would not be asserted. for example, a disk read error or ethernet network error would be signaled using normal geodelink packet mechanisms. this signal is reserved for the truly unexpected. each geodelink device has mechanisms for enabling and mapping multiple internal sources down to these singular outputs. the mechanism consists of the logical ?or? of all enabled sources. the gliu receives the asmi and error pair from each geodelink device. it has the same ?or? and enable mechanism that finally results in a single asmi and error pair for the whole component (see figure 4-2). the asmi is routed to the processor, while the error is routed to the glcp. within the glcp, the error signal can be mapped into an asmi for routing back into the gliu. 4.1.5 topology the connection of the gliu to the seven geodelink devices of the geode cs5535 companion device is illus- trated in figure 4-3. note the port number of the geodelink device; by design convention, the gliu is always port 0. part of the physical to device (p2d) descriptor is a port number. when there is a hit on the descriptor address, the port number indicates which geodelink device to route the packet to. if there is no hit, then the packet is routed to the default port. for the geode cs5535 companion device, the default is always port 4, that is, the diverse device (dd). figure 4-2. geodelink? architecture asmi and error routing asmi & error asmi & error asmi & error asmi & error asmi & error asmi & error asmi & error asmi & error glcp usbc1 acc dd atac usbc2 glpci_sb gliu asmi & error companion device error to glcp debug or conversion to asm companion device asmi to processor enable enable or or 58 amd geode? cs5535 companion device data book global concepts and features 31506b 4.1.6 address spaces and msrs the gliu and geodelink devices support the traditional memory and i/o spaces. the memory space supports a traditional 32-bit byte address with associated byte enables. the i/o space is a 20-bit byte address with byte enables. i/o registers can be 8, 16, or 32 bits. the gliu has both memory and i/o p2ds for routing. in addition to the above spac es, there is a model specific register (msr) space that is tied to the geodelink topol- ogy. as introduced in the previous section, the gliu has eight ports with port 0 assigned to the gliu. an msr ?address? is relative to the device making a request to it and the topology between the requestor and the msr. thus, for the geode gx processor to address an msr in the geode cs5535 companion device, it specifies a series of ports that must be traversed to get there. once a specific device port is identified, additional address bits are avail- able to select a specific msr within a given device. msr space is functionally similar to pci configuration space. at boot time system initialization, the core bios (see section 4.1 "geodelink? architecture overview" on page 55) traverses the topology of the system to determine what is present. by convention, the first msr at each port is an id register that indica tes a specific device. once the core bios knows what is pr esent, it assigns devices to specific locations in the appropriate memory or i/o address space using msrs. generally, msrs are used to configure and set up geodelink devices, but are not used for ongo- ing operations. the ?assignment? msrs are located in the glius as ?descriptors?. the ?assignment descriptor? basically says: ?route a request packet containing address x to port y?. port y can be the final device or another gliu. this sec- ond gliu must have assignments to route address x to port z. this process continues until the final device port is specified. figure 4-3. amd geode? cs5535 companion device geodelink? architecture topology port 7 port 3 usbc2 req in data in req out data out diag glpci_sb req in data in req out data out diag atac req in data in req out data out diag dd req in data in req out data out diag glcp req in data in req out data out diag usbc1 req in data in req out data out diag acc req in data in req out data out diag gliu port 4 port 5 port 6 port 0 port 2 port 1 amd geode? cs5535 companion device data book 59 global concepts and features 31506b in addition to the ?positive? address decode above, each gliu has a subtractive port that takes all addresses not assigned to a specific port. there is always a default sub- tractive port path to the boot rom to allow the central pro- cessor to start executing code from time zero. thus, from system reset, there is a default memory address path that allows the first processor instruction fetch to: 1) proceed down through the two geode gx processor glius; 2) cross the pci bus to the geode cs5535 companion device; 3) proceed down through the geode cs5535 companion device gliu to the default port connected to the dd; and 4) access the boot device connected to the dd. 4.1.7 special cycles and bizzaro flag the bizzaro flag is used to indicate special cycles and exceptions to normal packet operation. a ll special cycles traverse the gliu system as i/o packets with the biz- zaro flag set. the special cycles are: 1) interrupt acknowledge: i/o read from address zero. 2) shutdown: i/o write to address zero. 3) halt: i/o write to address one. 4.2 msr addressing an msr address consists of the fields shown in table 4-1. when a gliu receives an msr packet, it routes the packet to the port specified in field 0 but shifts address bits [31:14] to the left by three bits and replaces bits [16:14] with zero. thus, field 1 is moved to field 0, field 2 is moved to field 1, etc. the address field always remains unchanged and selects one 64-bit msr per address value, that is, the address value 0 accesses one 64-bit register, the address value 1 accesses one 64-bit register, the address value 2 accesses one 64-bit register, etc. there are no msr byte enables. all 64 bits are always written and read. many geode cs5535 companion device msrs are only 32 bits in physical size. in thes e cases, interface logic dis- cards the upper 32 bits on writes and pads the upper 32 bits on reads. read padding is undefined. lastly, geode cs5535 companion device geodelink devices only decode enough bits of the address to select one of n msrs, where n is the total number of msrs in the device. for example, if a geodelink device has only 16 msrs, then the addresses 0x2001, 0x0201, 0x0021, and 0x0x0001 all access msr number 1, while the addresses 0x200f, 0x020f, 0x002f, and 0x0x000f all access msr number 15. to access a given geodelink device, use table 4-2 "msr addresses from amd geode? gx processor" on page 60. note the target device addresses: glpci_sb 5100xxxxh gliu 5101xxxxh usbc2 5120xxxxh atac 5130xxxxh dd 5140xxxxh acc 5150xxxxh usbc1 5160xxxxh glcp 5170xxxxh the xxxx portion refers to the msr addresses as they appear any place within section 6.0 "register descrip- tions" on page 199. to form a complete msr address, ?or? an address provided in a register description section with the appropriate address above. table 4-1. msr routing conventions routing field 0 routing field 1 routing field 2 routing field 3 routing field 4 routing field 5 address field bits [31:29] bits [28:26] bits [25:23] bits [22:20] bits [19:17] bits [16:14] bits [13:0] 60 amd geode? cs5535 companion device data book global concepts and features 31506b table 4-2. msr addresses from amd geode? gx processor routing field 0 routing field 1 routing field 2 routing field 3 routing field 4 routing field 5 geodelink? device target name & address comment bits [31:29] bits [28:26] bits [25:23] bits [22:20] bits [19:17] bits [16:14] these bits are sh ifted off to the left and never enter the geode cs5535 companion device. these bits are shifted into posi- tions [31:23] by the time they reach the geode cs5535 com- panion device. bits in positions [22:14] are always 0 after shift- ing. 010 100 010 000 000 000 glpci_sb 5100xxxxh this all-zero convention indi- cates to the glpci_sb that the msr packet coming across the pci bus is actually for the glcpi_sb. 010 100 010 000 non-zero value gliu 5101xxxxh this non-zero convention indi- cates to the glpci_sb that the msr packet coming across the pci bus should be forwarded to the gliu. the gliu only looks at [22:20] and hence, keeps the packet. 010 100 010 001 any value illegal the gliu can not send any packets back to the port it came from. 010 100 010 010 any value usbc2 5120xxxxh 010 100 010 011 any value atac 5130xxxxh 010 100 010 100 any value dd 5140xxxxh 010 100 010 101 any value acc 5150xxxxh 010 100 010 110 any value usbc1 5160xxxxh 010 100 010 111 any value glcp 5170xxxxh amd geode? cs5535 companion device data book 61 global concepts and features 31506b 4.3 typical geodelink? device a typical or ?generic? geode cs5535 companion geodelink device is illustrated in figure 4-4 along with internal and external connections. the geodelink device consists of the native bloc k, geodelink adapter, msrs, and clock control units (ccu). each of these is discussed in the following paragraphs. before going into the blocks of the typical device, it should be noted that the following modules in the geode cs5535 companion device follow this model very closely: ? ac97 controller (acc) ? ata-5 controller (atac) ? diverse device (dd) specifically, they all use the geodelink adapter. the native block performs the ?useful? work for the device. for example, in a serial port device, the transmit parallel to serial shift register is located in this block. the native block connects to the outside world, that is, external devices, via the i/o cells and pads. the native block contains registers that are manipulated by software to perform the ?work?. these are operational registers that are typically manipu- lated by device drivers. the native blocks are covered in detail in the corresponding module?s register descriptions. the geodelink adapter sits between the gliu and the local bus. the local bus is a traditional address/data bus supporting geodelink adapter to native block transactions (slave transactions) and native block to geodelink adapter transactions (master transactions). however, it is a single transaction bus in that any given slave or master transaction runs to completion before another transaction can start. this is compatible with the native blocks listed above (i.e., acc, atac, and dd), which are all single transaction devices. as suggested by figure 4-4, the geodelink adapter contains no registers and is strictly speaking, just a bridge. the msrs are conceptually separate from the native block and geodelink adapter and generally provide overall geodelink device configuration and control. in most designs they are physically separated as shown. there are six standard msrs that are det ailed in section 4.8 "stan- dard geodelink? device msrs". all geodelink devices have these standard msrs. geodelink devices may also incorporate additional msrs as appropriate. on the upper right of the figure, the connections between the geodelink adapter and gliu are illustrated. all of these signals were covered previously in section 4.1 "geodelink? architecture overview". the clock control units (ccu) are key components in the active hardware clock gating (ahcg) infrastructure. they provide the mechanism for turning off clocks to sections of logic that are not busy . furthermore, they take an asyn- chronous global reset signal and synchronize it to the applicable clock domain. figure 4-4. typical geodelink? device msrs native block native block registers geodelink? adapter gliu msrs reg in data in reg out data out diag asmi err other device ccu ccu ccu local bus interface busy signals to glcp geodelink? device side-band signals to other native blocks external device interface i/o cells & pads geodelink? device clock local bus clock native block clock global internal reset connections 62 amd geode? cs5535 companion device data book global concepts and features 31506b 4.4 embedded pci adapter a geodelink device with an embedded pci bus is illus- trated in figure 4-5. note the similarity with figure 4-4 on page 61. the only difference is the pci adapter located in the center of the figure. t he pci adapter allows a module designed for the pci bus to be easily embedded in a geodelink architecture. it is used to embed the usb core into the geodelink architecture. the pci adapter provides the following features: converts geodelink adapter local bus transactions to/from pci bus transactions. provides pci bus configuration transactions from geodelink device msr transactions. performs pci bus protocol checking and sets the geodelink device error flag if appropriate. capable of responding to both single data phase as well as burst transactions. closely follows the functioning of the geodelink adapter. capable of issuing retries to the master when the local bus side is taking to long to complete the current trans- action. safely handles all the error conditions possible during normal and configuration pci transactions. using the virtual pci configuration space (see section 4.1 "geodelink? architecture overview" on page 55), the core bios lifts this embedded physical interface into the multi-function pci configuration space header. figure 4-5. geodelink? device with embedded pci bus msrs native block native block registers pci adapter reg in data in reg out data out diag asmi err ccu ccu ccu local bus interface geodelink? device side-band signals to other native blocks external device interface i/o cells & pads geodelink? adapter embedded pci bus interface amd geode? cs5535 companion device data book 63 global concepts and features 31506b 4.5 clock considerations 4.5.1 clock domain definitions table 4-3 lists the clock sources and domains for the geode cs5535 companion device. table 4-3. clock sources and clock domains component pin domain name description mhz66_clk atac_lb atac local bus and atac core inverted mhz66_clk (note 1) note 1. the mhz66_clk is first inverted and then fed to all these domains. gliu_gld gliu geodelink device interface and related logic gliu_stat gliu statistics counters glpci_gld glpci_sb geodelink device interface and related logic usbc2_gld usbc2 geodelink device interface and related logic atac_gld atac geodelink device interface and related logic dd_gld dd geodelink device interface and related logic acc_gld acc geodelink device interface and related logic usbc1_gld usbc1 geodelink device interface and related logic glcp_gld glcp geodelink device interface and related logic mhz66_clk divided by two (note 2) note 2. each domain receives the referenced cl ock and performs the divide just before the ccu. usbc2_lb usbc2 local bus interface and related logic acc_lb acc local bus interface and related logic usbc1_lb usbc1 local bus interface and related logic pci_clk glpci_trna glpci_sb transaction processing glpci_intf glpci_sb interface to pci bus glcp_pci glcp pci related logic mhz48_clk usbc2_cor usbc2 core logic usbc1_cor usbc1 core logic mhz48_clk divided by two (note 2) smb_cor smb controller core logic uart1_cor uart1 core logic uart2_cor uart2 core logic lpc_clk dd_lb dd local bus interface and related logic; includes pic lpc_cor lpc controller core logic pit_cor pit core logic dma_cor 8237 dma core logic ac_clk acc_cor acc core logic mhz14_clk (note 3) note 3. this clock differs from other clocks in this table in that this clock does not utilize a ccu nor is it subject to glcp c ontrol or power management control. mfgpt_cor_14m mfgpt core logic14 mhz clock pmc_slp power management controller sleep logic pit_ref programmable interval timer reference clock khz32_xci (note 3) rtc_cor rtc core logic mfgpt_cor_32k mfgpt core logic 32 khz clock mfgpt_cor_32k_s mfgpt 32khz clock source; standby power domain pmc_stb pmc standby logic; standby power domain gpio_cor gpio core logic gpio_cor_s gpio core logic; standby power domain tck (note 3) tap_cntrl jtag tap controller clock source (note 4) note 4. this logic does not have a fixed clock source. during debug it is switched to the clock domain of interest. it does have a ccu. glcp_dbg glcp debug logic 64 amd geode? cs5535 companion device data book global concepts and features 31506b 4.5.2 clock controls and setup each of the clock domains listed in table 4-3 on page 63 is subject to various glcp co ntrols and stat us registers except those with ?note 3?. these registers and a brief description of each is provided: glcp clock active (glcp_clkactive), msr 51700011h: a 1 indicates the corresponding clock is active. this is a read only register. glcp clock control (glcp_clkoff), msr 51700010h: a 1 indicates the corresponding clock is to be disabled immediately and unconditionally. not normally used operationally. debug only. glcp clock mask for debug clock stop action (glcp_clkdisable), msr 51700012h: a 1 indicates the corresponding clock is to be disabled by debug logic via a debug event or trigger. not normally used opera- tionally. debug only. glcp clock active mask for suspend acknowledge (glcp_clk4ack), msr 51700013h: a 1 indicates the corresponding clock is to be monitored during a power management sleep operation. when all the clocks with associated 1s go inactive, the glcp sends a sleep acknowledge to the power management controller. this register is used during sleep sequences and requires the clk_dly_en bit in glcp_glb_pm (msr 5170000bh[1]) to be 0. glcp clock mask for sleep request (glcp_pmclkdisable), msr 51700009h: a 1 indi- cates the corresponding clock is to be disabled uncondi- tionally during a power management sleep operation. clocks are disabled when the glcp completes all of its sleep request operations and sends a sleep acknowl- edge to the power management controller. all of the registers above have the same layout, where each bit is associated with a clock domain. the layout and recommended operating values for the registers is pro- vided in table 6-73 "clock mapping / operational settings" on page 536. 4.5.2.1 additional setup operations glcp debug clock control (glcp_dbgclkctl), msr 51700016h: set all bits to 0. this turns off all clocks to debug features; not needed during normal operation. glcp global power management control (glcp_glb_pm), msr 5170000bh: set all bits to 0. this disables the use of the fixed delay in glcp_clk_dis_delay and enables the use of glcp_clk4ack. glcp clock disable delay value (glcp_clk_dis_delay), msr 51700008h: set all bits to 0. since use of this register is disabled by setting all glcp_dbgclkctl bits to 0, the actual value of this register is a ?don?t care?; it is set here for completeness. if use of glcp_clk_dis_del ay is desired, set the clk_dly_en bit in glcp_glb_pm (msr 5170000bh[1] = 1). this will disable the use of glcp_clk4ack and shut off the clocks in glcp_pmclkdisable after the glcp_clk_dis_delay expires. this delay is measured in pci clock edges. amd geode? cs5535 companion device data book 65 global concepts and features 31506b 4.6 reset considerations the elements that effect ?reset? within the geode cs5535 companion device are illustrated in figure 4-6 on page 66. the following points are significant: signals denoted in upper case (i.e., all capitals) are external pins. signals denoted in lower case are internal signals. there are separate resets for the working power domain (reset_work#) and the standby power domain (reset_stand#). all elements in the figure are within the standby power domain and operate off the khz32_clk. the tap controller is in the working power domain, but it may be reset separately from the other working domain logic. any time the geode cs5535 companion device is in the standby state, the working power domain is uncondi- tionally and immediately driven into reset. any faulted event or external reset input forces the geode cs5535 companion device into the standby state. external reset (reset_out #) is always asserted immediately with internal working domain reset. deas- sertion is also immediate unless the event is a wakeup from a soft off condition (see section 5.17.3.4 "wakeup events" on page 178 for details). reset_out# asserts without any clocks but requires the khz32_clk for the delay and the pci_clk to de-assert. ide_reset# is always asse rted immediately with internal working domain reset and de-asserts when the atac comes out of reset, that is, within a few mhz66_clk edges of internal reset de-assert. lvd monitors v core and only asserts power_good_working when v core is within normal operating range. lvd monitors v core_vsb and v io_vsb along with reset_stand#. the assertion of power_good_standy only occurs when the voltages are within normal oper- ating range and reset_stand# is high, that is, de- asserted. when power is applied to the geode cs5535 companion device from a completely cold start, that is, no standby or working power, both reset_stand# and reset_work# are applied. alte rnatively, one or both of the reset inputs may be tied to standby i/o power (v io_vsb ), and the lvd circuit will generate internal power good working and internal power good standby. assum- ing the lvd circuit is enabled (lvd_en# pin tied low), power good standby will assert until proper standby volt- ages have been achieved and reset_stand# has been de-asserted. reset_out# is de-asserted synchronous with the low-to- high edge of pci_clk. the de-assertion is delayed from internal_reset using a counter in the power management controller. this counter is driven by the 32 khz clock and is located in the standby power domain. the value of the counter is programmable but defaults to 0x0_0100 (256 edges). 31.25 s per edge times 256 equals an 8 ms delay. note this counter default is established by reset_stand# and is not effected by reset_work#. therefore, the delay value may be changed and then the system can be reset with the new value. note the special consideration for tap controller reset. when boundary scan is being performed, internal compo- nent operation is not possible due to the scanning signals on the i/os. under this condition, it is desirable to hold the component internals in reset while the boundary scan is being performed by the tap controller. however, under normal operation, it is desirable to reset the tap controller with the other logic in the working domain during power management sequences. achieving these dual goals is accomplished as follows: for boundary scan: assert reset_stand#, causing internal power_good_standby to go low. this causes the complete component to reset, except for the tap controller. keep this input held low throughout boundary scan operations. assert and de-assert r eset_work# as needed to reset the tap controller. for normal operation: the internal power good standby will be high, meaning the tap controller reset asserts any time the standby state is active or anytime reset_work# is active. 66 amd geode? cs5535 companion device data book global concepts and features 31506b figure 4-6. reset logic faulted event capture power manage standby state controller faulted event status & immediately enter standby state unconditionally fail-safe power off alarm thermal alarm low power alarm shutdown special cycle mfgpt watchdog divil bad packet glcp soft reset divil soft reset working power fail reset_work# normal software request for standby state working work_aux standby state 32khz_clk de-assert delay pci_clk dq reset_out# lv d (low voltage detect) v core v core_vsb v io_vsb reset_stand# ata controller ide_reset# internal reset to all working domain logic except tap controller power good working power good standby (standby domain reset when low) tap controller reset standby_state amd geode? cs5535 companion device data book 67 global concepts and features 31506b 4.7 memory and i/o map overview 4.7.1 introduction there are several places in the geode cs5535 companion device where addresses are decoded and routed: physical pci bus. the glpci_sb decodes pci bus transactions and claims them with a ?devsel#? as appropriate. after claiming a transaction, the glpci_sb converts it to a gliu request packet. it then passes the request to the gliu. it has no routing control or respon- sibility beyond this point. gliu. the gliu compares the request addresses against the descriptor settings. it passes the request to the port associated with the compare hit. each port is connected to a specific geodelink device (see section 4.1.5 "topology" on page 57 for port assignment). there are also specific legacy addresses that receive ?special? routing beyond the standard descriptor routing mecha- nisms. typical geodelink device. for most geodelink devices, further decoding is minimal. if a device contains only msrs and a single native block (register group) in i/o or memory space, specific bits within the request packet can be used to easily select between the two. if a device contains more than one register group, a local base address register (lbar) for each group is used. like a pci base address register (bar), an lbar compare and hit operation is used to select the desired group. diverse device. the diverse device has the same decoding responsibilities as a typical geodelink device. beyond this programmable lbar decoding, it has substantial fixed decoding associated with legacy addresses. 4.7.2 pci bus decoding from reset, the glpci_sb does not actively decode any cycle. however, it does su btractively decode all cycles. from reset, any cycle not positi vely claimed on the pci bus is converted to a gliu request and passed to the gliu. using appropriate setup registers, the glpci_sb can be programmed to actively decode selected i/o and memory regions. other than actively claiming, the ?convert? and ?pass? operation is the same. there are control bits in glpci_ctl (msr 51700010h) to regulate behavior associated with legacy addresses: bits [12:11]: legacy i/o space active decode. these bits control the degree to which the glpci_sb actively claims i/o region 0000h through 03ffh: ? 00: subtractive ? claim on fourth clock. (default.) ? 01: slow ? claim on third clock. ? 10: medium ? claim on second clock. bit 13: reject primary ide. if this bit is set, the glpci_sb will not actively decode the primary ide addresses of 01f0h/01f7h and 03f6h. bit 14: reject secondary ide. if this bit is set, the glpci_sb will not actively decode the secondary ide addresses of 0170h/0177h and 0376h. bit 15: reject dma high page active. if this bit is set, the glpci_sb will actively decode the i/o range 0480h/048fh associated with the dma high page regis- ters. for further details on the glpci_ctl register see section 6.2.2.1 "global control (glpci_ctrl)" on page 234. lastly, there is an ?msr access mailbox? located in pci configuration register space. it consists of the following 32- bit registers: msr address (pci index f4h). full msr routing path in the upper portion plus 14 device address bits in the lower portion. msr data low (pci index f8h). bits [31:0]: when read, an msr cycle is generated. the 64-bit read returns the low 32 bits and saves the upper 32 bits for a read to ?data high?. a write holds the value written as the current ?data low?. msr data high (pci index fc h). bits [63:32]: reads return the upper 32 bits of the last msr value read. writes generate an msr write cycle using the current value and the ?data low? value. for further details on the msr access mailbox see section 6.2.3 "pci configuratio n registers" on page 240. 4.7.3 gliu decoding from reset, the gliu passes all request packets to the diverse device, except for the legacy primary ide addresses (01f0h/01f7h and 03f6h), these are passed to the ide device in the atac. there is a gliu iod_sc descriptor to control this primary ide behavior and it defaults configured (see se ction 6.1.4.2 "iod swiss cheese descriptors (gliu_iod_sc[x])" on page 226). if this descriptor is disabled, all requests pass to the diverse device. using appropriate msr setup registers (descriptors), the gliu can be programmed to route selected i/o and mem- ory regions to specific geodelink devices. any memory or i/o address that does not hit one of these regions, subtrac- tively routes to the diverse device. unlike pci, there is no performance loss associated with being the subtractive port. operationally, there are five bus masters within the geode cs5535 companion device: atac, acc, dd, usbc1, and usbc2. these masters only generate requests to access main memory off the geode gx processor. therefore, all their gliu requests need to be routed to the glpci_sb for presentation to the pci bus. a set of gliu p2d_bm descriptors could be used for this purpose. however, the geode cs5535 companion device gliu is uniquely modi- fied to route all requests for the listed masters to the 68 amd geode? cs5535 companion device data book global concepts and features 31506b glpci_sb unconditionally. therefore, gliu p2d_bm set- tings do not affect packet routing from the listed masters. gliu descriptors are only used to route requests from the glpci_sb and glcp. 4.7.4 legacy keyboard emulation in the geode cs5535 companion device, there are two usb controllers and hence two copies of this hardware. the usb control registers ar e memory mapped. the mem- ory region associated with these registers is relocatable via standard gliu descriptor msrs starting at an appropriate base address. the region size is 4 kb (1000h), that is, an offset range of 000h through ff fh. there are four registers called: hcecontrol, hceinpu t, hceoutput, and hcestatus. there are no usb control registers above this region. special consideration is given to the legacy keyboard emu- lation control registers normally associated with the usb controller. this ?normal? association is due to the fact that ?normally?, the keyboard emulation hardware is physically located with the usb hardware, even though there is no logical association between the two at the hardware level. this ?normal? association is driven by industry standard device drivers that group the two register sets in the same region. the keyboard emulation registers are located at the usb base address plus 0100h. a single copy of the keyboard emulation logic (kel) hard- ware is located in the diverse device (dd) module, where it can be closely coordinated with a possible real keyboard controller in any of three locations: in either usb controller (usbc1 or usbc2), or on the lpc bus. this leaves the problem of the control registers that are physically in the dd, but logically (from the software perspective) in the usb controller. a descriptor type is incorporated into the geode cs5535 companion device to deal with this keyboard issue. it is a variant of the standard ?p2d base mask descriptor? (p2d_bm) called p2d_bmk (keyboard). a p2d_bmk descriptor does additional decoding based on address bit 8. if this bit is low, the hit directs to the usb port. if this bit is high, the hit directs to the subtractive port. there are two p2d_bmk descriptors in the geode cs5535 companion device (see section 6.1.2.2 "p2d base mask kel descrip- tors (gliu_p2d_bmk[x])" on page 210). 4.7.5 geodelink? device decoding except diverse device table 4-4 shows the register space map for all geode cs5535 companion devices except the diverse device. there are no fixed addresses associated with these devices other than the msrs and the legacy ide i/o addresses as detailed in sect ion 4.7.3 "gliu decoding" on page 67. 4.7.6 diverse device decoding except legacy i/o the diverse device register space map except legacy i/o is shown in table 4-5 on page 69. table 4-4. register space map except diverse device device msr space (note 1) i/o space memory space glpci_sb standard geodelink device msrs plus glpci_sb setup. all msrs also accessi- ble from pci configuration space. none. none. glcp standard geodelink device msrs plus diagnostic and debug. none. none. gliu standard geodelink device msrs plus descriptor setup. programmable ssmis. programmable ssmis. acc standard geodelink device msrs. 16-byte codec interface plus a 48-byte master interface. all trap registers removed. generates no ssmis. the register space can be here also. atac standard geodelink device msrs plus timing parameters. bus master lbar. legacy primary addresses. 16-byte master interface. none. usbc1 standard geodelink device msrs plus pci configuration emulation. must set pci bar in usb controller. none. 4 kb, but less than 256 bytes used. keyboard emulation reg- isters to diverse device. usbc2 standard geodelink device msrs plus pci configuration emulation. must set pci bar in usb controller. none. 4 kb, but less than 256 bytes used. keyboard emulation reg- isters to diverse device. note 1. see section 4.8 "standard geodelink? devi ce msrs" on page 74 for register descriptions. amd geode? cs5535 companion device data book 69 global concepts and features 31506b table 4-5. diverse device register space map except legacy i/o device msr space (note 1) i/o space memory space dd standard geodelink device msrs plus: smb lbar, acpi lbar, pm lbar, gpio lbar, mfgpt lbar, nand lbar, kel lbar, kel lbar, irq mapper lbar, legacy controls, dma mappers, shadow registers, lpc controls, and memory mask. nor flash address control. located by associated lbar. defaults disabled. 008 bytes smb, 016 bytes acpi, 064 bytes pm support, 256 bytes gpio and icfs, 064 bytes mfgpts, 016 bytes nand flash, and 032 bytes irq mapper. all i/o that does not hit one of the items above and does not hit a legacy address, is directed to the lpc bus. 16-byte kel host controller reg- ister set at lbar. defaults dis- abled. nor flash per lbar. all other memory accesses are directed to the lpc bus. note 1. see section 4.8 "standard geodelink? devi ce msrs" on page 74 for register descriptions. 70 amd geode? cs5535 companion device data book global concepts and features 31506b 4.7.7 legacy i/o decoding table 4-6 details the legacy i/o range for 000h through 4ffh. each i/o location has a read/write (r/w) capability. note the following abbreviations: --- unknown or can not be determined. yes read and write the register at the indicated location. no shadow required. wo write only. value written can not be read back. reads do not contain any useful information. ro read only. writes have no effect. shw the value written to the register can not be read back via the same i/o location. read back is accomplished via a ?shadow? register located in msr space. shw@ reads of the location return a constant or meaningless value. shw$ reads of the location return a status or some other meaningful information. rec writes to the location are ?recorded? and written to the lpc. reads to the location return the recorded value. the lpc is not read. table 4-6. legacy i/o: 000h-4ffh i/o addr. function size r/w comment 000h slave dma address - channel 0 8-bit yes 16-bit values in two transfers. 001h slave dma counter - channel 0 8-bit yes 16-bit values in two transfers. 002h slave dma address - channel 1 8-bit yes 16-bit values in two transfers. 003h slave dma counter - channel 1 8-bit yes 16-bit values in two transfers. 004h slave dma address - channel 2 8-bit yes 16-bit values in two transfers. 005h slave dma counter - channel 2 8-bit yes 16-bit values in two transfers. 006h slave dma address - channel 3 8-bit yes 16-bit values in two transfers. 007h slave dma counter - channel 3 8-bit yes 16-bit values in two transfers. 008h slave dma command/status - channels [3:0] 8-bit shw$ 009h slave dma request - channels [3:0] 8-bit wo reads return value b2h. 00ah slave dma mask - channels [3:0] 8-bit shw@ reads return value b2h. 00bh slave dma mode - channels [3:0] 8-bit shw@ reads return value b2h. 00ch slave dma clear pointer - channels [3:0] 8-bit wo reads return value b2h. 00dh slave dma reset - channels [3:0] 8-bit wo reads return value b2h. 00eh slave dma reset mask - channels [3:0] 8-bit shw@ reads return value b2h. 00fh slave dma general mask - channels [3:0] 8-bit shw@ reads return value b2h. 010h-01fh no specific usage --- --- 020h pic master - command/status 8-bit shw$ 021h pic master - command/status 8-bit shw$ 022h-03fh no specific usage --- --- 040h pit ? system timer 8-bit shw$ 041h pit ? refresh timer 8-bit shw$ 042h pit ? speaker timer 8-bit shw$ 043h pit ? control 8-bit shw$ 044h-05fh no specific usage --- --- 060h keyboard/mouse - data port 8-bit y es if kel memory offset 100h[0] = 1 (emulationenable bit). if msr 5140001fh[0] = 1 (snoop bit) and kel memory offset 100h[0] = 0 (emulationenable bit). 061h port b control 8-bit yes amd geode? cs5535 companion device data book 71 global concepts and features 31506b 062h-063h no specific usage --- --- 064h keyboard/mouse - command/ status 8-bit yes if kel memory offset 100h[0] = 1 (emulationenable bit). if msr 5140001fh[0] = 1 (snoop bit) and kel memory offset 100h[0] = 0 (emulationenable bit). 065h-06fh no specific usage --- --- 070h-071h rtc ram address/data port 8- bit yes options per msr 51400014h[0]. (note 1) 072h-073h high rtc ram address/data port 8-bit yes options per msr 51400014h[1]. 074h-077h no specific usage --- --- 078h-07fh no specific usage --- --- 080h post code display 8-bit rec write lpc and dma. read only dma. 081h dma channel 2 low page 8-bit rec upper addr bits [23:16]. write lpc and dma. read only dma. 082h dma channel 3 low page 083h dma channel 1 low page 084h-086h no specific usage 8-bit rec write lpc and dma. read only dma. 087h dma channel 0 low page 8-bit rec upper addr bits [23:16]. write lpc and dma. read only dma. 088h no specific usage 8-bit rec wr ite lpc and dma. read only dma. 089h dma channel 6 low page 8-bit rec upper addr bits [23:16]. write lpc and dma. read only dma. 08ah dma channel 7 low page 08b dma channel 5 low page 08ch-08eh no specific usage 8-bit rec write lpc and dma. read only dma. 08fh dma c4 low page 8-bit rec upper addr bits [23:16]. see com- ment at 080h. 090h-091h no specific usage --- --- 092h port a 8-bit yes if kel_porta_en is enabled, then access port a; else access lpc. 093h-09fh no specific usage --- --- 0a0h pic slave - command/status 8-bit shw$ 0a1h pic slave - command/status 8-bit shw$ 0a2h-0bfh no specific usage 8-bit --- 0c0h master dma address - channel 4 8-bit yes 16-bit values in two transfers. 0c1h no specific usage 8-bit --- 0c2h master dma counter - channel 4 8-bit yes 16-bit values in two transfers. 0c3h no specific usage 8-bit --- 0c4h master dma address - channel 5 8-bit yes 16-bit values in two transfers. 0c6h master dma counter - channel 5 8-bit yes 16-bit values in two transfers. table 4-6. legacy i/o: 000h-4ffh (continued) i/o addr. function size r/w comment 72 amd geode? cs5535 companion device data book global concepts and features 31506b 0c7h no specific usage 8-bit --- 0c8h master dma address - channel 6 8-bit yes 16-bit values in two transfers. 0cah master dma counter - channel 6 8-bit yes 16-bit values in two transfers. 0cbh no specific usage 8-bit --- 0cch master dma address - channel 7 8-bit yes 16-bit values in two transfers. 0cdh no specific usage 8-bit --- 0ceh master dma counter - channel 7 8-bit yes 16-bit values in two transfers. 0cfh no specific usage 8-bit --- 0d0h master dma command/status - channels [7:4] 8-bit shw$ 0d1h no specific usage 8-bit --- 0d2h master dma request - channels [7:4] 8-bit wo 0d3h no specific usage 8-bit --- 0d4h master dma mask - channels [7:4] 8-bit yes 0d5h no specific usage 8-bit --- 0d6h master dma mode - channels [7:4] 8-bit shw@ 0d7h no specific usage 8-bit --- 0d8h master dma clear pointer - channels [7:4] 8-bit wo 0d9h no specific usage 8-bit --- 0dah master dma reset - channels [7:4] 8-bit wo 0dbh no specific usage 8-bit --- 0dch master dma reset mask - channels [7:4] 8-bit wo 0ddh no specific usage 8-bit --- 0deh master dma general mask - channels [7:4] 8-bit shw@ 0dfh no specific usage 8-bit --- 0e0h-2e7h no specific usage --- --- 2e8h-2efh uart/ir - com4 8-bit --- msr bit enables/disables into i/o space.(uart1 msr 51400014h[18:16], uart2 msr 51400014h[22:20]). defaults to lpc. 2f0h-2f7h no specific usage --- --- 2f8h-2ffh uart/ir - com2 8-bit --- msr bit enables/disables into i/o space.(uart1 msr 51400014h[18:16], uart2 msr 51400014h[22:20]). defaults to lpc. 300h-36fh no specific usage --- --- 370h floppy status r a 8-bit ro second floppy. 371h floppy status r b 8-bit ro second floppy. 372h floppy digital out 8-bit shw@ second floppy. 373h no specific usage 8-bit --- 374h floppy cntrl status 8-bit ro second floppy. 375h floppy data 8-bit yes second floppy. 376h no specific usage 8-bit --- table 4-6. legacy i/o: 000h-4ffh (continued) i/o addr. function size r/w comment amd geode? cs5535 companion device data book 73 global concepts and features 31506b 377h floppy conf reg 8-bit shw$ second floppy. 378h-3e7h no specific usage --- --- 3e8h-3efh uart/ir - com3 8-bit --- msr bit enables/disables into i/o space.(uart1 msr 51400014h[18:16], uart2 msr 51400014h[22:20]). defaults to lpc. 3f0h floppy status r a 8-bit ro first floppy. 3f1h floppy status r b 8-bit ro first floppy. 3f2h floppy digital out 8-bit shw@ first floppy. 3f3h no specific usage 8-bit --- 3f4h floppy cntrl status 8-bit ro first floppy. 3f5h floppy data 8-bit yes first floppy. 3f6h no specific usage 8-bit --- 3f7h floppy conf reg 8-bit shw$ first floppy. 3f8h-3ffh uart/ir - com1 8-bit --- msr bit enables/disables into i/o space.(uart1 msr 51400014h[18:16], uart2 msr 51400014h[22:20]). defaults to lpc. 400h-47fh no specific usage --- --- 480h no specific usage 8-bit wo write lpc and dma. read only dma. 481h dma channel 2 high page 8-bit rec upper addr bits [31:24]. write lpc and dma. read only dma. 482h dma channel 3 high page 483h dma channel 1 high page 484h-486h no specific usage 8-bit wo write lpc and dma. read only dma. 487h dma channel 0 high page 8-bit rec upper addr bits [31:24]. write lpc and dma. read only dma. 488h no specific usage 8-bit wo write lpc and dma. read only dma. 489h dma channel 6 high page 8-bit rec upper addr bits [31:24]. write lpc and dma. read only dma. 48ah dma channel 7 high page 48bh dma channel 5 high page 48ch-48eh no specific usage 8-bit wo write lpc and dma. read only dma. 48fh dma channel 4 high page 8-bit rec upper addr bits [31:24]. write lpc and dma. read only dma. 490h-4cfh no specific usage --- --- 4d0h pic level/edge 8-bit yes irq0-irq 7. 4d1h pic level/edge 8-bit yes irq8-irq15. 4d2h-4ffh no specific usage --- --- note 1. the diverse device snoops writes to this port and maintains the msb as nmi enable. when low, nmi is enabled. when high, nmi is disabled. this bit def aults high. reads of this port return bits [6:0] from the on-chip or off-chip target, while bit 7 is returned from the ?maintained? value. table 4-6. legacy i/o: 000h-4ffh (continued) i/o addr. function size r/w comment 74 amd geode? cs5535 companion device data book global concepts and features 31506b 4.8 standard geodelink? device msrs all geodelink devices have the following standard msrs and are always located at the addresses indicated below from the base address given in table 4-2 "msr addresses from amd geode? gx processor" on page 60: msr address 0: geodelink device capabilities (gld_msr_cap) msr address 1: geodelink device master configura- tion (and gla prefetch) (gld_msr_config) msr address 2: geodelink device system manage- ment interrupt control (gld_msr_smi) msr address 3: geodelink device error control (gld_msr_error) msr address 4: geodelink device power management (gld_msr_pm) msr address 5: geodelink device diagnostic msr (gld_msr_diag) (this register is reserved for internal use by amd and should not be written to.) 4.8.1 msr address 0: capabilities the capabilities msr (gld_msr_cap) is read only and provides identification informat ion as illustrated table 4-7. 4.8.2 msr address 1: master configuration the defined fields in the geodelink device master config- uration msr (gld_msr_conf) vary depending upon the device. refer to the appropriate geodelink device register chapter starting in section 6.0 "register descriptions" on page 199 for descriptions. 4.8.3 msr address 2: smi control each geodelink device within the geode cs5535 com- panion device incorporates system management inter- rupts (smis). these smis ar e controlled via the standard gld_msr_smi located at msr address 2 within each geodelink device (see table 4-8). the lower 32 bits of this register contain enable (en) bits, while the upper 32 bits contain flag (flag) bits. the en and flag bits are organized in pairs of (n, n+32). for example: (0,32); (1,33); (2,34); etc. the gld_msr_smi is used to control and report events . an event is any action or occurrence within the geodelink device requiring processor attention. the flag bits are status bits that record events. the en bits enable events to be recorded. an en bit must be 1 for an event to be recorded (with the exception of the glui and the glcp - the en bit must be 0 for an event to be recorded). when an event is recorded, the associated flag bit is set to a 1. smi events are of two types: asynchronous smi (asmi) and synchronous smi (ssmi). table 4-7. gld_msr_cap bit descriptions bit name description 63:24 rsvd reserved. reads as 0. 23:8 dev_id device id. identifies the module. 7:0 rev_id revision id. identifies the module revision. table 4-8. standard gld_msr_smi format 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag smi_flag 313029282726252423222120191817161514131211109876543210 smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en smi_en amd geode? cs5535 companion device data book 75 global concepts and features 31506b 4.8.3.1 asmi asmis fall into two classes: direct and in-direct . a behavioral model for a direct class asmi is illustrated in figure 4-7. in the model, an event is represented as a short duration (much less than 1 s) pos itive pulse that is associ- ated with a given enable/event pair n . the enable/event pair is represented by a pair of simple ?d? flip/flops that can be set (write 1 to q) or cleared (write 0 to q) by software. the en bit can be written high or low, but the flag bit can only be cleared. by geodelink architecture convention, writing a 1 to a flag bit clears it; writing a 0 has no effect. if the en bit is 1, then t he 0-to-1 transition of the event pulse clocks a 1 into the smi flag flip/flop. all of the asmi bits are ored together to form the geodelink device asmi . the geodelink device asmi is routed through the gliu where it is ored with all other device asmis to form the geode cs5535 companion device asmi. figure 4-7. direct asmi behavioral model a behavioral model for an in-direct class asmi is illustrated in figure 4-8 on page 76. an event is represented as before, but it is first applied to some type of native event register. generally, this is an irq status register of some kind that records multiple irq sources. alternatively, there might be multiple independent native event registers that are at some point ored together to form a single native event summary signal (ness). in general, a ness can also be an irq signal routed to the pic subsystem. hence, depending on operational needs, a ness can be an irq or asmi. the important point is that the ness 0-to-1 transition clocks a 1 into the smi flag flip/flop. the event only in- directly causes the smi flag bit to be set. further note that the event[x] and asmi[ n+1] are independently clear- able. asmi[n+1] can be cleared, while leaving ness at a 1 state. after such cleari ng action with ness high, asmi[n+1] will not set again. al ternatively, event[x] could be cleared without effectin g the state of asmi[n+1]. lastly, it is possible to clear and set asmi[n+1] while ness remains at a constant high st ate. consider the following sequence: 1) assume en[n] is high. 2) event[x] occurs and ness makes a 0-to-1 transition that sets asmi[n+1]. 3) software clears asmi[n+1] by writing a 1 to it. 4) ness remains high because event[x] has not been cleared. 5) en[n] is cleared to 0. 6) en[n] is set to a 1 and causes asmi[n+1] to be set again. note: step 5 could also be performed between steps 2 and 3 instead, yielding the same result. the sequence of setting en[n] to 0 followed by setting en[n] to 1 is called an enable toggle . the previous sequence is used when multiple events x, y, z, etc. all or to form a single ness. the events are shar- ing a single ness. under this arrangement, the following virtual system architecture? (vsa) software sequence would be typical: 1) assume en[n] is high. 2) event[x] fires and causes a geode cs5535 compan- ion device asmi. 3) vsa searches the geode gx processor/geode cs5535 companion device system looking for the asmi source and finds asmi[n+1]. 4) vsa clears en[n] to 0 and begins to perform the actions associated with event[x]. 5) while the ?actions? are being taken, event[y] fires. 6) vsa ?actions? include clearing event[x] and asmi[n+1]. smi msr dq ci + flag bit[n+1] asmi [n+1] geodelink? clear_by_software dq ci set_by_software clear_by_software event [x] en bit[n] other asmi flag bits device asmi 76 amd geode? cs5535 companion device data book global concepts and features 31506b 7) ness remains high because event[y] has fired. 8) vsa sets en[n] high. this action sets asmi[n+1] high again and causes another geode cs5535 companion device asmi. 9) vsa begins to return to t he process interrupted by the original asmi, but notes smi into the processor is still asserted and returns to step 3. 10) if there was no event[y] at any point above, return to the interrupted process. note: step 5 above could occur at any time between step 2 and step 9, or the event[y] could come after step 10. regardless, the same vsa approach is used in order not to miss any events. 4.8.3.2 apparent ssmi an ssmi event is associated with an i/o space access to a specific address or range of addresses. if ssmis are enabled for the given address, then the hardware traps or blocks access to the target register. the actual register write and/or read operation is not performed. generally, only write operations are trapped, but there are cases of trapping writes and reads. the geode cs5535 companion device does not support ssmis, however, the geode cs5535 companion device supports a mechanism called ?apparent ssmi? using asmis. (hereafter ?apparent ssmi? is referred to as ?ssmi?.) the geode cs5535 companion device insures that the asmi is taken on the i/o instruction boundary. the asmi reaches the cpu before a target ready is signaled on the pci bus. this action creates an ssmi because the i/o instruction will not complete before asmi reaches the cpu. vsa software then examines the glpci_sb gld_smi_msr to determine if an ssmi has occurred from an i/o trap. figure 4-8. in-direct asmi behavioral model native event dq ci + flag bit[x] clear_by_software dq ci set_by_software clear_by_software event [x] en bit[m] other flag bits smi msr dq ci + flag bit[n+1] asmi [n+1] geodelink? clear_by_software dq ci set_by_software clear_by_software en bit[n] other asmi flag bits native event summary signal (ness) event [x] register or all or all device asmi amd geode? cs5535 companion device data book 77 global concepts and features 31506b ssmis are primarily used for hardware emulation and extension. from the perspective of the code on which the trap occurred, everything is normal and done in hardware. however, vsa code generally performs a number of oper- ations to achieve the desired result. this can include returning an appropriate read value to the trapped soft- ware. the gliu is often used to implement ssmi traps. any i/o descriptor can be used for this purpose by setting the destination id to 0. on a descriptor hit, the gliu traps the access and sets the ssmi bit in the response packet. 4.8.3.3 asmi/ssmi summary table 4-9 provides a register summary for the standard gld_smi_msrs. table 4-9. gld_msr_smis summary port #, device flag bit en bit smi type description port 0, gliu ( note 1 ) 35 3 asmi statistics counter 2 event 34 2 asmi statistics counter 1 event 33 1 asmi statistics counter 0 event 32 0 ssmi descriptor trap and illegal accesses port 1, glpci_sb 22 6 asmi target abort signaled 21 5 asmi parity error 20 4 asmi system error 19 3 asmi execp received 18 2 asmi ssmi received 17 1 asmi target abort received 16 0 asmi master abort received port 2, usbc2 33 1 asmi int by the usb (see pic for actual source) 32 0 asmi asmi for the usb (see usb for actual source) port 3, atac 33 1 asmi irq for ide (see pic for actual source) 1 0 ssmi ide pio port 4, dd (divil) 47 15 ssmi pmc pm1_cnt 46 14 ssmi pmc pm2_cnt 45 13 asmi kel a20 keyboard 44 12 ssmi 8237 dma controller access during legacy dma 43 11 ssmi lpc access during legacy dma 41 9 ssmi uart 2 access during legacy dma 40 8 ssmi uart 1 access during legacy dma 39 7 asmi kel init port a 38 6 asmi kel a20 port a 37 5 asmi kel init keyboard 36 4 asmi pmc event (see pmc for actual source) 35 3 asmi extended pic mapper (see pic for actual source) 34 2 asmi kel emulation event 33 1 asmi shutdown special cycle 32 0 asmi halt special cycle port 5, acc 32 0 ssmi irq from acc port 6, usbc1 33 1 asmi int by the usb (see pic for actual source) 32 0 asmi asmi for the usb (see usb for actual source) port 7, glcp (note 1) 17 1 asmi debug event 16 0 asmi convert geode cs5535 companion global gliu_error to asmi note 1. for this device, the listed events are enabled when the en bit is low. for all other devices, events are enabled when th e associ- ated en bit is high. 78 amd geode? cs5535 companion device data book global concepts and features 31506b 4.8.4 msr address 3: error control each geodelink device within the geode cs5535 com- panion device can generate errors. furthermore, these errors are controlled via the standard geodelink device error msr (gld_msr_error) located at msr address 3 within each geodelink device. the register is organized just like gld_msr_smi, that is, the lower 32 bits contain enable (en) bits, while the upper 32 bits contain flag (flag) bits (see table 4-8 on page 74). the en and flag bits are organized in pairs of (n, n+32). for example: (0,32); (1,33); (2,34); etc. the error msr is used to control and report errors. the smi concepts of direct asynchronous and synchro- nous carry over into similar e rror concepts. however, there is no concept of an in-direct error. at each geodelink device, all of the error flag bits are ored together to form the error signal. the error is routed through the gliu where it is ored with all other device errors to form the geode cs5535 companion device error signal. this signal is routed to the glcp for debug purposes. only the gliu is capable of generating synchronous errors that utilize the exception (excep) bit of the associated response packet. all other geode cs5535 companion device geodelink devices only generate asynchronous errors. 4.8.5 msr address 4: power management all the power management msrs (gld_msr_pm) con- form to the model illustrated in table 4-10. the power and i/o mode functions are completely independent other than sharing the same msr. the gld_msr_pm fields have the following definitions: power mode for clock domains: ? 00: disable clock gating. clocks are always on. ? 01: enable active hardware clock gating. clock goes off whenever this module?s circuits are not busy. ?10: reserved. ?11: reserved. i/o mode (applies only to glpci_sb and atac modules, see table 4-11 and table 4-12 for a list of controlled signals): ? 00: no gating of i/o cells during a sleep sequence (default). ? 01: during a power management sleep sequence, force inputs to their non-asserted state when pm_in_slpctl is enabled. ? 10: during a power management sleep sequence, force inputs to their non-asserted state when pm_in_slpctl is enabled, and park (force) outputs low when pm_out_slpctl is enabled. ? 11: immediately and unconditionally, force inputs to their not asserted state, and park (force) outputs low. the pmc controls when the pci/ide inputs and outputs (listed in table 4-11 and table 4-12) are asserted and de- asserted. the pm_out_slpct l (pms i/o offset 0ch) and pm_in_slpctl (pms i/o offset 20h) registers pro- vide the global control of the pci/ide i/os. the io_mode bits individually control pci (glpci_sb gld_msr_pm (msr 51000004h[49:48]) and ide (atac gld_msr_pm (msr 51300004h[49:48]) i/os. table 4-10. msr power management model 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 io mode h io mode g io mode f io mode e io mode d io mode c io mode b io mode a rsvd 313029282726252423222120191817161514131211109876543210 pmode15 pmode14 pmode13 pmode12 pmode11 pmode10 pmode9 pmode8 pmode7 pmode6 pmode5 pmode4 pmode3 pmode2 pmode1 pmode0 amd geode? cs5535 companion device data book 79 global concepts and features 31506b 4.9 power management typically the three greatest power consumers in a comput- ing device are the display, the hard drive (if it has one) and the system electronics. the cpu usually consumes the most power of all the system electronic components. man- aging power for the first two is relatively straightforward in the sense that they are simply turned on or off. managing cpu power is more difficult since effective use clock con- trol technology requires effective detection of inactivity, both at a system level and at a code processing level. power consumption in a geode gx processor or other geode processor based system is managed with the use of both hardware and software. the complete hardware solution is provided for only when the geode gx processor is combined with the geode cs5535 companion device. the processor power consumption is managed primarily through a sophisticated clock stop management technol- ogy. the processor also pr ovides the hardware enablers from which the complete power management solution depends on. basically two methods are supported to manage power during periods of inactivity. the first method, called activity based power management allows the hardware in the geode cs5535 companion device to monitor activity to certain devices in the system an d if a period of inactivity occurs take some form of power conservation action. this method does not require os support because this support is handled by smm software. simple monitoring of external activity is imperfect as we ll as inefficient. the second method, called passive power management, requires the os to take an active role in managing power. amd sup- ports two application programming interfaces (apis) to enable power management by the os: advanced power management (apm) and advanced configuration and power interface (acpi). these two methods can be used independent of one another or they can be used together. the extent to which thes e resources are employed depends on the application and the discretion of the sys- tem designer. the geode gx processor and geode cs5535 companion device contain advanced powe r management features for reducing the power consumption of the processor, com- panion device and other devices in the system. table 4-11. sleep driven pci signals signal ball no. direction c/be[3:0]# r6, t9, u11, u14 pad driven to 0. internal logic sees logic 1. devsel# r11 pad driven to 0. internal logic sees logic 1. frame# u9 pad driven to 0. internal logic sees logic 1. trdy# t10 pad driven to 0. internal logic sees logic 1. irdy# r10 pad driven to 0. internal logic sees logic 1. stop# t11 pad driven to 0. internal logic sees logic 1. par u10 pad driven to 0. internal logic sees logic 1. req# t1 pad driven to 0. gnt# r1 pad tri-state. internal logic sees logic 0. ad[31:0] u1, t3, u3, r4, t4, r5, t5, u5, t6, u6, r7, t7, u7, r8, t8, u8, r12, t12, u12, r13, t13, u13, r14, t14, p15, r15, t15, p16, t16, r16, t17, r17 pad driven to 0. table 4-12. sleep driven ide signals signal ball no. direction ide_cs[1:0]# c10, b10 pad driven to 0. ide_ior0# b13 pad driven to 0. ide_iow0# c13 pad driven to 0. ide_ad[2:0] b11, a12, a11 pad driven to 0. ide_reset# f15 pad driven to 0. ide_rdy0 a13 pad tri-state. internal logic sees logic 0. ide_dreq0 a14 pad tri-state. internal logic sees logic 0. ide_dack0# c12 pad driven to 0. ide_data[15:0] c14, b15, b16, a17, c17, d16, d17, e17, e16, e15, d15, b17, c16, c15, a15, b14 pad driven to 0. 80 amd geode? cs5535 companion device data book global concepts and features 31506b 4.9.1 power domains in order to support power management in periods of inac- tivity as well as ?off? conditions, the geode cs5535 com- panion device is divided into three power domains: working domain - consists of v core and v io standby domain - consists of v core_vsb and v io_vsb rtc domain - consists of v bat when the system is in an operational mode , all three of the domains are on. in general the power management tech- niques used while operating produce power savings with- out user awareness. the perfo rmance and usability of the system is unaffected. when the system is ?off? only the standby domain is pow- ered. if desired, the operational design can allow returning the system to the operational point when the system was last ?on?. this ?instant on? feature is a requirement for many battery powered systems. if the system has been removed from all power sources the real time clock (rtc) can be kept operating with a small button battery. all sections of the geode cs5535 companion device use the working domain except: standby domain gpio[31:24] and associated registers. gpio input conditioning functions 6 and 7. gpio power management events (pmes) 6 and 7. mfgpt[7:6]. power management controller (pmc) standby controller and associated i/o consisting of: working, work_aux, and reset_out. pmc standby registers starting at pms i/o offset 30h. see table 6-68 "pm support registers summary" on page 495. rtc domain real time clock 4.9.2 acpi power management acpi power management is a standardized method to manage power. an overview of the standard is presented here. see section 5.17 "power management control" on page 172 for a more complete discussion of acpi support in the geode cs5535 companion device see acpi specifi- cation v2.0 for complete details on acpi. a geode gx pro- cessor/cs5535 companion devi ce system solution can fully support all the requirements in the acpi specification. acpi defines power states from a system perspective down to a device perspective. there are four global system states: g0 through g3. as a subset of the global system states g0-g2 there are six sleep states: s0 through s5. within the sleep states s0-s1 there are five cpu states: c0-c3 and ct, and three device states: d0-d2. in a geode gx processor/cs5535 companion device system design, the optional sleep stat e s2, and the cpu states c3 and ct (cpu throttling) are not supported. see table 5- 34 "supported acpi power management states" on page 172?. table 5-34 shows how the acpi power states relate to each other. the table also shows the condition of the power domains and the logic within those domains with respect to the acpi power states. 4.9.3 apm power management some systems rely solely on an apm (advanced power management) driver for enabling the operating system to power-manage the cpu. apm provides several services which enhance the system power management. it is a rea- sonable approach to power management but apm has some limitations: apm is an os-specific driver, and may not be available for some operating systems. application support is inconsistent. some applications in foreground may prevent idle calls. apm does not help with suspend determination or peripheral power management. 4.10 component revision id the revision id number of the geode cs5535 companion device may be read in any of the following places. all return the same value: 1) glcp_chip_rev_id register: msr 51700017h[7:0]. 2) pci configuration space device revision id: pci index 08h[15:0]. 3) tap controller revision register: instruction 8ffffah[7:0]. the revision is an 8-bit value. bits [7:4] indicate major revi- sions while bits [3:0] indicate minor revisions. for example: 0x11 a1 value assigned to first manufactured silicon of any new product. 0x12 a2 minor update to first silicon. 0x21 b1 major change to first silicon. for listing of updates, refer to the amd geode? cs5535 companion device specification update document. amd geode? cs5535 companion device data book 81 5 module functional descriptions 31506b 5.0 module functional descriptions the modules that make up the amd geode? cs5535 companion device (shown in gray in figure 5-1) are: geodelink? interface unit geodelink pci south bridge geodelink control processor ata-5 controller (ide controller multiplexed with flash interface) universal serial bus 1 controller with ports 1-1 and 1-2 universal serial bus 2 controller with ports 2-1 and 2-2 audio codec 97 (ac97) controller diverse device the low voltage detect (lvd) circuit is not a geodelink device, but is connected to the power management con- troller (pmc) for voltage monitoring support. this section provides a functional description of each mod- ule. figure 5-1. module block diagram geodelink? pci south bridge amd geode? gx processor interface pci test/reset interface ac97 controller external audio ata-5 controller usb controller #1 usb controller #2 33 or 66 mhz flash interface 82xx pc legacy mfgp timers rtc & cmos ram uart (2) & ir (1) smb controller lpc port power mgmnt external i/o external usb ports 1-1 & 1-2 external usb ports 2-1 & 2-2 geodelink? interface unit external ide/flash gpio diverse integration logic (divil) diverse device (dd) low voltage detect (lvd) system power voltages power good for power on reset (por) (glpci_sb) (gliu) (usbc1) (usbc2) (acc) (atac) geodelink? control processor (glcp) 82 amd geode? cs5535 companion device data book geodelink? interface unit 31506b 5.1 geodelink? interface unit many traditional architectures use buses to connect mod- ules together, usually requiring unique addressing for each register in every module. this requires that some kind of house-keeping be done as new modules are designed and new devices are created from the module set. module select signals can be used to create the unique addresses, but that can get cumbersome and it requires that the mod- ule selects be sourced from some centralized location. to alleviate this issue, amd developed an internal bus architecture called geodelink. the geodelink architecture connects the internal modules of a device using the data channels provided by geodelink interface units (glius). using glius, all internal module port addresses are derived from the distinct port t hat the module is connected to. in this way, a module?s model specific registers (msrs) do not have unique addresses until a device is defined. also, as defined by the geodelink architecture, a module?s port address depends on the location of the mod- ule sourcing the cycle, or source module. the geode cs5535 companion device incorporates one gliu into its device architecture. except for the configura- tion registers that are required for x86 compatibility, all internal registers are accessed through a model specific register (msr) set. msrs have a 32-bit address space and a 64-bit data space. the full 64-bit data space is always read or written when accessed. 5.1.1 gliu port connections table 5-1 shows the geodelink devices connected to each of the seven gliu ports on the geode cs5535 com- panion device. table 5-1. gliu port connections port # geodelink? device 1 geodelink pci south bridge (glpci_sb) 2 usb controller #2 (usbc2) 3 ata-5 controller (atac) 4 diverse device (dd) 5 ac97 audio controller (acc) 6 usb controller #1 (usbc1) 7 geodelink control processor (glcp) amd geode? cs5535 companion device data book 83 geodelink? interface unit 31506b 5.1.2 descriptor summary table 5-2 shows the descriptors reserved for each geodelink device. table 5-2. gliu descriptors reserved for geodelink? devices geodelink? device descriptor type # of descriptors usage usbc1 p2d_bmk 1 do not hit on keyboard emulation registers. usbc2 p2d_bmk 1 do not hit on keyboard emulation registers. atac iod_bm 1 for ide master registers. iod_bm 1 defaults to 1fxh. iod_sc 1 defaults to 3f6h. dd iod_bm 3 com ports legacy power management. iod_bm 1 for secondary ide trapping to 17xh. iod_sc 1 for secondary ide trapping to 376h. iod_sc 1 keyboard legacy power management. iod_sc 3 lpc ports legacy power management. iod_sc 1 floppy legacy power management. acc p2d_bm 1 for memory space registers. iod_bm 1 for i/o space registers. glpci_sb p2d_bm 1 for master requests to geode gx processor?s glpci. spares iod_bm 2 provides the possibility to virtualize nand flash accesses when the ide/flash shared pins are in the ?ide position?. for the ?flash posi- tion?, already dedicated ide descriptors can be used to virtualize. iod_bm 1 iod_sc 1 p2d_bm 1 84 amd geode? cs5535 companion device data book geodelink? pci south bridge 31506b 5.2 geodelink? pci south bridge the geodelink? pci bus south bridge (glpci_sb) pro- vides a pci interface for geodelink device based designs. its three major functions are: 1) acting as a pci slave and transforming pci transac- tions to gliu transactions as a gliu master. 2) acting as a gliu slave and transforming gliu trans- actions to pci bus transactions as a pci master. 3) providing a cpu serial interface that conveys system information such as interrupts, ssmi, asmi, etc. features include: pci v2.2 compliance. optional signals perr#, serr#, lock#, and clkrun are not implemented. 32-bit, 66 mhz pci bus operation and 64-bit, 66 mhz geodelink device operation. target support for fast back-to-back transactions. zero wait state operation within a pci burst. msr access mailbox in pci configuration space. capable of handling in-bound transactions after reset_out# + 2 clock cycles. dynamic clock stop/start support for geodelink and pci clock domains via power management features. programmable idsel selection. support active decoding for legacy i/o space 000h to 3ffh and dma high page 480h to 48fh. support subtractive decode for memory and i/o space. special performance enhancements for fast ide pio data transfers. the glpci_sb module is composed of the following major blocks: geodelink interface fifo/synchronization transaction forwarding pci bus interface cpu interface serial (cis) the gliu and pci bus interfaces provide adaptation to the respective buses. the transaction forwarding block pro- vides bridging logic. the cis block provides serial output to the cpu for any change in ssmi and the selected side- band signals. little endian byte ordering is used on all sig- nal buses. figure 5-2 is a block diagram of the glpci_sb module. figure 5-2. glpci_sb block diagram geodelink? interface pci bus interface pci bus request request data req# / gnt# msr transaction forwarding fifos/synchronization cis side-band signals amd geode? gx processor cis amd geode? cs5535 companion device data book 85 geodelink? pci south bridge 31506b 5.2.1 geodelink? interface the geodelink interface block provides a thin protocol conversion layer between the transaction forwarding mod- ule and the gliu. it is responsible for multiplexing in-bound write request data with out- bound read response data on the single gliu data out bus. 5.2.2 fifos/synchronization the fifo block consists of a collection of in-bound and out-bound fifos. each fifo provides simple, synchro- nous interfaces to the reader and to the writer. the fifo block also includes synchronization logic for a few non-fifo related signals and clock gating logic. 5.2.3 transaction forwarding the transaction forwarding block receives, processes, and forwards transaction requests and responses between the geodelink interface and pci bus interface blocks. it implements the transaction ordering rules. it performs write/read prefetching as needed . it also performs the nec- essary translation between gliu and pci commands. the transaction forwarding block also handles the conversion between 64-bit gliu data paths and 32-bit pci data paths. out-bound transactions are handled in a strongly ordered fashion. all out-bound memory writes are posted. the send_response flag is never expected to be set in a memory write and is ignored. any queued out-bound requests are flushed prior to handling an in-bound read request. all in-bound memory writes are posted. south bridge mas- ter out-bound read request data can pass in-bound writes. thus, a pending out-bound read request need not be deferred while posted in-bound write data is waiting to be flushed or is in the process of being flushed. the out-bound read request may be performed on the pci bus at the same time that the in-bound write data is flowing through the gliu. when handling an in-bound read request, the intended size of the transfer is unknown. in-bound read requests for non- prefetchable addresses will on ly fetch the data explicitly indicated in the pci transaction. thus, all in-bound read requests made to non-prefetchable addresses will return at most a single 32-bit word. in-bound read requests made to prefetchable memory may cause more than a 32-bit word to be prefetched. the amount of data prefetched is configurable via the read threshold fields of the global control (glpci_ctrl), msr 51000010h. multiple read requests may be generated to satisfy the read threshold value. in-bound read requests may pass posted in-bound write data when there is no address collision between the read request and the address range of the posted write data (dif- ferent cache lines) and the read address is marked as being prefetchable. support ide data port read prefetch when msr control register (msr 51000010h[19:18]) is set to ide prefetch for performance enhancement. i/o reads to address 1f0h can follow a prefetching behavior. when enabled, the glpci_sb issues gliu read request packets for this specific address before receiving a request on the pci bus for it. all pci accesses to 1f0h must be dwords; that is, 4 bytes. 5.2.4 pci bus interface the pci bus interface block provides a protocol conver- sion layer between the transaction forwarding module and the pci bus. the master and target portions of this module operate independently. thus, ou t-bound write requests and in-bound read responses are effectively multiplexed onto the pci bus. it includes address decoding logic to recog- nize distinct address regions for slave operation. each address region is defined by a starting address, an address mask, and some attached attributes (i.e., memory and/or i/o space indicator, prefetchable, retry/hold, postable memory write, region enable). the pcif is responsible for retrying out-bound requests when a slave termination without data is seen on the pci bus. it also must restart transactions on the pci that are prematurely ended with a slave termination. this module also always slave terminates in-bound read transactions issued to non-prefetchable regions after a single word has been transferred. 5.2.5 cpu interface serial the cpu interface serial block provides a serial interface to the cpu for side-band signals. from reset, the glpci_sb connects only the susp# signal to the serial output. all other signals must be added by programming the cis mode (msr 51000010h[4:3]). any change of the signals selected from the 16 side-band signals will start shifting to the cpu all 20 bits of the cis register including two start bits (00) and two padding stop bits (11). three different modes contro l the selection of the side- band signals to the cis shift register. 5.2.6 programmable id selection an id select register, idsel[31:0], is used for programma- ble id selection. only one bit in idsel[31:12] is set and used as a chip select (i.e., compared with ad[31:12]) dur- ing a pci configuration write/read. the reset value of the idsel register is 02000000h. af ter reset, the first 32-bit i/o write pci command (i.e., be# = 0h) with address 00000000h and one bit set in ad[31:0] is assumed to ini- tialize the idsel register. only data with one bit set in ad[31:0] is considered valid. all other values are ignored and will not change the contents of idsel. 86 amd geode? cs5535 companion device data book geodelink? pci south bridge 31506b 5.2.7 ssmi and excep support in gliu read/write response packets if the hcd (hold for cis transfer disable) bit in glpci_msr_ctrl (msr 51000010h[9]) is set, any in- bound memory, i/o, or external msr read/write response packet will be checked for ssmi and excep bits. if the response packet has the excep bit and/or ssmi bit set, then the glpci_sb will not complete the transaction (it will either issue a retry or hold pci bus) until the cis transfer completes. during an out-bound transaction, when the glpci_sb issues a master abort, the excep bit in the gliu response packet is set. 5.2.8 subtractive decoding if the sdoff (subtractive decode off) bit in the glpci_msr_ctrl (msr 51000010h[10]) is cleared (reset value), any pci transaction, other than configuration read/write, interrupt acknowledge, and special cycle transactions, not claimed by any device (i.e., not asserting devsel#) within the default active decode cycles (three cycles immediately after frame# being asserted) will be accepted by glpci_sb at the fourth clock edge. the retry condition will be issued for memory read, memory read line, memory read multiple (after initial latency timeout), and i/o read/write (immediately) and all the required infor- mation (command, address and byte enable bits) is stored for the following delayed transactions. during delayed transactions, the active decode scheme is used. any address accessed through a subtractive decoding is assumed to be non-prefetchable. 5.2.9 byte enable checking in i/o address decoding in any in-bound i/o transaction , the byte enables be[3:0]# are checked against address bits pci_ad[1:0] for valid combinations. if an illegal byte enable pattern is asserted, the glpci_sb will issue a target abort. the only excep- tion is when subtractive decode is used. during a subtrac- tive decode, pci_ad[1:0] a nd be# are passed to the gliu as is. the ioed (i/o addre ssing error checking disable) bit in glpci_msr_ctrl (msr 51000010h[8]) can be set to disable the i/o addressing error checking, where ad[1:0] is ignored and the byte enables are passed to the gliu. 5.2.10 ide data port read prefetch this algorithm issues multiple four byte reads to the ide data register (1f0h) at the ?beginning? of an ide ?read operation?. the hardware contin ues to read ahead of soft- ware read requests until a sector boundary is about to be crossed. the hardware does not read ahead over a sector boundary. once a software read crosses a sector bound- ary, the hardware proceeds to read ahead again. further- more, the algorithm does not prefetch the last read of a sector because there is the potential that th e last sector read will be the last read of the overall ?read operation?. on the last read, the status will change to indicate the opera- tion is complete. by not prefetching the last sector read, the data and status never get out of sync with each other. in pide prefetch mode, hardware always makes four byte reads to the ide data register (1f0h) and supplies the four bytes of read data to ide read operations ignoring byte enables of the ide read operation. 5.2.11 ide data port write posting the ppide (post primary ide) in glpci_msr_ctrl (msr 51000010h[17]) controls po st/write on confirmation for i/o writes of address 1f0h (part of primary ide address). if bit 17 is set, a write is completed immediately on the pci bus as soon as it is accepted by the glpci_sb. if bit 17 is cleared, an i/o write is completed only after com- pleting the write in the primary ide space. default behavior is write on confirmation. 5.2.12 other typical slave write posting for each glpci_sb region configuration register (0 through 15), if the space bit (bit 32) is programmed for i/o and bit 3 (pf, prefetchable) is high, post all i/o writes to this region. (see section 6.2. 2.2 "region 0-15 configura- tion msrs (glpci_r[x])" on page 238 for further details.) use of this feature is most appropriate for gpio ?bit bang- ing? in the diverse device module. posting writes on the north bridge side will not increase performance. 5.2.13 memory writes with send response normally memory writes are posted independent of region and independent of decode and legacy/non-legacy address. the usb registers are in memory space and can not be moved to i/o space due to driver compatibility issues. in a geode gx processor/companion device sys- tem, a memory write is posted and a possibility exists that a subsequent i/o write will complete before the posted memory write completes. in order to prevent out of order execution, when a memory write is issued to the gliu in the geode cs5535 companion device, the request packet is issued with the send response bit set to serialize the request. i/o writes are not an issue, since the requests packet always has the send response bit set. amd geode? cs5535 companion device data book 87 geodelink? pci south bridge 31506b 5.2.14 cpu interface serial (cis) the cis provides t he system interface between t he geode cs5535 companion device and geode gx processor. the interface supports several modes to send different combi- nations of 16-bit side-band signals through the cis signal (ball p3). the sideband signals are synchronized to the pci clock through 2-stage latching. whenever at least one of 16 signals is changed, the serial transfer (using the pci clock) immediately starts to send the information from the south bridge to the north bridge. but, if any bit changes within 20 clocks of any previous change, the later change will not be transmitted during the transfer. another transfer will start immediately after the conclusion of the transfer due to the subsequent change. there are three modes of operation for the cis signal (ball p3). note that the transmitted polarity may be different than the ?generally defined? polarity state: mode a - non-serialized mode with cis equivalent to susp# (reset mode). not used in normal operation. mode b - serialized mode with signals susp#, nmi#, sleep#, and delayed sleep#. not used in normal opera- tion. mode c - serialized mode with mode b signals plus smi#, and intr#. used in normal operation. if the glpci_msr_ctrl bit hcd (msr 51000010h[9]) is set, any in-bound transaction, except in-bound memory writes, will be held for any cis transfer to complete before claiming completion. mode selection is programmed in the glpci_msr_ctrl, bits [4:3] (msr 51000010h). table 5-3 lists the serial data with corresponding side-band signals. the serial shift register takes the selected side- band signals as inputs. the signal smi is the ored result of the ssmi_asmi_flag (ssmi received event) bit in glpci_sb gld_msr_smi (msr 51000002h[18]) and the side-band signal asmi. it also serves as a direct output to the processor. table 5-3. cis serial bits assignment and descriptions bit position mode b mode c comment 0 (start) 0 0 start bit 0 1 (start) 0 0 start bit 1 211reserved 311reserved 4 susp# susp# sleep request 5 nmi# nmi# non-maskable interrupt 6 sleep# sleep# power management input disable 7 delayed sleep# delayed sleep# power management output disable 8 1 smi# asynchronous smi or synchronous smi 9 1 intr# maskable interrupt out 10 1 1 reserved 11 1 1 reserved 12 1 1 reserved 13 1 1 reserved 14 1 1 reserved 15 1 1 reserved 16 1 1 reserved 17 1 1 reserved 18 (end) 1 1 stop bit 0 19 (end) 1 1 stop bit 1 note: mode a is not listed since it is a non-serialized mode with cis equivalent to susp# (reset mode). 88 amd geode? cs5535 companion device data book geodelink? pci south bridge 31506b 5.2.15 exception handling this section describes how various errors are handled by the pci bus interface block. since perr# is not implemented on the geode cs5535 companion device or the geode gx processor, error reporting via this signal is not supported. in a geode gx processor/cs5535 companion device system, other pci devices that do have the perr# pin must have a pull-up. 5.2.16 out-bound write exceptions when performing an out-bound write on pci, three errors may occur: master abort, target abort, and parity error. when a master or target abort occurs, the pci bus inter- face block will flush any stored write data. if enabled, an asmi is generated. asmi generation is enabled and reported in glpci_sb gld_msr_smi (msr 51000002h). parity errors are detected and handled by the processor. the failed transaction will not be retried. 5.2.17 out-bound read exceptions when performing an out-bound read on pci, three errors may occur: master abort, target abort, and detected parity error. when a master or target abort occurs, the pci bus interface block will return the expected amount of data. if enabled, an asmi is generated. asmi generation is enabled and reported in glpci_sb gld_msr_smi (msr 51000002h). parity errors are detected and handled by the processor. the failed transaction will not be retried. 5.2.18 in-bound write exceptions when performing an in-bound write from pci, two errors may occur: a detected parity error and a gliu exception. a gliu exception cannot be relayed back to the originating pci bus master, because in-bound pci writes are always posted. when a parity error is detected, an asmi is gener- ated if it is enabled. asmi generation is enabled and reported in glpci_sb gld_msr_smi (msr 51000002h). however, the corrupted write data will be passed along to the gliu. 5.2.19 in-bound read exceptions when performing an in-bound read from the gliu, the excep flag may be set on any received bus-word of data. this may be due to an address configuration error caused by software or by an error reported by the source of data. the asynchronous err and/or smi bit will be set by the pci bus interface block and the read data, valid or not, will be passed to the pci bus interface block along with the associated exceptions. the pc i bus interface block should simply pass the read response data along to the pci bus. amd geode? cs5535 companion device data book 89 ac97 audio codec controller 31506b 5.3 ac97 audio c odec controller the primary purpose of the ac97 audio codec controller (acc) is to stream data be tween system memory and an ac97 codec (or codecs) us ing direct memory access (dma). the ac97 codec supports several channels of digi- tal audio input and output. hence, the acc contains sev- eral bus mastering dma engines to support these channels. this method off-loads the cpu, improving sys- tem performance. the acc is connected to the system through the gliu and all accesses to and from system memory go through the gliu. the ac97 codec is con- nected with a serial interface, and all communication with the codec occurs via that interface (see figure 5-3). features include: ac97 version 2.1 compliant interface to codecs: serial in (x2), serial out, sync out, and bit clock in. eight-channel buffered gliu mastering interface. support for industry standard 16-bit pulse code modu- lated (pcm) audio format. support for any ac97 codec with sample rate conver- sion (src). transport for audio data to and from the system memory and ac97 codec. capable of outputting multi-channel 5.1 surround sound (left, center, right, left rear, right rear, and low frequency effects). hardware includes: geodelink? adapter. three 32-bit stereo-buffered bus masters (two for output, one for input). five 16-bit mono-buffered bus masters (three for output, two for input). ac link control block for interfacing with external ac97 codec(s). the acc logic controls the traffic to and from the ac97 codec. for input channels, serial data from the codec is buffered and written to system memory using dma. for output channels, software-processed data is read from system memory and streamed out serially to the codec. figure 5-3. acc block diagram gliu data in gliu data out geodelink? adaptor (gla) output data mux registers / control to/from codec control signals to bus masters glcp i/f bus master 0 bus master 1 bus master 2 bus master 3 bus master 4 bus master 5 bus master 6 bus master 7 ccu gl clock ccu lbus clock ccu ac link bit clock ac link 90 amd geode? cs5535 companion device data book ac97 audio codec controller 31506b 5.3.1 audio bus masters the acc includes eight bus mastering units (three for input, five for output). each bus master corresponds to one or two slots in the ac link transfer protocol (see section 5.3.4.1 "ac link serial interface protocol" on page 91). table 5-4 lists the details for each bus master. 5.3.2 bus master audio configuration registers the bus masters must be programmed by software to con- figure how they transfer data. this is done using their con- figuration registers. these r egisters determine whether the bus master is active and what parts of memory they have been assigned to transfer. status registers allow software to read back information on the state of the bus masters. (see section 6.3.2 "acc native registers" on page 252 for further details on the bus master audio configuration reg- isters.) 5.3.3 ac link overview the ac link is the interface between the ac97 codec and the acc. the interface is ac97 v2.1 compliant. any ac97 codec that supports sample rate conversion (src) can be used with the acc. see intel corporation?s ?audio codec 97? revision 2.1 component specification for more details. the ac link protocol defines an input and output frame consisting of 12 ?slots? of data. each slot contains 20 bits, except slot 0, it contains 16 bits. the sync signal is gener- ated by the acc and defines the beginning of an input and an output frame. the serial clock is generated by the ac97 codec. the ac link is covered in depth in section 5.3.4.1 "ac link serial interface protocol" on page 91. it is impor- tant to note that the ac97 code c has its own set of configu- ration registers that are separate from the acc. these registers are accessible over the serial link. there are reg- isters in the acc that provide software with an interface to the ac97 codec registers. (see section 6.3.2 "acc native registers" on page 252 for register descriptions.) table 5-4. audio bus master descriptions bus master size direction ac link slot(s) channel description bm0 32-bit (16 bits/channel) output to codec 3 (left) and 4 (right) left and right stereo main playback bm1 32-bit (16 bits/channel) input from codec 3 (left) and 4 (r ight) left and right stereo recording bm2 16-bit output to codec 5 modem line 1 dac output bm3 16-bit input from codec 5 modem line 1 adc input bm4 16-bit output to codec 6 or 11 (configurable) center channel playback (slot 6) or headset playback (slot 11) bm5 16-bit input from codec 6 or 11 (config urable) microphone record (slot 6) or headset record (slot 11) bm6 32-bit (16 bits/channel) output to codec 7 (left) and 8 (right) left and right surround playback bm7 16-bit output to codec 9 low frequency effects playback (lfe) amd geode? cs5535 companion device data book 91 ac97 audio codec controller 31506b 5.3.4 codec interface 5.3.4.1 ac link serial interface protocol the following figures outline the slot definitions and timing scheme of the ac link serial protocol. figure 5-4. ac link slot scheme figure 5-5. ac link output frame figure 5-6. ac link input frame tag cmd pcm pcm line1 pcm pcm pcm pcm rsvd hset gpio ac_s_sync ac_s_out (outgoing stream) ac_s_in data phase tag addr cmd data left right dac cen l sur r sur lfe dac cntl tag status pcm pcm line1 mic rsvd hset gpio addr status data left right adc adc acd status or ac_s_in2 (incoming stream) rsvd rsvd rsvd 0123456789101112 slot # phase valid frame slot 1 slot 2 slot 12 end of ac_clk ac_s_sync time slot ?valid? bits (?1? = time slot contains valid pcm data) slot 1 slot 2 slot 3 slot 12 tag phase data phase 48 khz (20.8 s) 12.288 mhz (81.4 ns) ac_s_out ?0? ?0? ?0? 19 0 19 19 019 00 slot 3 previous frame codec ready slot 1 slot 2 slot 12 end of time slot ?valid? bits (?1? = time slot contains valid pcm data) slot 1 slot 2 slot 3 slot 12 ac_s_in or ac_s_in2 ?0? ?0? ?0? ?19? 0 19 0 19 0 19 0 ac_clk ac_s_sync tag phase data phase 48 khz (20.8 s) 12.288 mhz (81.4 ns) previous frame 92 amd geode? cs5535 companion device data book ac97 audio codec controller 31506b 5.3.4.2 ac link output frame (ac_s_out) the audio output frame data stream corresponds to the time division multiplexed bundles of all digital output data targeting the ac97 codec?s dac inputs and control regis- ters. each audio output frame contains 13, 20-bit outgoing data slots, except for slot 0, it has 16 bits. slot 0 is a dedi- cated slot used for the ac link protocol. an audio output frame begins with a low-to-high transition of the ac_s_sync signal. ac_s_sync is synchronous to the rising edge of ac_clk. the ac97 codec samples the ac_s_sync on the immediately following falling edge of ac_clk. ac_s_sync is held high for 16 bit clocks. the acc transmits data on each rising edge of the bit clock, whereas the ac97 codec samples the data on the falling edge of ac_clk. the serial output stream is msb justified (msb first) within each slot, and all non-valid bit positions are stuffed with 0s by the ac link interface module. slot 0: tag this slot is used for ac link protocol information. the first bit (bit 15) flags the validity of the entire audio frame as a whole. if this bit is 0, all of the remaining bits in the frame should be 0. the next 12 bits indicate the validity of the 12 following slots. the last two bits contain the codec id for accessing registers of several codecs. when the codec id is 01, 10, or 11, bits 13 and 14 must always be 0, even if slots 1 and 2 are valid. slots that are marked invalid by slot 0 should be padded with all 0s (except for slots 1 and 2 while accessing registers of a secondary codec). bit 15 frame valid bit 14 slot 1 valid (primary codec only) bit 13 slot 2 valid (primary codec only) bits [12:3] slot 3-12 valid bits (bit[12] -> slot 3, bit[11] -> slot 4, bit[10] -> slot 5, ... , bit[3] -> slot 12) bit 2 reserved bits [1:0] codec id field slot 1: command address the command address is used to access registers within the ac97 codec. the ac97 regi sters control features and monitor status for ac97 codec functions, including mixer settings and power management as indicated in the ac97 codec specifications. the control interface architecture supports up to 64 16-bit read/write registers, addressable on even byte boundaries, and reserves support for 64 odd addresses. audio output frame slot 1 communicates c ontrol register address, and write/read command information to the ac97 codec. bit 19 read/write command (1 = read, 0 = write) bits [18:12] control register index (64 16-bit locations, addressed on even byte boundaries) bits [11:0] reserved (stuffed with 0s) the first bit (msb) indicates whether the current control transaction is a read or write operation. the following 7 bit positions communicate the targeted control register address. slot 2: command data the command data slot carries 16-bit control register write data if the current command port operation is a write cycle as indicated by slot 1, bit 19. bits [19:4] control register write data (stuffed with 0s if current operation is a read) bits [3:0] reserved (stuffed with 0s) if the current command port operation is a read, then the entire slot is stuffed with 0s. slot 3: pcm playback left channel outputs the front left audio dac data (main output) (16-bit resolution, msb first, unused lsbs = 0). slot 4: pcm playback right channel outputs the front right audio dac data (main output) (16- bit resolution, msb first, unused lsbs = 0). slot 5: modem line 1 dac outputs the modem line 1 dac data (16-bit resolution, msb first, unused lsbs = 0). slot 6: pcm playback center channel outputs the center channel dac data (16-bit resolution, msb first, unused lsbs = 0). slot 7: pcm playback left surround channel outputs the left surround channel dac data (16-bit resolu- tion, msb first, unused lsbs = 0). slot 8: pcm playback right surround channel outputs the right surround channel dac data (16-bit reso- lution, msb first, unused lsbs = 0). slot 9: pcm playback lfe channel outputs the low frequency effects channel dac data (16- bit resolution, msb first, unused lsbs = 0). slot 10: not used slots 10 is not used by the acc. amd geode? cs5535 companion device data book 93 ac97 audio codec controller 31506b slot 11: modem headset dac outputs the headset dac data (16-bit resolution, msb first, unused lsbs = 0). slot 12: gpio control this slot allows the acc to set the value of the ac97 codec?s gpio output pins. bits [19:4] value of the gpio pins (up to 16 can be implemented) bits [3:0] reserved 5.3.4.3 ac link input fr ame (ac_s_in, ac_s_in2) the audio input frame data streams correspond to the time division multiplexed bundles of all digital input data coming from the ac97 codec. each input frame contains 13, 20-bit incoming data slots, except for slot 0; it is 16 bits. slot 0 is a dedicated slot used for t he ac link protocol. an audio input frame begins with a low-to-high transition of the ac_s_sync signal. ac_s_sync is synchronous to the rising edge of ac_clk. the ac97 codec samples the ac_s_sync signal on the immediately following falling edge of the bit clock. the ac97 codec transmits data on each following rising edge of ac_clk. the acc samples the data on the falling edges of ac_clk. the serial input stream is msb justified (msb first) within each slot, and all non-valid bit positions stuffed with zeroes by the ac97 codec. slot 0: tag the first bit of the tag slot (bit 15) is the codec_ready bit. the next 12 bits indicate the validity of the next 12 data slots. slot 1: status address / slotreq bits the status address is the ec ho of the register address (index) that was sent to the codec on output slot 1 of the previous output frame. it indicates the address (index) of the register whose data is being returned in slot 2 of the input frame. bit 19 reserved (stuffed with 0s) bits [18:12] control register index (echo of register index for which data is being returned) bits [11:2] slotreq bits (for variable sampling rate) bits [1:0] reserved (stuffed with 0s) the slotreq bits support the variable sample rate sig- naling protocol. with normal 48 khz operation, these bits are always zero. when the ac97 codec is configured for a lower sample rate, some output frames will not contain samples because the ac link always outputs frames at 48 khz. the slotreq bits serve as the codec?s instrument to tell the acc whether it needs a sample for a given slot on the next output frame. fo r each bit: 0 = send data; 1 = do not send data. if the codec does not request data for a given slot, the acc should tag that slot invalid and not send pcm data. the mapping between slotreq bits and output slots is given in table 5-5. the slotreq bits are independent of the validity of slot 1, and slot 1 will only be tagged valid by the codec if it contains a register index. slot 2: status data the status data slot delivers 16-bit control register read data. bits [19:4] control register read data (stuffed with 0s if slot 2 is tagged ?invalid? by slot 0) bits [3:0] reserved (stuffed with 0s) slot 3: pcm record left channel contains the left channel adc input data (16-bit resolution, msb first, unused lsbs = 0). slot 4: pcm record right channel contains the right channel adc input data (16-bit resolu- tion, msb first, unused lsbs = 0). slot 5: modem line 1 adc contains the modem line 1 adc input data (16-bit resolu- tion, msb first, unused lsbs = 0). slot 6: optional microphone record data contains the microphone adc input data (16-bit resolution, msb first, unused lsbs = 0). slots 7-10: not used slots 7-10 are reserved. table 5-5. slotreq to output slot mapping bit slot request notes 11 slot 3 left channel out (bm0) 10 slot 4 right channel out (bm0) 9 slot 5 modem line 1 out (bm2) 8 slot 6 center out (bm4 if selected) 7 slot 7 left surround out (bm6) 6 slot 8 right surround out (bm6) 5 slot 9 lfe out (bm7) 4 slot 10 not supported 3 slot 11 handset out (bm4 if selected) 2 slot 12 not supported 94 amd geode? cs5535 companion device data book ac97 audio codec controller 31506b slot 11: modem headset adc contains the modem headset a dc input data (16-bit reso- lution, msb first, unused lsbs = 0). slot 12: gpio status this slot returns the pin status of the ac97 codec?s gpio pins (if implemented). bits [19:4] value of the gpio pins (up to 16 can be implemented) bits [3:1] reserved bit 0 gpio_int input pin event interrupt (1 = event; 0 = no event) bit[0] indicates that there was a transition on one of the unmasked codec gpio pins (see ac97 codec specifica- tion v2.1 for details). if the codec gpio interrupt enable bit is set, then slot 12, bit[0] = 1 will trigger an irq and set the codec gpio interrupt flag bit. 5.3.5 ac link power management 5.3.5.1 ac link power-down the ac link interface signals can be placed in a low power mode by programming the ac97 codec?s power-down control/status register. when this is performed, both the ac_clk and ac_s_in are brought to a low voltage level by the ac97 codec. this happens immediately following the write to the ac97 codec?s power-down control/status register, so no data can be transmitted in slots 3-12 for the frame signaling power-down. after powering down the ac link, the acc must keep ac_s_sync and ac_s_out low; hence, all the ac link signals (input and output) are driven low. ac_clk is de-asserted at the same time that bit[4] of slot 2 is being transmitted on the ac link. this is necessary because the precise time when the codec stops ac_clk is not known. 5.3.5.2 ac link wakeup (warm reset) a warm reset re-activates the ac link without altering the registers in the ac97 code c. the acc signals the warm reset by driving ac_s_sync high for a minimum of 1 s in the absence of the ac_clk. this must not occur for a min- imum of four audio frame periods following power-down (note that no bit clock is available during this time). ac_s_sync is normally a synchronous signal to ac_clk, but when the ac97 codec is powered down, it is treated as an asynchronous wakeup signal. during wakeup, the ac97 codec does not re-activate the bit clock until ac_s_sync is driven high (for 1 s minimum) and then low again by the acc. once ac_s_sync is driven low, ac_clk is re-asserted. see "audio driver power-up/down programming model" on page 98 for additional power management information and programming details. 5.3.6 bus mastering buffer scheme because the bus masters must feed data to the codec with- out interruption, they require a certain amount of data buff- ering. the 32-bit bus masters (stereo) use 24 bytes of buffer space, and the 16-bit bus masters (mono) use 20 bytes of buffer space. a bus master will always do buffer fill/empty requests whenever it can transfer 16 bytes of data. it will attempt to do transfers of 16 bytes on a 16-byte boundary, whenever possible. a bus master may do a transfer of more (if it is just starting, and sufficient buffer space is available) or less than 16 bytes (to bring itself onto a 16- byte boundary). it may also do a transfer of less than 16 bytes if the size of the physica l memory region causes it to end on a non-16 byte boundary. some important details on how a bus master behaves: when an outgoing bus master is enabled, it begins sending data over the ac link as soon as data is avail- able in its buffer. the slot valid tag for its slot will be asserted beginning with the first audio sample. when a bus master is disabled while operating, any data in its buffer is lost. re-e nabling the bus master begins by fetching a prd. if the bus master is paused during recording or play- back, the data in its buffer remains there in a frozen state. once resumed, it c ontinues as if nothing has occurred. if the bus master is playing back data, the output slots corresponding to the bus master are tagged invalid while it is in the paused state. if a buffer underrun occurs on an outgoing bus master, the output slots corresponding to the bus master are tagged invalid until data becomes available. if a buffer overrun occurs on an incoming bus master, samples coming in on the serial link are tossed away until space becomes available in the bus master?s buffer. amd geode? cs5535 companion device data book 95 ac97 audio codec controller 31506b 5.3.7 acc software programming 5.3.7.1 physical region descriptor (prd) table address register before a bus master starts a transfer it must be pro- grammed with a pointer to a physical region descriptor (prd) table. this is done by writing to the bus master?s prd table address register. this pointer sets the starting memory location of the prd table. the prds in the prd table describe the areas of memory that are used in the data transfer. the table must be aligned on a 4-byte boundary (dword aligned). 5.3.7.2 physical region descriptor format each physical memory region to be transferred is described by a prd as illustrated in table 5-6. the prd table must be created in memory by software before the bus master can be activated. when the bus master is enabled by setting its bus master enable bit, data transfer begins, with the prd table serving as the bus master?s ?guide? for what to do. the bus master does not cache prds. a prd entry in the prd table consists of two dwords. the first dword contains a 32-bit pointer to a buffer to be transferred (memory region base address). the second dword contains control flags and a 16-bit buffer size value. the maximum amount of audio data that can be transferred for a given prd is 65534 bytes for mono streams and 65532 bytes for stereo streams. for stereo streams (bus masters 0, 1, and 6): memory region base address and size should be a multiple of four (dword aligned). this ensures an equal number of left and right samples. for mono streams (bus masters 2, 3, 4, 5, and 7): memory region base address and size should be a multiple of two (word aligned). descriptions of the control flags are: end of transfer (eot) - if set in a prd, this bit indi- cates the last entry in the pr d table. the last entry in a prd table must have either the eot bit or the jmp bit set. a prd can not have both the jmp and eot bits set. when the bus master reaches an eot, it stops and clears its bus master enable bit. if software desires an irq to be generated with the eot, it must set the eop bit and the eot bit on the last prd entry. end of page (eop) - if set in a prd and the bus master has completed the prd?s transfer, the end of page bit is set (in the irq status register) and an irq is generated. if a second eop is reached due to the completion of another prd before the end of page bit is cleared, the bus master error bit is set (in the irq status register) and the bus master pauses. in this paused condition, reading the irq status re gister clears both the bus master error and the end of page bits, and the bus master continues. jump (jmp) - this prd is special. if set, the memory region base address is now the target address of the jmp. the target address of the jmp must point to another prd. there is no audio data transfer with this prd. this prd allows the creation of a looping mecha- nism. if a prd table is created with the jmp bit set in the last prd, the prd table does not need a prd with the eot bit set. a prd can not have both the jmp and eot bits set. table 5-6. physical region descriptor (prd) format dword byte 3 byte 2 byte 1 byte 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 memory region base address [31:0] (address of audio data buffer) 1e o t e o p j m p reserved size [15:0] 96 amd geode? cs5535 companion device data book ac97 audio codec controller 31506b 5.3.7.3 pcm data format and byte order table 5-7 shows an example of the how pcm audio data is stored in memory (byte order and channel order). each row represents a byte in memory, with increasing addresses as you go down. the byte order can be configured via the bus master command register for intel (little endian) or motor- ola (big endian) byte ordering. changing the byte order only affects how pcm data is interpreted. prd entries and register contents are always little endian. the two channel format applies to the 32-bit bus masters handling left and right input and output. the single channel format applies to the 16-bit bus mast ers. the 32-bit bus masters always operate on stereo data, and the 16-bit bus masters always operate on mono data. since there is no special mode for playing monaural sound through the main chan- nels (left and right), it is the responsibility of the software to create stereo pcm data with identical samples for the left and right channels to effectively output monaural sound. 5.3.7.4 progra mming model audio playback/record the following discussion explains, in steps, how to initiate and maintain a bus master transfer between memory and an audio slave device. in the steps, the reference to exam- ple refers to figure 5-7: 1) software creates a prd ta ble in system memory. the last prd entry in a prd table must have the eot or jmp bit set. example - assume the data is outbound. there are three prds in the example prd table. the first two prds (prd_1, prd_2) have only the eop bit set. the last prd (prd_3) has only the jmp bit set. this example creates a prd loop. figure 5-7. acc prd table example table 5-7. pcm data format (byte and channel ordering) 2 channel, little endian 1 channel, little endian 2 channel, big endian 1 channel, big endian sample channel byte sample byte sample channel byte sample byte 0 left low 0 low 0 left high 0 high 0 left high 0 high 0 left low 0 low 0 right low 1 low 0 right high 1 high 0 right high 1 high 0 right low 1 low 1 left low 2 low 1 left high 2 high 1 left high 2 high 1 left low 2 low 1 right low 3 low 1 right high 3 high 1 right high 3 high 1 right low 3 low address_1 size_1 eot = 0 audio buffer_1 audio buffer_2 size_1 size_2 address_1 eop = 1 jmp = 0 address_2 size_2 eot = 0 eop = 1 jmp = 0 address_3 don?t care eot = 0 eop = 0 jmp = 1 prd_1 prd_2 prd_3 address_2 address_3 amd geode? cs5535 companion device data book 97 ac97 audio codec controller 31506b 2) software loads the starting address of the prd table by programming the prd table address register. example - program the prd table address register with address_3. 3) software must fill the buffers pointed to by the prds with audio data. it is not absolutely necessary to fill the buffers; however, the buffer filling process must stay ahead of the buffer emptying. the simplest way to do this is by using the eop flags to generate an interrupt when an audio buffer is empty. example - fill audio buffer_1 and audio buffer_2. ensure than an interrupt service routine is assigned to the audio interrupt. 4) read the irq status register to clear the bus master error and end of page flags (if set). program the ac97 codec properly to receive audio data (mixer settings, etc.). engage the bus master by setting the bus master enable bit. the bus master reads the prd entry pointed to by the prd table address register. using the address from the prd, it begins the audio transfer. the prd table address register is incremented by eight. example - the bus master is now properly pro- grammed to transfer audio buffer_1 to a specific slot(s) in the ac97 interface. 5) the bus master transfers data from memory and sends it to the ac97 codec. at the completion of each prd, the bus master?s next response depends on the settings of the flags in the prd. example - after transferring the data described by prd_1, an interrupt is generated because the eop bit is set, and the bus master continues on to prd_2. the interrupt service routine reads the second level audio irq status register to det ermine which bus master to service. it refills audio buffer_1 and then reads the bus master?s irq status register to clear the end of page flag and the interrupt. after transferring the data described by prd_2, another interrupt is generated because the eop bit is set, and the bus master co ntinues on to prd_3. the interrupt service routine reads the second level audio irq status register to det ermine which bus master to service. it refills audio buffer_2 and then reads the bus master?s irq status register to clear the end of page flag and the interrupt. prd_3 has the jmp bit set. this means the bus mas- ter uses the address stored in prd_3 (address_3) to locate the next prd. it does not use the address in the prd table address register to get the next prd. since address_3 is the location of prd_1, the bus master has looped the prd table. no interrupt is gen- erated for prd_3. pausing the bus master can be accomplished by set- ting the bus master pause bi t in its control register. the bus master stops immedi ately on the current sam- ple being processed. upon resuming, the bus master (clearing the bus master pause bit), resumes on the exact sample where it left off. the bus master can be stopped in the middle of a transfer by clearing the bus master enable bit in its control register. in this case, the bus master will not remember what sample it left off on. if it is re-enabled, it will begin by reading the prd entry pointed to by its prd table address register. if software does not re- initialize this pointer, it will be pointing to the prd entry immediately following the prd entry that was being processed. this may be an invalid condition if the bus master was disabled while processing the last prd in a prd table (prd table address register pointing to memory beyond the table). note that if the bus master error bit is set, the interrupt service routine should refill two buffers instead of one, because a previous interrupt was missed (unless it was intentionally missed). for this to work correctly, the service routine should read the second level audio irq status register, fill the buffer of the bus master needing service, read the bus master?s irq status register, and then fill the next buffer if the bus master error bit was set. failing to fill the first buffer before reading the irq status register would possibly resume the bus master too early and result in sound being played twice or data being overwritten (if record- ing). codec register access the acc provides a set of registers that serve as an inter- face to the ac97 codec?s re gisters. the codec command register allows software to initiate a read or a write of a codec register. the codec status register allows software to read back the data from the codec after a read operation has completed. since the ac link runs very slow relative to core cpu speed (and therefore software speed), it is nec- essary for software to wait between issuing commands to the codec. for register reads, software specifies a command address and sets both the read/write flag and the codec command new flag in the codec control register. software must then wait for the codec status new bit to be set before using the returned status data in the codec status register. before issuing another read command, software must wait for the codec command new flag to be cleared by hardware. (note: codec command new will clear before codec sta- tus new is set; therefore, a second read can be issued before the result of the current read is returned). for register writes, software specifies a command address and command data using the codec control register. at the same time it must set the codec command new flag. before issuing another read or write, software must wait for the codec command new flag to clear. see section 6.3 "ac97 audio codec controller register descriptions" for details on the codec register interface. 98 amd geode? cs5535 companion device data book ac97 audio codec controller 31506b audio driver power-up/down programming model the acc contains machine specific registers (msrs) that relate to a very low level power management scheme, but are discrete from the power management features of the codec and the device driver programming model. this sec- tion covers the power management features for the device driver. see section 5.3.5 "ac link power management" on page 94 for power management hardware details. the following sections outline how the device driver should perform power management. power-down procedure 1) disable or pause all bus masters using their bus mas- ter command register. 2) it may be necessary to determine if a second codec is being used, and if so, verify that the power-down semaphore for secondary codec bit is set before pro- ceeding (to insure that the modem driver has prepared the second codec for po wer-down, if necessary). 3) using the codec control register, access the primary codec?s registers and program the codec to power- down. also, simultaneously write to the ac link shut- down bit in the codec control register (acc i/o offset 0ch[18]). 4) the acc and codec will power-down once the com- mand is received by the codec. all of the contents of the acc and codec registers are preserved during the power-down state. 5) if you wish to enable the gpio wakeup interrupt, wait for an additional two audio frame periods (42 s) before setting the gpio wakeup interrupt enable bit (acc i/o offset 00h[29]). failure to wait will cause false interrupt events to occur. power-up procedure 1) if gpio wakeup interrupt enable (acc i/o offset 00h[29]) was set in the power-down procedure, it will automatically be disabled upon power-up. 2) set the ac link warm reset bit in the codec control register (acc i/o offset 0ch[17]). this will initiate the warm reset sequence. 3) wait for the codec ready bit(s) in the codec status register (acc i/o offset 08h[23:22]) to be asserted before accessing any codec features or enabling any bus masters. notes: 1) if the gpio wakeup interrupt enable (acc i/o offset 00h[29]) is set, and an interrupt occurs, it is detected and fired, but the interrupt does not wakeup the codec and acc. the hardware will only wakeup if the soft- ware responds to the interrupt and performs the power-up procedure. 2) once software has issued a power-down, it must not perform the power-up procedure for at least six audio frame periods (about 0.125 ms or 125 s). doing so could lock up the codec or acc. 3) if the system has cut off power to the codec and restarted it, it is not necessary to initiate a warm reset. the ac link shutdown should be cleared manually to restart the operation of the ac link. amd geode? cs5535 companion device data book 99 ata-5 controller 31506b 5.4 ata-5 controller the hard disk controller is an ata-5 compatible ide con- troller (atac). this controller supports udma/66, mdma, and pio modes. the controller can support one channel (two devices). the ide interface provides a va riety of features to optimize system performance, including 32-bit disk access, post write buffers, bus master, mdma, look-ahead read buffer, and prefetch mechanism. the ide interface timing is completely programmable. tim- ing control covers the command active and recover pulse widths, and command block register accesses. the ide data-transfer speed for each device on each channel can be independently programmed allowing high-speed ide peripherals to coexist on the same channel as older, com- patible devices. faster devices must be ata-5 compatible. the atac also provides a software-accessible buffered reset signal to the ide drive. the ide_rst# signal is driven low during system reset and can be driven low or high as needed for device power-off conditions. features include: ata5-compliant ide controller supports pio (mode 0 to 4), mdma (mode 0 to 2), and udma (mode 0 to 4) supports one channel, two devices allows independent timing programming for each device 5.4.1 pio modes the ide data port transaction latency consists of address latency, asserted latency, and recovery latency. address latency occurs when a pci master cycle targeting the ide data port is decoded, and the ide_addr[2:0] and ide_cs# lines are not set up. address latency provides the setup time for the ide_addr[2:0] and ide_cs# lines prior to ide_ior# and ide_iow#. asserted latency consists of the i/o command strobe assertion length and recovery time. recovery time is pro- vided so that transactions may occur back-to-back on the ide interface without violating minimum cycle periods for the ide interface. if ide_iordy is asserted when the initial sample point is reached, no wait states ar e added to the command strobe assertion length. if ide_iordy is negated when the initial sample point is reached, additi onal wait states are added. recovery latency occurs after the ide data port transac- tions have completed. it provides hold time on the ide_addr[2:0] and ide_cs# lines with respect to the read and write strobes (ide_ior# and ide_iow#). the pio portion of the ide registers is enabled through: channel 0 drive 0 pio (atac_ch0d0_pio) (msr 51300020h) channel 0 drive 1 pio (atac_ch0d1_pio) (msr 51300022h) the ide channel and devices can be individually pro- grammed to select the proper address setup time, asserted time, and recovery time. the bit formats for these registers are shown in section 6.4.3 "atac native registers" on page 274. note that there are different bit formats for each of the pio program- ming registers depending on the operating format selected: format 0 or format 1. channel 0 drive 0/1 - the dma register (msr 51300021h/ 51300023h) sets the format of the pio register. if bit 31 = 0, format 0 is used and it selects the slowest pio mode (bits [19:16]) for commands. if bit 31 = 1, format 1 is used and it allows independent control of command and data. also listed in the bit formats are recommended values for the different pio modes. note that these values are only recommended settings and are not 100% tested. maximum pio data throughput is achieved when the pio data port is read/written using 32-bit accesses. 5.4.2 bus master mode an ide bus master is provided to perform the data trans- fers for the ide channel. the atac off-loads the cpu and improves system performance. the bus master mode programming interface is an exten- sion of the standard ide programming model. this means that devices can always be dealt with using the standard ide programming model, with the master mode functional- ity used when the appropriate driver and devices are present. master operation is designed to work with any ide device that supports dma transfers on the ide bus. devices that work in pio mode can only use the standard ide programming model. the ide bus master uses a simple scatter/gather mecha- nism, allowing large transfer blocks to be scattered to or gathered from memory. this cuts down on the number of interrupts to and interactions with the cpu. 5.4.2.1 physical region de scriptor table address before the controller starts a ma ster transfer it is given a pointer to a physical region descriptor table. this pointer sets the starting memory location of the physical region descriptors (prds). the prds describe the areas of mem- ory that are used in the data transfer. the prds must be aligned on a 4-byte boundary and the table cannot cross a 64 kb boundary in memory. 5.4.2.2 ide bus m aster registers the ide bus master registers have an ide bus master command register and bus mast er status register. these registers can be accessed by byte, word, or dword. 100 amd geode? cs5535 companion device data book ata-5 controller 31506b 5.4.2.3 physical region descriptor format each physical memory region to be transferred is described by a physical region descriptor (prd) as illus- trated in table 5-8. when the bus master is enabled (com- mand register bit 0 = 1), data transfer proceeds until each prd in the prd table has been transferred. the bus mas- ter does not cache prds. the prd table consists of two dwords. the first dword contains a 32-bit pointer to a buffer to be trans- ferred. this pointer must be word aligned. the second dword contains the size (16 bits) of the buffer and the eot (end of table) flag. the size must be in multiples of one word (2 bytes) or zero (meaning a 64 kb transfer). the eot bit (bit 31) must be set to indicate the last prd in the prd table. 5.4.2.4 programming model the following steps explain how to initiate and maintain a bus master transfer between memory and an ide device: 1) software creates a prd table in system memory. each prd entry is 8 bytes long, consisting of a base address pointer and buffer size. the maximum data that can be transferred from a prd entry is 64 kb. a prd table must be aligned on a 4-byte boundary. the last prd in a prd table must have the eot bit set. 2) software loads the starting address of the prd table by programming the prd table address register. 3) software must fill the buffers pointed to by the prds with ide data. 4) write 1 to the bus master interrupt bit and bus master error (status register bits 2 and 1) to clear the bits. 5) set the correct direction to the read or write control bit (command register bit 3). engage the bus master by writing a 1 to the bus mas- ter control bit (command register bit 0). the bus master reads the prd entry pointed to by the prd table address register and increments the address by 08h to point to the next prd. the transfer begins. 6) the bus master transfers data to/from memory responding to bus master requests from the ide device until all prd entries are serviced. 7) the ide device signals an interrupt once its pro- grammed data count has been transferred. 8) in response to the interrupt, software resets the bus master control bit in the command register. it then reads the status of the c ontroller and ide device to determine if the transfer is successful. table 5-8. physical region descriptor format dword byte 3 byte 2 byte 1 byte 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 memory region physical base address [31:1] (ide data buffer) 0 1 eot reserved size [15:1] 0 amd geode? cs5535 companion device data book 101 ata-5 controller 31506b 5.4.2.5 udma/66 mode the atac supports udma/66. it utilizes the standard ide bus master functionality to interface, initiate, and control the transfer. the udma/66 definition also incorporates a cyclic redundancy checking (crc) error checking proto- col to detect errors. the udma/66 protocol requires no extra signal pins on the ide connector. the atac redefines three standard ide control signals when in udma/66 mode. these definitions are shown in table 5-9. all other signals on the ide connector retain their func- tional definitions during the udma/66 operation. ide_iow# is defined as stop for both read and write transfers to request to stop a transaction. ide_ior# is redefined as dmardy# for transferring data from the ide device to the atac. it is used by the atac to signal when it is ready to transfer data and to add wait states to the current transaction. the ide_ior# signal is defined as strobe for transferring data from the atac to the ide device. it is the data strobe signal driven by the atac on which data is transferred during each rising and falling edge transition. ide_iordy is redefined as strobe for transferring data from the ide device to the at ac during a read cycle. it is the data strobe signal driven by the ide device on which data is transferred during each rising and falling edge tran- sition. ide_iordy is defined as dmardy# during a write cycle for transferring data from the atac to the ide device. it is used by the ide device to signal when it is ready to transfer data and to add wait states to the current transaction. udma/66 data transfer consists of three phases: a startup phase, a data transfer phase, and a burst termination phase. the ide device begins the startup phase by asserting ide_dreq. when ready to begin the transfer, the atac asserts ide_dack#. when ide_dack# is asserted, the atac drives ide_cs0# and ide_cs1# asserted, and ide_addr[2:0] low. for write cycles, the atac negates stop, waits for the ide device to assert dmardy#, and then drives the first data word and strobe signal. for read cycles, the atac negates stop and asserts dmardy#. the ide device then sends the first data word and asserts strobe. the data transfer phase continues the burst transfers with the atac and the ide via providing data, toggling strobe and dmardy#. ide_data[15:0] is latched by the receiver on each rising and falling edge of strobe. the transmitter can pause the burst cycle by holding strobe high or low, and resume the burst cycle by again toggling strobe. the receiver can pause the burst cycle by negating dmardy# and resumes the burst cycle by asserting dmardy#. the current burst cycle can be terminated by either the transmitter or receiver. a burst cycle must first be paused, as described above, before it can be terminated. the atac can then stop the burst cycle by asserting stop, with the ide device acknowledging by negating ide_dreq. the transmitter then drives the strobe sig- nal to a high level. the atac then puts the result of the crc calculation onto ide_data[15:0] while de-asserting ide_dack#. the ide device latches the crc value on the rising edge of ide_dack#. the crc value is used for error checking on udma/66 transfers. the crc value is calculated for all data by both the atac and the ide device during the udma/66 burst transfer cycles. this result of the crc calculation is defined as all data transferred with a valid strobe edge while ide_dack# is asserted. at the end of the burst transfer, the atac drives the result of the crc calculation onto ide_data[15:0], which is then strobed by the de- assertion of ide_dack#. the ide device compares the crc result of the atac to its own and reports an error if there is a mismatch. the timings for udma/66 are programmed into the dma control registers: channel 0 drive 0 dma (atac_ch0d0_dma) (msr 51300021h) channel 0 drive 1 dma (atac_ch0d1_dma) (msr 51300023h) the bit formats for these registers are given in section 6.4.3 "atac native registers" on page 274. note that msr 51300021h[20] is used to select either mdma or udma mode. bit 20 = 0 selects mdma mode. if bit 20 = 1, then udma/66 mode is selected. once mode selection is made using this bit, the remaining dma registers also operate in the selected mode. also listed in the bit formats are recommended values for both mdma modes 0-2 and udma/66 modes 0-4. note that these values are only recommended settings and are not 100% tested. table 5-9. udma/66 signal definitions ide channel signal udma/66 read cycle udma/66 write cycle ide_iow# stop stop ide_ior# dmardy# strobe ide_iordy strobe dmardy# 102 amd geode? cs5535 companion device data book universal serial bus controller 31506b 5.5 universal serial bus controller the two universal serial bus controllers (usbc) each contain a geodelink? adapter, pci adapter, and usb core blocks. the functional descriptions of the blocks are described in the following subsections. 5.5.1 geodelink? adapter the geodelink adapter (gla) translates geodelink trans- actions to/from local bus transactions. the gla interfaces to a 64-bit gliu (geodelink interface unit) and a 32-bit local bus. the gla supports in-bound memory and i/o requests which are converted by the pci adapter (pa) into pci memory and i/o requests th at target the usbc. it also supports in-bound msr transactions to the msrs. these are located ?between? the gla and pa. lastly, there is a special msr used to pass pci configuration requests to the pa. the gla supports out-bound memory requests only. i/o and msr transactions from the usbc never occur. usbc pci master requests are converted by the pa into local bus master requests. these requests may con- sist of a simple 4-byte read or write. alternatively, a pci burst transaction of any length may be converted to an appropriate series of gliu transactions by the gla. lastly, the gla synchronizes gliu tran sactions at the gliu clock to the slower local bus transaction at local bus clock. 5.5.2 pci adapter the pci adapter translates pci signals to a specific local bus transaction that is attached to the gla, while the pci signals are connected directly to a compatible pci device. it also translates the local bus transactions to pci transac- tions. 5.5.3 usb core the usb core is a pci-based implementation of the uni- versal serial bus (usb) v1.1 specification utilizing the open host controller interface (ohci) standard developed by compaq, microsoft ? , and national semiconductor. the usb core consists of the three blocks: host controller, usb interface, and pci interface the usb core block diagram is shown in figure 5-8. figure 5-8. usb core block diagram usb port 1 port 1 port 2 root hub control sie usb port 2 data buffer clock generator bus master list processor interrupts frame mgmnt pci i/o pci slave pci config pci master usb core pci host controller usb interface interface embedded pci bus amd geode? cs5535 companion device data book 103 universal serial bus controller 31506b 5.5.4 host controller the usb host interacts with usb devices through the host controller. the host is responsible for: detecting the attachment and removal of usb devices. managing control flow between the host and usb devices. managing data flow between the host and usb devices. collecting status and activity statistics. providing power to attached usb devices. the usb system software on the host manages interac- tions between usb devices and host-based device soft- ware. there are five areas of interactions between the usb system software and device software: 1) device enumeration and configuration. 2) isochronous data transfers. 3) asynchronous data transfers. 4) power management. 5) device and bus management information. whenever possible, the usb system software uses exist- ing host system interfaces to manage the above interac- tions. the ohci specification for the universal serial bus is a register-level description of a host controller for the univer- sal serial bus, which in turn is described by the universal serial bus specification. ohci allows multiple host control- ler vendors to design and sell host controllers with a com- mon software interface, freeing them from the burden of writing and distributing software drivers. the design goal has been to balance the complexity of the hardware and software so that ohci is mo re than the simplest possible host controller for usb yet not the most complex possible. the host controller has four usb states visible to the host controller driver via the operational registers: u sb o pera - tional , u sb r eset , u sb s uspend , and u sb r esume . these states define the host controller responsibilities relating to usb signaling and bus states. the usb states are reflected in the hostcontroller functionalstate field of the hccontrol register. the host controller may only perform a single state transition. during a remote wakeup event, the host controller may transition from u sb s uspend to u sb r esume . the host controller interface registers are pci memory mapped i/o. the functional state machine (fsm) is shown in figure 5-9. 5.5.5 usb interface the usb interface includes the integrated root hub with two external ports, port 1 and port 2, as well as the serial interface engine (sie) and usb clock generator. the inter- face combines responsibility for executing bus transactions requested by the host controller as well as the hub and port management specified by usb. figure 5-9. usb host controller fsm u sb s uspend u sb r esume u sb o perational u sb r eset u sb r eset w rite u sb o perational w rite u sb r eset w rite u sb o perational w rite u sb s uspend w rite u sb r esume w rite or r emote w akeup u sb r eset w rite h ardware r eset s oftware r eset 104 amd geode? cs5535 companion device data book diverse integration logic 31506b 5.6 diverse integration logic the diverse integration logic (divil) connects a series of local bus devices to the geodelink? architecture. figure 5-10 illustrates how the divi l (within the dashed lines) interfaces with the other devices of the diverse device. the main blocks of the divil are: address decode, stan- dard msrs, local bars, and dataout mux (dom). figure 5-10. diverse logic block diagram gliu interface ri di do ro 8254 & port b (2) 8259a & kybd emu & system mgmt (2) uart & ir irq map port a bus control (2) 8237 & lpc bus rtc & cmos dma map control ram gpio & icf mfgp timers local bus interface pwr mgmnt nor & nand data out data in flash interfaces and control external i/o req/ack external i/o address external i/o external i/o external i/o slave addr & byte enables ro packet arguments from msr master addr & byte enables local bus handshake chip selects address decode and legacy decode msrs standard msrs local bars, compares, address hits * geodelink? adapter divil * data out mux not shown. and miscellaneous amd geode? cs5535 companion device data book 105 diverse integration logic 31506b address decode - decodes the upper local bus address bits to select a target slave. most of the legacy devices have fixed addresses or are selectable between a small number of selectable i/o addresses. however, many of the functions are relocatable via a local base address register (lbar); established via an msr. address decode also detects special gliu cycles, such as shutdown, and takes appropriate action. standard msrs - includes the standard geodelink device msrs found in all geodelink devices: capabili- ties, master configuration, smi control, error control, power management, and diagnostics. local bars - local base address registers (lbars) establish the location of non-legacy functions within the diverse device. the module also includes logic to compare the current bus cycle address to the lbar to detect a hit. for the i/o lbars, the i/o address space 000h-4ffh is off limits. no i/o lbar is allowed to point to this space. data out mux (dom) - this mux is not explicitly illus- trated. each function above produces a single output to the divil. the divil dom has a port for each of the functions and is responsible for selecting between them. 5.6.1 lbars and comparators the lbars are used to establish the address and hence, chip select location of all fu nctions that do not have fixed legacy addresses. this bloc k also has comparators to establish when a current bus cycle address hits an lbar. a hit is passed to the address decode block and results in a chip select to the target device if there are no conflicts. the mask and base address values are established via an msr. 5.6.1.1 fixed target size i/o lbars this discussion applies to the following lbars: msr 51400008h: irq mapper (msr_lbar_irq) msr 5140000bh: smb (msr_lbar_smb) msr 5140000ch: gpio and icfs (msr_lbar_gpio) msr 5140000dh: mfgpts (msr_lbar_mfgpt) msr 5140000eh: acpi (msr_lbar_acpi) msr 5140000fh: power management support (msr_lbar_pms) the io_mask only applies to the upper bits [15:12] (see figure 5-11). normally, one would set all the mask bits (i.e., no mask on upper bits). one should only mask or clear bits if address wrapping or aliasing is desired. rule. when a mask bit is cleared, the associated bit in the base address must also be cleared. otherwise, the compare will not be equal on these bits. this rule applies to both memory and i/o lbars. the base size is fixed based on the target. for example, the gpio takes 256 bytes of address space. therefore, the base only applies to bits [15:8]. base bits [7:0] are always cleared by the hardware. therefore, the base is always forced by hardware to be on a boundary the size of the tar- get. figure 5-11. i/o space lbar - fixed target size addr[15:12] i/o_mask compare base_addr hit [15:n] [15:12] notes: 1) the i/o mask is always 4 bits. 2) the i/o base address is variable ([15:n]). the value of ?n? depends on the i/o spac e requirements of the target. for exam ple, a device needing 4, 8, 16, 32, 64, 128, or 256 bytes of i/o space has ?n? = 2, 3, 4, 5, 6, 7, 8, respectively . the value ?n? for various functions is: msr_lbar_irq n = 5 msr_lbar_smb n = 3 msr_lbar_gpio n = 8 msr_lbar_mfgpt n = 6 msr_lbar_acpi n = 5 msr_lbar_pms n = 7 msr_lbar_flash_io n = 4 106 amd geode? cs5535 companion device data book diverse integration logic 31506b 5.6.1.2 variable target size i/o lbars this discussion applies to the following lbars: msr 51400010h: flash chip select 0 (msr_lbar_flsh0) with bit 34 = 0 (i/o mapped) msr 51400011h: flash chip select 1 (msr_lbar_flsh1) with bit 34 = 0 (i/o mapped) msr 51400012h: flash chip select 2 (msr_lbar_flsh2) with bit 34 = 0 (i/o mapped) msr 51400013h: flash chip select 3 (msr_lbar_flsh3) with bit 34 = 0 (i/o mapped) note: flash chip selects [3:0] can be programmed for i/o or a memory space. see section 5.6.1.3 "mem- ory lbars". the i/o lbar works just like the fixed style, except the size of the io_mask has been expanded to cover the entire address range (see figure 5-12). in the fixed style, the io_mask applies to bits [ 15:12] but for variable style, the io_mask applies to bits [15:4]. if all bits are set, then the target size is 16 bytes and base address bits [15:4] determine the base. base bits [3:0] are a ?don't care? and are effectively forced to zero by the hardware. thus, the smallest i/o target is 16 bytes. as the lsbs of io_mask are cleared, the ?target space? expands. for example, assume a 64-byte device is desired in i/o space. the io_mask = ffch, base addre ss bits [15:6] are pro- grammed to the desired base, and base address bits [5:4] are cleared (see rule on page 105). 5.6.1.3 memory lbars this discussion applies to the following lbars: msr 51400009h: kel from usb host controller 1 (msr_lbar_kel1) msr 51400010h: flash chip select 0 (msr_lbar_flsh0) with bit 34 = 1 (memory mapped) msr 51400011h: flash chip select 1 (msr_lbar_flsh1) with bit 34 = 1 (memory mapped) msr 51400012h: flash chip select 2 (msr_lbar_flsh2) with bit 34 = 1 (memory mapped) msr 51400013h: flash chip select 3 (msr_lbar_flsh3) with bit 34 = 1 (memory mapped) msr 5140000ah: kel from usb host controller 2 (msr_lbar_kel2) note: the flash chip selects [3:0] can be programmed for an i/o space or a memory space. for memory space, the lbar works exactly like the vari- able style (see figure 5-13), except that clearing the lsbs of the mem_mask begins to make sense. for example, assume there is a 64 kb external rom that is going to be connected to flash chip select 0. such a device needs address bits [15:0]. the mem_mask would normally be programmed to ffff0h and base address bits [31:16] would be programmed to the desired base. the values in base address [15:12] would be cleared because the asso- ciated mask bits are cleared (see rule on page 105). lastly, the memory target can not be smaller than 4 kb. figure 5-12. i/o space lbar - variable target size figure 5-13. memory space lbar addr[15:4] i/o_mask compare base_addr hit [15:4] [15:4] addr[31:12] mem_mask compare base_addr hit [31:12] [31:12] note: the memory mask is always 20 bits, which is equal to the number of memory base address bits. amd geode? cs5535 companion device data book 107 diverse integration logic 31506b 5.6.1.4 miscellaneous block special cycles are sent to the miscellaneous block. they are decoded as given in table 5-10. note that the halt spe- cial cycle depends on the value of the spec_cyc_md bit in msr_leg_io (msr 51400014h[28]). soft irq and soft reset msrs are decoded within the mis- cellaneous block. each block in the diverse device generates an output to the divil. the divil dom has a port for each of the func- tions and is responsible for selecting between them. 5.6.2 standard msrs this block contains the standard geodelink device msrs and their associated logic. these standard msrs are: capabilities, master configuration, smi control, error con- trol, power management, and diagnostics. the capabili- ties, master configuration, and diagnostic msrs are ?passive? in that they contain values that have an effect elsewhere. the other msrs have various ?active? bits that are set and cleared via hardware/software interactions. table 5-10. special cycle decodes cycle type address function action write 00h shutdown send shutdown pulse to msr_error. send shutdown pulse to msr_smi. if reset_shut_en (msr 51400014h[31]) is high, send reset pulse to power management indicating shutdown reset. spec_cyc_md (msr 51400014h[28]) = 0 write 01h halt send halt pulse to msr_smi. spec_cyc_md (msr 51400014h[28]) = 1 write 02h halt send halt pulse to msr_smi. all other values x86 special discard with no side effects. all other values not defined discard with no side effects. read 00h interrupt ack send cycle to pic. geodelink adapter generates back-to-back bus cycles. all other values not defined ret urn zero with no side effects. 108 amd geode? cs5535 companion device data book programmable interval timer 31506b 5.7 programmable interval timer the programmable interval timer (pit) generates pro- grammable time intervals from the divided clock of an external clock signal of a crystal oscillator. the pit (8254) has six modes of operation. figure 5-14 shows the block diagram of the pit and its connectivity to the local bus. the 8254 is comprised of three independently programma- ble counters. each counter is 16 bits wide. a 14.318 mhz external clock signal (from a crystal oscillator or an external clock chip) is divided by 12 to generate 1.19 mhz, which is used as a clocking reference for these three counters. each counter is enabled or triggered with its gate signal. based on the counting mode, the counter concerned is activated by a high level or a low-to-high transition of its gate signal. each counter has its output signal, whose shape is depen- dent upon the counter?s operational mode. the control register loads the counters a nd controls the various modes of operation. this control register controls the operation mode of the control logic (counter state machine), which in turn controls the counter, the high-order and low-order out- put latches. a status latch is also present in the 8254 and is used to output status information. features include: comprised of three 16-bit wide counters. supports read-back and counter latch commands. supports six modes of counting. allows several counter latch commands in parallel with the read-back command. figure 5-14. pit block diagram cpu local bus pit shadow divide by 12 timer 0 timer 1 timer 2 geodelink? adapter control c c 14 mhz register register amd geode? cs5535 companion device data book 109 programmable interval timer 31506b 5.7.1 programming the 8254 pit programming of the 8254 pit is initiated by first writing one control word via i/o address 043h into the pit mode con- trol word register. it is followed by writing one or two data bytes via the i/o address of the intended counter. if the control register is loaded once, the counters may be over- written with different values without accessing the control register again. table 5-11 lists the i/o addresses of the various registers. the control register in the 8254 pit is write-only, but cer- tain control information can be determined by the read- back (read-status) command. 5.7.1.1 write to the counters to load a counter with new values, a control word needs to output that defines the inte nded counter, number and type of bytes to write, the counting mode and the counting for- mat. bits [5:4] of the contro l word register (see section 6.8.2.7 on page 347) indicate whether low-order or high- order or both are going to be written. if low-order or high- order counter byte only is specified to be written, then only that byte can be read during a read access. according to bits [5:4] of the control word register, one needs to write either the low-order or the high-order or both into the counter after passing the control word. if bits [5:4] of the control word register is 11, then a low-order byte needs to be written first, followed by a high-order byte. for small counting values or counting values that are multiples of 256, it is sufficient to pass the low-order or high-order counter byte. bits [3:1] of the control word register define the counting mode of the counter selected by bits [5:4]. bit 0 of the control word register defines the binary or bcd counting format. the maximum loadable count value is not ffffh (binary counting) or 9999 (bcd counting), but 0. on the next clk pulse the counte r concerned jumps to ffffh or 9999. once the value is decreased to 0 again, it outputs a signal according to the programmed mode. therefore, the value 0 corresponds to 2^16 for binary counting and 10^4 for bcd counting. read from the counters there are three options for reading a counter in the 8254 pit: 1) counter latch command 2) read-back (read-status) command 3) direct read to read a counter, the third option (direct read) should not be used. the counter latch command or read-back com- mand should be used to transf er the current state of the counter into its output latches. one or two successive read counter instructions for the port address of the counter con- cerned reads these latches. if only the low-order or high- order byte was written when the counter was loaded with the initial counting value, then read the current counting value of the initially written byte by a single read counter instruction. if both the lo w-order and high-order counter bytes are written previously, then to read the current counter value, two read counter instructions are needed. the 8254 pit returns the low-order byte of the 16-bit counter with the first read co unter instruction, and then the high-order byte with the second read counter instruction. if the content of the counter has been transferred once by a counter latch command into the output latches, then this value is held there until t he cpu executes one or two counter read instructions, or until the corresponding counter is reprogrammed. successive counter latch com- mands are ignored if the out put latches haven?t been read before. figure 5-15 shows the format of the control word for the counter latch command. figure 5-15. pit counter latch command format table 5-11. 8254 pit register ports i/o address register access type 040h counter 0 read/ write 041h counter 1 read / write 042h counter 2 read / write 043h control word write bits [7:6] = select counter to latch 7654321 0 00xxxx 110 amd geode? cs5535 companion device data book programmable interval timer 31506b the read-back command present in the 8254 pit is used to determine the current counter value and its status like counting format, the counting mode, the low-order or high- order byte or both being read or written, and the status of its output. figure 5-16 shows the format of the read-back command. the two most signif icant bits define the read- back command with their value 11b. ct and st indicate that the value and the status of the counter are to be deter- mined respectively. the c0-c2 bits define the counter whose value or status is to be determined. with the read- back command, several counter latch commands can be issued in parallel by indicating several counters simulta- neously with the c0-c2 bits. the 8254 then behaves as if several counter latch commands have been issued individ- ually, and transfers the individual count values into the out- put latches of each counter. all successive counter latch commands, whether issued by its own counter or a next read-back command, are ignored if the counter concerned has not been read by counter read instructions. to deter- mine the programmed mode of a particular counter, set ct = 1 and st = 0. the read-back command latches the current mode and provides a status byte (see figure 5-17) at the port address of the counter concerned. this status byte is fetched by a counter read instruction. the pin bit indicates the current status of the concerned counte r?s output pin. if pin = 1, then the counter output is at l ogic 1, else at logic 0. bit 0 shows whether the last written counter value has already been transferred to the counter. not before zero = 0 is it meaningful to read back the counter value. figure 5-16. pit read-back command format figure 5-17. pit status byte format ct: determine count value of selected counter. 0 = determine count value. 1 = do not determine count value. st: determine status of selected counter. 0 = determine count status. 1 = do not determine count status. c2, c1, c0: counter selection. 0 = counter not selected. 1 = counter selected. 7654321 0 ct st c2 c1 c0 x 1 1 pin: status of co unter output pin: 0 = output pin low. 1 = output pin high. load: is counter loaded with a start value? 0 = counter loaded, count value can be read. 1 = counter not yet loaded, count value cannot be read. lh: corresponds to bits [5:4] of the control word register. mode: corresponds to bits [3:1] of the control word register. bcd: corresponds to bit 0 of the control word register. 76543210 lh mode bcd load pin amd geode? cs5535 companion device data book 111 programmable interrupt control 31506b 5.8 programmable interrupt control the programmable interrupt control subsystem (pic) is illustrated in figure 5-18. the major modules are the map- per and masks (mm), extended pic (xpic), and legacy 8259a pic (lpic). features two x86 compatible 8259as 15-level priority controller programmable interrupt modes individual request mask capability individual edge/level controls complete 8259a state read back via shadow registers mapper routes 62 inputs to 15 legacy interrupts and one asynchronous system management interrupt (asmi) all 62 inputs individually maskable and status readable (msrs 51400020h-51400027h or pic i/o offsets 00h- 1ch, see section 6.9.1 on page 350) 5.8.1 mapper and masks this block maps and masks up to 62 interrupt sources to 60 discrete extended pic (xpi c) inputs. the sources are organized into four groups: 1) 15 primary pre-defined inputs (see table 5-12) 2) 15 lpc inputs pre-defined (see table 5-12) 3) 16 unrestricted y inputs (see table 5-13) 4) 16 unrestricted z inputs (see table 5-14) the outputs are organized into 16 groups of four signals each, except groups 0 and 2; they have two signals each. each group is called an interrupt group (ig). each pre- defined input is mapped to a specific ig. each unrestricted input can be mapped to any ig except ig0. regardless of mapping, any interrupt source can be masked to prevent participation in the interrupt process. once the input to out- put map is established along with the mask values, signal flow from input to output is always completely combina- tional. figure 5-18. pic subsystem primary input 0 primary input 1 primary input 3 primary input 4 primary input 15 lpc input 0 lpc input 1 lpc input 3 lpc input 4 lpc input 15 unrestricted y input 0 unrestricted y input 1 unrestricted y input 2 unrestricted y input 3 unrestricted y input 15 unrestricted z input 0 unrestricted z input 1 unrestricted z input 2 unrestricted z input 3 unrestricted z input 15 mapper and masks (mm) ig0 (note) ig1 ig2 (note) ig3 ig4 ig5 ig6 ig7 ig8 ig9 ig10 ig11 ig12 ig13 ig14 ig15 irq0 irq1 (irq2) irq3 irq4 irq5 irq6 irq7 irq8 irq9 irq10 irq11 irq12 irq13 irq14 irq15 extended pic (xpic) legacy 8259a pics (lpic) asmi intr : : : : note: the outputs are organized into 16 groups of four signals eac h, except ig0 and ig2; they have two signals each. 112 amd geode? cs5535 companion device data book programmable interrupt control 31506b table 5-12. irq map - primary and lpc input # primary sources lpc sources legacy irq input 0 8254 timer irq lpc irq0 8254 timer input 1 kel irq1 lpc irq1 keyboard n/a none (slave controller) none none input 3 reserved - grounded lpc irq3 uart input 4 reserved - grounded lpc irq4 uart input 5 reserved - grounded lpc irq5 parallel port 2 input 6 reserved - grounded lpc irq6 floppy input 7 reserved - grounded lpc irq7 parallel port1 input 8 rtc periodic irq lpc irq8 rtc input 9 reserved - grounded lpc irq9 undefined input 10 reserved - grounded lpc irq10 undefined input 11 reserved - grounded lpc irq11 undefined input 12 kel irq12 lpc irq12 mouse input 13 float point error irq lpc irq13 fpu input 14 primary ide channel irq lpc irq14 primary ide input 15 reserved - grounded lpc irq15 secondary ide amd geode? cs5535 companion device data book 113 programmable interrupt control 31506b table 5-13. irq map - unrestricted sources y unrestricted y source comment input 0 software generated irq input 1 usb1 irq input 2 usb2 irq input 3 rtc alarm this is a pulse from the rtc. must use edge triggered inter- rupt, that is, level interrupt will not work. input 4 audio irq or of all audio codec interrupts and master interrupts. input 5 power management sci or of all possible power management system control inter- rupts (scis). input 6 nand flash ready ready to perform nand write or read. input 7 nand flash distraction nor access occurred during nand operation causing a nand abort or distraction. input 8 reserved, grounded input 9 reserved, grounded input 10 reserved, grounded input 11 reserved, grounded input 12 smb controller irq input 13 kel emulation irq input 14 uart 1 irq input 15 uart 2 irq table 5-14. irq map - unrestricted sources z unrestricted z source comment input 0 mfgpt_comp_1a or of mfgpt_comp_1 0 and 4. input 1 mfgpt_comp_1b or of mfgpt_comp_1 1 and 5. input 2 mfgpt_comp_1c or of mfgpt_comp_1 2 and 6. input 3 mfgpt_comp_1d or of mfgpt_comp_1 3 and 7. input 4 mfgpt_comp_2a or of mfgpt_comp_2 0 and 4. input 5 mfgpt_comp_2b or of mfgpt_comp_2 1 and 5. input 6 mfgpt_comp_2c or of mfgpt_comp_2 2 and 6. input 7 mfgpt_comp_2d or of mfgpt_comp_2 3 and 7. input 8 gpio interrupt 0 from gpio interrupt/pme mapper. input 9 gpio interrupt 1 from gpio interrupt/pme mapper. input 10 gpio interrupt 2 from gpio interrupt/pme mapper. input 11 gpio interrupt 3 from gpio interrupt/pme mapper. input 12 gpio interrupt 4 from gpio interrupt/pme mapper. input 13 gpio interrupt 5 from gpio interrupt/pme mapper. input 14 gpio interrupt 6 from gpio interrupt/pme mapper. input 15 gpio interrupt 7 from gpio interrupt/pme mapper. 114 amd geode? cs5535 companion device data book programmable interrupt control 31506b 5.8.2 extended pic (xpic) for each of 16 input igs of four signals each (except ig0 and ig2 with two signals each), xpic provides a four input ?or?. thus, 16 outputs are formed. a software readable xpic input request register (xirr) is available to read the status of the 64 inputs. outputs [0:1] and [3:15] are connected directly to the corresponding inputs on lpic. output 2 can be used as an asmi. 5.8.3 legacy pic (lpic) the lpic consists of two 8259a compatible programmable interrupt controllers (pics) connected in cascade mode through ir2 (see figure 5-19). the lpic devices support all x86 modes of operation except special fully nested mode. lpic contains mechanisms to: 1) mask any of the 15 inputs via an interrupt mask regis- ter (imr). 2) determine the input request status via an interrupt request register (irr). 3) generate an interrupt request (intr) to the processor when any of the unmasked requests are asserted. 4) provide an interrupt vector to the processor as part of an interrupt acknowledge operation based on request priorities. 5) determine which requests are acknowledged but not yet fully serviced, via an in-service register (isr). in addition to the above 8259a features, there are two reg- isters to control edge/level mode for each of the interrupt inputs as well as shadow registers to obtain the values of legacy 8259a registers that have not been historically readable. figure 5-19. cascading 8259as for lpic 8259a slave 8259a master inta int int inta d0-d7 d0-d7 irq0 irq1 irq2 irq3 irq4 irq5 irq6 irq7 irq8 irq9 irq10 irq11 irq12 irq13 irq14 irq15 ir0 ir1 ir2 ir3 ir4 ir5 ir6 ir7 ir0 ir1 ir2 ir3 ir4 ir5 ir6 ir7 note: cascading the 8259a pics. the int output of the slave is connected to the irq2 input of the master. amd geode? cs5535 companion device data book 115 programmable interrupt control 31506b as illustrated in figure 5-20, the blocks that make up the 8259a pic are: read/write control logic interrupt request register (irr) in-service register (isr) interrupt mask register (imr) priority resolver interrupt sequence data bus buffer cascade buffer/comparator read/write control logic the function of this block is to accept commands from the cpu. it contains the four in itialization command word reg- isters, icw1-icw4, and three operation command word registers, ocw1-ocw3, that can be programmed to oper- ate in various modes. irr, isr, and imr three registers are available to handle interrupts in the pic: interrupt request register (irr), in-service register (isr), and interrupt mask regist er (imr). each of the three registers is eight bits wide, where every bit corresponds to one of the ir0-ir7 input lines. priority resolver the priority resolver block manages the hardware requests according to their priority. as several bits may be set in the irr simultaneously, the priority encoder passes only the highest priority bit; ordered in priority 0 through 7 (0 being the highest). interrupt sequence the int output goes directly to the cpu interrupt input. when an int signal is activated, the cpu responds with an interrupt acknowledge access that is translated to two pulses on the inta input of the pic. at the first inta pulse the highest priority irr bit is loaded into the corresponding isr bit, and that irr bit is reset. the second inta pulse instructs the pic to present t he 8-bit vector of the interrupt handler onto the data bus. data bus buffer control words and status information are transferred through the data bus buffer. cascade buffer/comparator this functional block stores and compares the ids of the pics. figure 5-20. pic 8259a block diagram internal bus interrupt mask register (imr) in-service register (isr) priority resolver interrupt request register (irr) control logic data bus buffer read/ write logic cascade buffer/ comparator inta int d7-d0 rd wr a0 cs cas0 cas1 cas2 sp/en ir0 ir1 ir2 ir3 ir4 ir5 ir6 ir7 116 amd geode? cs5535 companion device data book programmable interrupt control 31506b 5.8.3.1 interrupt sequence there are three registers in the pic that control the inter- rupt requests: interrupt requ est register (irr), interrupt service register (isr), and interrupt mask register (imr). the eight interrupt lines ir0-ir7 are connected to the irr. the peripheral that requests an interrupt raises the signal at the corresponding ir0-ir7 inputs, which sets the corre- sponding bit in the irr. several peripheral devices can issue interrupt requests at the same time. the pic gates these requests under the inte rrupt mask register and under the priority of any interrupt service routine already entered (using the isr), and activates the pic?s output intr to the cpu. the cpu acknowledges the intr, generating two inta pulses. on the first, the priority encoder transfers (clears) the highest-priority enabled bit in the irr to the corresponding bit in the isr (sets). also, the two pics use their cascade connections to decide which one will be selected to respond further. on the second inta pulse, the selected pic presents the 8- bit pointer (called as vector data) onto the data bus. the cp u reads this pointer as the number of the interrupt handler to call. software writes a command (eoi) at the end of the inter- rupt subroutine, which clears the appropriate isr bit. initialization and programming two types of command words are generated by the cpu to program the pic: 1) initialization command word (icw): the pic is first initialized by four icws (icw1-icw4) before any nor- mal operation begins. the sequence is started by writ- ing initialization command word 1 (cw1). after icw1 has been written, the controll er expects the next writes to follow in the sequence icw2, icw3, and icw4 if it is needed. 2) operation command word (ocw): using these three ocws (ocw1-ocw3), the pic is instructed to operate in various interrupt modes. these registers can be written after the initialization above. icws and ocws must be programmed before operation begins. since both the pics are casc aded, the icw3 of the master pic should be programmed with the value 04h, indicating that the irq2 input of the master pic is connected to the int output of the slave pic, rather than the i/o device. this is part of the system initializa tion code. also, icw3 of the slave pic should be programmed with the value 02h (slave id) as that corresponds to the input on the master pic. for accessing the pic?s registers, two ports are available for the master and slave. table 5-15 lists the addresses and read/write data for these registers. 5.8.3.2 interrupt modes fully nested mode the interrupt requests are ordered in priority from 0 through 7. the highest priority request is processed and its vector data placed on the bus. the corresponding isr bit is set until the trailing edge of the last inta. while the isr bit is set, all other interrupts of the same or lower priority are inhibited, while higher levels will be acknowledged only if the cpu?s internal interrupt enable flip-flop has been re-enabled through software. end of interrupt (eoi) mode the isr bit can be reset by a command word that must be issued to the pic before returning from a service routine. eoi must be issued twice if in cascade mode, once for the master and once for the slave. there are two forms of eoi: specific and non-specific. when a non-specific eoi is issued, the pic automatically resets the isr bit corresponding to the highest priority level in service. a non-specific eoi can be issued with ocw2 (eoi = 1, sl = 0, r = 0). a specific eoi is issued when a mode is used that may dis- turb the fully nested structure and the pic might not be able to determine the last interrupt level acknowledged. a specific eoi can be issued with ocw2 (eoi = 1, sl = 1, r = 0, and l0-l2 is the binary level of the isr bit to be reset). automatic end of interrupt (aeoi) mode the pic automatically performs a non-specific eoi at the trailing edge of the last inta pulse. this mode is not sup- ported in the geode cs5535 companion device. table 5-15. 8259a pic i/o addresses and i/o data i/o address irq0-irq7 (master) i/o address irq8-irq15 (slave) read data write data 020h 0a0h irr isr icw1 ocw2 ocw3 021h 0a1h imr icw2 icw3 icw4 ocw1 (imr) amd geode? cs5535 companion device data book 117 programmable interrupt control 31506b automatic rotation mode in cases where a number of irqs have equal priority, the device that has been serviced, will receive the lowest prior- ity. so now that device, if requesting another interrupt, must wait until the other seven devices have been ser- viced. there are two ways to accomplish automatic rotation using ocw2: rotation on the non-specific eoi command (r = 1, sl = 0, eoi = 1). rotation in automati c eoi mode, which is set by (r = 1, sl = 0, eoi = 0) and cleared by (r = 0, sl = 0, eoi = 0). specific rotation mode priorities can be changed by programming the bottom pri- ority, which fixes all other priorities. for example, if ir5 is programmed as the bottom priority device, then ir6 will have the highest priority. the command is issued to ocw2 (r = 1, sl = 1, and l0-l2 is the binary priority level code of the bottom priority device). special mask mode in this mode, when a mask bit is set in ocw1, it inhibits further interrupts at that level and enables interrupts from all other levels (lower as well as higher) that are not masked. the special mask mode is set (ssmm = 1, smm = 1) and cleared (ssmm = 1, smm = 0) by ocw3. 5.8.4 pic subsystem operation from reset, the pic subsystem comes up in legacy mode. the ?primary? mapper and mask inputs connect directly to lpic and all other interrupt sources are masked off. while there are a number of different ways to use the pic subsystem, the discussions that follow assume a mix of ?level? and ?edge? interrupt inputs. the first discussion assumes the os schedules the ?work? of the interrupt ser- vice after a brief interrupt service routine. the second dis- cussion assumes the os perfo rms the ?work? real-time in the interrupt service routine. assume the mapper and masks have been established as desired. ?level? interrupts can be shared, but ?edge? inter- rupts cannot. this means an xpic ?level? output can be driven by up to four mapper and masks inputs. further, this means an xpic ?edge? output can only be driven by one mapper and mask input. assume all edge interrupts generate a low-to-high edge to indicate an interrupt. assume active low interrupts are inverted outside the pic subsystem as needed; that is, all mm inputs are active high. an external pci bus uses active low interrupts that can be shared in an open-collector wired ?or? fashion. this is ok. on -chip, the interrupt sense is inverted. lastly, note that for the edge interrupts the edge must remain high until the interrupt acknowledge action. assume lpic is initialized as follows: ;set initialization command words (icws) ;all values are in hex ;pic #1 (master) out 20, 11 ; icw1 - edge, master, icw4 needed out 21, 8 ; icw2 - interrupt vector table offset is 8 out 21, 4 ; icw3 - master level 2 out 21, 1 ; icw4 - master, 8086 mode out 21, ff ; mask all irqs ;pic #2 (slave) out a0, 11 ; icw1 - edge, slave icw4 needed out a1, 70 ; icw2 - interrupt vector table offset 70 out a1, 2 ; icw3 - slave level 2 out a1, 1 ; icw4 - slave, 8086 mode out a1, ff ; mask all irqs ;use operation control words (ocws) during interrupt service thus, the lpic 8259as all start in edge mode. this is fol- lowed by writes to the individual edge level registers at 4d0h (interrupts 0-7) and 4d1h (interrupts 8-15) to estab- lish level mode for all level in puts. note th at irq0 and irq2 can not be put in level mode. writing 0ffh to 4d0h will read back 0fah. scheduled interrupts approach the following set of events would be typical. assume the processor has maskable interrupts enabled: 1) one or more interrupts are generated in the system. these set the associated bits in the lpic interrupt request register (irr). 2) the maskable interrupt signal (intr) is asserted by the lpic and interrupts the processor. intr is an active high level. 3) the processor generates an interrupt acknowledge bus cycle that flows through the geodelink? system as a single bizzaro packet. when it reaches the diverse logic, it is converted to the two cycle interrupt acknowledge sequence expected by the lpic. 4) the acknowledge operation returns an interrupt vector to the processor that is used to call the appropriate interrupt service routine. processor interrupts are now disabled at the processor. 5) the acknowledge operation also selects the highest priority interrupt from the ir r and uses it to set one bit in the lpic interrupt service register (isr). each acknowledge operation always sets a single isr bit. 118 amd geode? cs5535 companion device data book programmable interrupt control 31506b 6) the acknowledge operation generally de-asserts intr if there are no higher priority interrupts. how- ever, it is possible that another interrupt is generated in the system anytime after the acknowledge. any new interrupts will appear in the irr. if they are higher pri- ority than the current interrupt, then the intr is re- asserted. since interrupts ar e disabled at the proces- sor, intr remaining high or going high during the interrupt service routine has no effect until interrupts are explicitly enabled again at the processor by the interrupt service routine or implicitly enabled when a return-from-interrupt is executed. 7) the interrupt service rout ine masks off the interrupt in the lpic interrupt mask register (imr). the interrupt service routine interacts with the os to schedule calls to the drivers associated with the interrupt. if level, one or more drivers could be associated. if edge, only one driver could be associated. the service executes a return-from-interrupt. 8) the os calls the drivers associated with the interrupt as scheduled. each driver checks its associated device to determine service needs. if no ?need?, the driver returns to the os without any action. if ?need?, the driver performs the interrupt action, clears the interrupt source, and returns to the os. when all the scheduled drivers have been called, the os un-masks the interrupt at lpic. note that the individual drivers do not directly interact with lpic. note in the above procedure that there is not a need to handle ?level? and ?edge? types separately as long as ?edge? types are not shared. real-time interrupts approach the following discussion assumes the ?work? associated with the interrupt is performed in the interrupt service rou- tine. the setup and steps 1 through 6 are the same: 1) if there is only one driver associated with the interrupt, it is called at this point. if more than one driver (shared), then they could be called in order to deter- mine ?need?. alternately, the xirr could be read to directly identify the source. 2) depending on the event being serviced and the os policies, the processor will enable interrupts again at some point. potentially, this will generate another higher priority interrupt causing the current service routine to nest with another interrupt acknowledge cycle. for a nest operation, an additional bit will be set in the isr. 3) eventually, the highest priority service routine is run- ning and intr is de-asserted. the service calls the driver(s) associated with the interrupt. the driver com- pletes the interrupt ?work?, clears the interrupt at its system source, and returns to the interrupt service routine. 4) the interrupt service routine disables interrupts at the processor and prepares to return to a lower priority service routine or the initially interrupted process. it writes an end-of-interrupt (eoi) command (020h) to the lpic ocw2 register. this clears the highest prior- ity isr bit. one eoi always clears one isr bit. the service routine executes a return-from-interrupt that enables interrupts again at the processor. 5) it is possible for intr to assert from the same interrupt as soon as eoi is written. the initial interrupt acknowl- edge action copies the bit to the isr. for edge mode, the initial interrupt acknowledge action also clears the bit in the irr. for level, irr always reflects the level of the signal on the interrupt port. after the interrupt acknowledge for edge mode, another edge could set the bit in the irr before the eoi. if in level mode, another shared interrupt could be keeping the input high or potentially the initial interrupt has occurred again, since the driver cleared the source but before the eoi. at any rate, if i rr is high at eoi, intr will immediately assert again. hence, the need to disable interrupts at the processor in step 10 above before writing the eoi. 6) eventually, all system events are serviced and control returns to the originally interrupted program. note that the above procedure did not use the interrupt mask register (imr), but variations on the above could have. lastly note, as in the first discussion, drivers do not directly interact with the lpic. amd geode? cs5535 companion device data book 119 direct memory access module 31506b 5.9 direct memory access module the direct memory access (dma) module supports indus- try standard dma architecture using two 8237-compatible dma controllers in cascaded configuration. figure 5-21 shows the dma module partitioning. it consists of two stan- dard 8237 dma controllers, a bus interface, address map- per, and source mapper. features 32-bit address range support via high page registers. supports the standard 7-channel dma configuration, out of which the four 8- bit channels are used. dma mapper to route dma sources to the four 8-bit dma channels. dma sources from the lpc bus, and from transmit and receive buffers from the two on-chip uarts are supported. allow the data bus to be released in between dma transfers during demand or bulk mode to allow transfers to the dma module or the module doing dma transfers. 5.9.1 dma controllers the core logic module supports seven dma channels using two standard 8237-equivalent controllers. dma con- troller 1 contains channels 0 through 3 and supports 8-bit i/o adapters. these channels are used to transfer data between 8-bit peripherals and system memory. using the high and low page address registers, a full 32-bit address is output for each channel so they can all transfer data throughout the entire 4 gb system address space. each channel can transfer data in 64 kb pages. dma controller 2 is unused. figure 5-21. dma module block diagram 8237 8237 data lbus i/f lpc i/f dma r/w controls dma requests dma acks bus interface and registers lpc and dma interfaces with dma mapper 120 amd geode? cs5535 companion device data book direct memory access module 31506b 5.9.2 dma transfer modes each dma channel can be programmed for single , block , demand or cascade transfer modes. in the most commonly used mode, single transfer mode, one dma cycle occurs per drq and the pci bus is released after every cycle. this allows the core logic module to timeshare the pci bus with the gx1 module. this is imperative, especially in cases involving large data transfers, because the gx1 module gets locked out for too long. in block transfer mode, the dma controller executes all of its transfers consecutively without releasing the pci bus. in demand transfer mode, dma transfer cycles continue to occur as long as drq is high or terminal count is not reached. in this mode, the dma controller continues to execute transfer cycles until the i/o device drops drq to indicate its inability to continue providing data. for this case, the pci bus is held by the core logic module until a break in the transfers occurs. in the geode cs5535 companion device design, block and demand transfers behave much like single transfer mode to avoid the lockout problem. in cascade mode, the channel is connected to another dma controller or to an isa bus master, rather than to an i/o device. in the core logic module, one of the 8237 con- trollers is designated as the master and the other as the slave. the hold output of the slave is tied to the drq0 input of the master (channel 4), and the master?s dack0# output is tied to the slave?s hlda input. in each of these modes, the dma controller can be pro- grammed for read , write, or verify transfers. both dma controllers are rese t at power-on reset (por) to fixed priority. since master channel 0 is actually connected to the slave dma controller, the slave?s four dma channels have the highest priority, with channel 0 as highest and channel 3 as the lowest. immediately following slave channel 3, master channel 1 (c hannel 5) is the next high- est, followed by channels 6 and 7. 5.9.3 dma controller registers the dma controller can be programmed with standard i/o cycles to the standard register space for dma. when writing to a channel's address or word count reg- ister, the data is written into both the base register and the current register simultaneously. when reading a channel address or word count register, only the current address or word count can be read. the base address and base word count are not accessible for reading. 5.9.4 dma transfer types each of the seven dma channels may be programmed to perform one of three types of transfers: read, write, or ver- ify . the transfer type selected defines the method used to transfer a byte or word during one dma bus cycle. for read transfer types, the dma controller reads data from memory and writes it to the i/o device associated with the dma channel. for write transfer types, the dma controller reads data from the i/o device associated with the dma channel and writes to the memory. the verify transfer type causes the dma controller to exe- cute dma transfer bus cycles, including generation of memory addresses, but neither the read nor write com- mand lines are activated. this transfer type was used by dma channel 0 to implement dram refresh in the original ibm pc and xt. 5.9.5 dma priority the dma controller may be programmed for two types of priority schemes: fixed and rotate . in fixed priority, the channels are fixed in priority order based on the descending values of their numbers. thus, channel 0 has the highest priority. in rotate priority, the last channel to get service becomes the lowest-priority channel with the priority of the others rotating accordingly. this pre- vents a channel from dominating the system. the address and word count registers for each channel are 16-bit registers. the value on the data bus is written into the upper byte or lower byte, depending on the state of the internal addressing byte pointer. this pointer can be cleared by the clear byte pointer command. after this command, the first read/write to an address or word- count register reads or writes to the low byte of the 16-bit register and the byte pointer points to the high byte. the next read/write to an address or word-count register reads or writes to the high byte of the 16-bit register and the byte pointer points back to the low byte. the dma controller allows t he user to program the active level (low or high) of the drq and dack# signals. since the two controllers are cascaded together internally on the chip, these signals should always be programmed with the drq signal active high and the dack# signal active low. amd geode? cs5535 companion device data book 121 direct memory access module 31506b 5.9.6 dma shadow registers the diverse integration logic module contains shadow registers (see section 6.13 on page 417) for reading the configuration of the dma controllers. 5.9.7 dma addressing capability dma transfers occur over the entire 32-bit address range of the pci bus. this is accomplished by using the dma controller?s 16-bit memory address registers in conjunction with an 8-bit dma low page register and an 8-bit dma high page register. these registers, associated with each channel, provide the 32-bit memory address capability. a write to the low page register clears the high page regis- ter, for backward compatib ility with the pc/at standard. the starting address for the dma transfer must be pro- grammed into the dma controller registers and the chan- nel?s respective low and high page registers prior to beginning the dma transfer. dma page registers and extended addressing the dma page registers provide the upper address bits during dma cycles. dma addre sses do not increment or decrement across page boundaries. page boundaries for the 8-bit channels (channels 0 through 3) are every 64 kb and page boundaries for the 16-bit channels (channels 5, 6, and 7) are every 128 kb. before any dma operations are performed, the page regis- ters must be written at the i/o port addresses in the dma controller registers to select the correct page for each dma channel. the other address locations between 080h and 08fh and 480h and 48fh are not used by the dma chan- nels, but can be read or written by a pci bus master. these registers are reset to zero at por. a write to the low page register clears the high page register, for back- ward compatibility with the pc/at standard. for most dma transfers, the high page register is set to zeros and is driven onto pci address bits ad[31:24] during dma cycles. this mode is ba ckward compatible with the pc/at standard. for dma extended transfers, the high page register is programmed and the values are driven onto the pci addresses ad[ 31:24] during dma cycles to allow access to the full 4 gb pci address space. 5.9.8 dma address generation the dma addresses are formed such that there is an upper address, a middle address, and a lower address por- tion. the upper address portion, which selects a specific page, is generated by the page registers. the page registers for each channel must be set up by the system before a dma operation. the dma page register values are driven on pci address bits ad[31:16] for 8-bit channels and ad[31:17] for 16-bit channels. the middle address portion, which selects a block within the page, is generated by the dma controller at the begin- ning of a dma operation and any time the dma address increments or decrements through a block boundary. block sizes are 256 bytes for 8-bit channels (channels 0 through 3) and 512 bytes for 16-bit channels (channels 5, 6, and 7). the middle address bits are driven on pci address bits ad[15:8] for 8-bit channels and ad[16:9] for 16-bit chan- nels. the lower address portion is generated directly by the dma controller during dma operations. the lower address bits are output on pci address bits ad[7:0] for 8-bit chan- nels and ad[8:1] for 16-bit channels. 5.9.9 dma mapper source selection for each 8-bit dma channel, the dma mapper allows the dma request to come from a number of sources. table 5- 16 shows how the dma mapper register select field selects the appropriate dma source. when lpc is selected as the dma source for dma chan- nel 0, the source is lpc dma channel 0. similarly, when lpc is selected as the source for dma channel 1, 2, or 3, then the dma sources for t hose three dma channels are respectively lpc dma channels 1, 2, and 3. therefore, lpc dma channel 0 can only be mapped to dma channel 0, lpc dma channel 1 can only be mapped to dma chan- nel 1, etc. table 5-16. dma source selection source selector value from dma mapper dma source 0 none (dma channel off) 1uart1 transmit 2 uart1 receive 3uart2 transmit 4 uart2 receive 5 reserved (not active) 6 reserved (not active) 7lpc 122 amd geode? cs5535 companion device data book keyboard emulation logic 31506b 5.10 keyboard emulation logic the keyboard emulation logic (kel) provides a virtual 8042 keyboard controller interface that is used to map non- legacy keyboard and mouse sources to this traditional interface. for example, universal serial bus (usb) sources are ?connected? to this interface via system man- agement mode (smm) software. it also allows mixed envi- ronments with one lpc legacy device and multiple new (usb) devices. it produces irq and asmi outputs. features provides a virtual 8042 keyboard controller interface. allows mixed environments. produces irq and asmi outputs. employs a clock control logic for power management purposes. no usb controller required for kel to operate. 5.10.1 keyboard emulation and port a the keyboard emulation logic (kel) with port a is illus- trated in figure 5-22. strictly speaking, these are separate functions. however, since they both effect the fa20# (force processor address bit 20 to zero when low), the two functions are implemented t ogether. the keyboard emula- tion logic is the most comp lex and is discussed first. figure 5-22. kel block diagram * * * port a write & read kel x control 32 32 88 usb1_sof local bus clock reset in out out in local bus data local bus data * * read-back multiplexer is not shown usb2_sof 1 khz clock keyboard emulator logic (kel) lpc_irq1 lpc_irq12 asmi emulationenable snoopenable fa20# init keyboard irq 1 (to pic subsystem) irq 12 (to pic subsystem) emulationinterrupt port a enable a20 keyboard init port a a20 port a port 060h and port 064h write port 060h read * port 064h read hce control hce input hce output hce status * * 14 mhz to 1 khz 14 mhz amd geode? cs5535 companion device data book 123 keyboard emulation logic 31506b 5.10.2 keyboard emulation overview the purpose of the kel is to model the legacy 8042 key- board/mouse controller interfaced via legacy i/o addresses 060h and 064h (also known as ports 60 and 64). this hardware and supporting processor system man- agement mode (smm) software are designed to support systems that do not have a true ps/2-compatible keyboard and/or mouse interface, but those that have alternative devices performing the equivalent function. generally, the alternative device is a keyboard or mouse off a usb (uni- versal serial bus) port, but it need not be. due to the ori- gins of the hardware to be explained shortly, this discussion generally assumes a usb alternative device, but this is not a requirement from a hardware perspective. the kel closely models the keyboard emulation hardware detailed in the usb openhost controller interface specifi- cation (ohci). it is specif ically designed to be software compatible with this model. in the usb model, it is part of the usb ?host controller?, but is logically separate from it. the discussion and description that follows is taken from the ohci specificatio n, but with modifications to reflect the geode cs5535 companion device specific implementa- tion. to support applications and drivers in non-usb-aware environments (e.g., dos), a peripheral subsystem needs to provide some hardware support for the emulation of a ps/2 keyboard and/or mouse by their usb equivalents (alternative devices). for ohci, this emulation support is provided by a set of registers that are controlled by code running in smm. working in conjunction, this hardware and software produces approximately the same behavior-to- application code as would be produced by a ps/2-compati- ble keyboard and/or mouse interface. when data is received from the alternative device, the emulation code is notified and becomes responsible for translating the alternative device keyboard/mouse data into a data sequence that is equivalent to what would be pro- duced by a ps/2-compatible keyboard/mouse interface. the translated data is made available to the system through the legacy keyboard interface i/o addresses 060h and 064h. likewise, when data/c ontrol is to be sent to the alternative device (as indicat ed by the system writing to the legacy keyboard interface), the emulation code is notified and becomes responsible for translating the information into appropriate data to be sent to the alternative device. on the ps/2 keyboard/mouse interface, a read of i/o address 060h returns the current contents of the keyboard output buffer; a read of i/o address 064h returns the con- tents of the keyboard status register. an i/o write to i/o addresses 060h and 064h puts data into the keyboard input buffer (data is being input into the keyboard sub- system). when emulation is enabled, reads and writes of i/o addresses 060h and 064h are captured in the kel hceoutput, hcestatus, and/or hceinput operational regis- ters. the kel described here supports a mixed environment in which either the keyboard or mouse is implemented as an alternative device and the other device is attached to a standard ps/2 interface. the following sub-sections use the term ?alternate device interrupt?. this is an asmi or irq as appropriate for the device; for example the usb can generate either an asmi or irq. the kel generates a separate asmi or irq. 5.10.3 theory - keyboard / mouse input when data is received from the alternative device, the emulation code is notified with an alternate device interrupt and translates the keyboard/mouse data into an equivalent ps/2-compatible sequence for presentation to the applica- tion software. for each byte of ps/2-compatible data that is to be presented to the applications software, the emulation code writes to the hce_outp ut register. the emulation code then sets the appropriate bits in the hce_status reg- ister (normally, outputfull is set for keyboard data and outputfull plus auxoutputfull for mouse data). if key- board/mouse interrupts are enabled, setting the hce_status register bits causes the generation of an irq1 for keyboard data and irq12 for mouse data. the emula- tion code then exits and waits for the next alternate device interrupt. when the host cpu exits from smm, it can service the pending irq1/irq12. this nor mally results in a read from i/o address 060h. when i/o address 060h is read, the kel intercepts the access and returns the current contents of hce_output. the kel also clears the outputfull bit in hce_status and de-asserts irq1/irq12. if the emulation software has multiple characters to send to the application software, it sets the characterpending bit in the hce_control register. this causes the kel to generate an asmi at the beginning of the next frame a time after the application read from i/o address 060h (hce_output.). 5.10.4 theory - keyboard output keyboard output is indicated by application software writ- ing data to either i/o addre ss 060h or 064h. upon a write to either address, the kel captures the data in the hce_input register and, exc ept in the case of a fa20# (force processor address bit 20 to zero when low) sequence, updates the hce_status register?s inputfull and cmddata bits. when the inputfull bit is set, a kel asmi is generated at the beginning of the next frame. upon receipt of the kel asmi, the emulation software reads hce_control and hce_status to determine the cause of the emulation interrupt and performs the opera- tion indicated by the data. generally, this means putting out data to the alternate device. 5.10.5 emulation events emulation events (ees) are caused by reads and writes of the emulation registers. ees generated by the emulation hardware are steered by the kel to either an asmi or an emulation interrupt. steering is determined by the ee routing (eer) bit of the keyboard emulation logic control register (kelx_ctl) (msr 5140001fh[1]). 124 amd geode? cs5535 companion device data book keyboard emulation logic 31506b historically, ees for data coming from the keyboard/mouse are generated on usb frame boundaries. the kel is inde- pendent of the usb logic, but uses usb frame boundaries for backward compatibility. alternately, an independent 1 ms counter can be used (msr 5140001fh[3:2]). at the beginning of each frame, the conditions that define asyn- chronous ees are checked and, if an ee condition exists, the ee is signaled to the host. this has the effect of reduc- ing the number of ees that are generated for legacy input to no more than 1,000 per second. the number of emula- tion interrupts is limited because the maximum rate of data delivery to an application cannot be more than 1,000 bytes per second. a benefit of this rule is that, for normal key- board and mouse operations, only one ee is required for each data byte sent to the application. additionally, delay of the ee until the next start of frame causes data persis- tence for keyboard input data that is equivalent to that pro- vided by an 8042. 5.10.6 theory - kel ees there are three ees that produce the signal kel asmi. these three ees are: character pending, input full, and external irq. an a20 sequence is a possible input full ee. the a20sequence bit in the hce_control register (kel memory offset 100h[5]) will be set in this case. the signal kel asmi is an active high pulse one local bus clock in width and sent to the diverse integration logic (divil). this signal is only asserted when the emulationenable bit in hce_control is high (kel memory offset 100h[0] = 1), that is, emulation is enabled. for an ee, kel also option- ally produces an emulation irq (kel_emu_irq). this signal is a level and is only asserted when the ee routing (eer) bit in msr_kelx_ctl (msr 5140001fh[1]) is low. de-asserting kel_emu_irq requires clearing the appro- priate bit in the hce_control or kel hce_status registers (kel memory offset 100h and 10ch). for the keyboard a20sequence, kel sets the kel_a20_asmi_flag if enabled in the divil. keyboard init and a20 are generated as appropriate when emulation is enabled or snoop is enabled in msr_kelx_ctl. kel asmi is generated as appropriate when emulation is enabled. kel asmi is not generated when emulation is disabled and snoop is enabled. key- board a20 under snoop does not require service beyond the divil gld_msr_smi (msr 51400002h); that is, kel does not need to be manipulated. the inputfull bit in hce_status (kel memory off set 10ch[1]) will set, but does not require service. each new keyboard a20sequence will set the kel_init_asmi_flag if enabled. if a write to port a changes the value of bit 1, the kel sets the porta_a20_asmi_flag if en abled in the divil. if bit 0 of port a is written to a 1, kel sets the porta_init_asmi_flag if enabled in t he divil. it also sets port a to the value 2; that is, only bit 1 is high. the a20state bit in hce_control (kel memory offset 100h[8]) is not effected. the rate of application software reading of i/o address 060h is dependent on the alternate device interrupt rate or sofevent (start of frame event, msr 5140001fh[3:2]) when the characterpending bit is used in the hce_control register (kel memory offset 100h[2]). there is one kel ee per application software read of i/o address 060h when characterpending is set. the rate of application software writing of i/o addresses 060h and 064h is no greater than sofevent. generally, there is one kel ee per appl ication write to i/o address 060h. sofevent is used to emul ate normal delays associated with a real 8042 controller and ps/2 device. its source is established via msr 5140001fh[3:2]. its value is 1 ms frame interval. 5.10.7 theory - mixed environment a mixed environment is one in which an alternate device and a ps/2 device are supported simultaneously (e.g., a usb keyboard and a ps/2 mouse). the mixed environ- ment is supported by allowing the emulation software to control the ps/2 interface. control of this interface includes capturing i/o accesses to i/o addresses 060h and 064h and also includes capture of interrupts from the ps/2 key- board controller off the lpc. irq1 and irq12 from the lpc keyboard controller are routed through the kel. when external-irqen in hce_co ntrol (kel me mory offset 100h[4]) is set, irq1 and irq12 from the legacy keyboard controller are blocked at the kel and an asmi is gener- ated instead. this allows the emulation software to capture data coming from the legacy controller and presents it to the application through the emulated interface. the behav- ior of irq1 and irq12 with respect to externalirqen and irqen bits is summarized in table 5-17. table 5-17. kel mixed environment emulation enable external irqen irqen lpc_irq1 lpc_ irq12 output full output fullaux irq1 active irq12 active action 101001000irq1 101000100irq12 x10010001ee x10100010ee amd geode? cs5535 companion device data book 125 keyboard emulation logic 31506b 5.10.8 theory - force a20 low sequence the fa20 sequence occurs frequently in dos applica- tions. mostly, the sequence is to set fa20 high; that is, do not force address bit 20 to a 0. high is the default state of this signal. to reduce the number of asmis caused by the a20 sequence, kel generates an asmi only if the gatea20 sequence would change the state of a20. the a20 sequence is initiated with a write of d1h to i/o address 064h. on detecting this write, the kel sets the a20sequence bit in hce_control (kel memory offset 100h[5]). it captur es the data byte in hce_input (kel memory offset 104h[7:0]), but does not set the inputfull bit in hce_status (kel memory offset 10ch[1]). when a20sequence is set, a write of a value to i/o address 060h that has bit 1 set to a value different than a20state in hce_control (kel memory o ffset 100h[8]) causes input- full to be set and causes an asmi. an asmi with both inputfull and a20sequence set indicates that the applica- tion is trying to change the setting of fa20 on the keyboard controller. however, when a20sequence is set, and a write of a value to i/o address 060h that has bit 1 set to the same value as a20state in hce_control is detected, then no asmi will occur. as mentioned above, a write to i/o address 064h of any value other than d1h causes a20sequence to be cleared. if a20sequence is active and a value of ffh is written to i/o address 064h, a20sequence is cleared but inputfull is not set. a write of any value other than d1h or ffh causes inputfull to be set, which then causes an asmi. a write of ffh to i/o address 064h when a20sequence is not set causes inputfull to be set. the current value of the a20_mask is maintained in two unconnected places. the a20state bit in hce_control and bit 1 in port a. the value of a20state is only changed via a software write to hce_control. it is set to 0 at reset. the value of bit 1 in port a changes on any write to port a. from reset porta[1] is 1. 5.10.9 theory - processor initialize sequence the processor initialization sequence is possible if either of the following cases is true: a write of a value fed to i/o address 064h indicates processor initialization (init) or warm reset. this sets kel_init_asmi_flag if enabled in the divil. all hce registers and port a are not effected. port a initialization, init will respond to: write 01h to i/o address 092h. (refer to section 5.10.10 "port a".) 5.10.10 port a this register is at i/o address 092h. it can also be used to change the state of a20 or to cause an init. when 8-bit data that has its bit 0 set to 1 is written, it causes an init. however, if bit 1 of the 8-bit data is set to 1, it causes a change in the state of a20 (a20 gets asserted). as above, an asmi is only generated on an init or a20 event. the init operation always forces a20 high. writes to bits 2 and higher are a ?don?t care?. reads to port a always return 00h or 02h depending on the state of the bit 1 of port a. note that a20 can be changed with port a or the gatea20 sequence. another important point is that a20state in hce_control and bit 1 in port a are independent from each other. writing a 1 to port a bit 1 does not effect the a20state bit. changing the state of the a20state bit does not effect the bit 1 of port a. note that when a20 has a value of 0, it means that the sec- ond mb wraps to the first mb. however, a value of 1 means that a20 is not modified. the following statements summarize the above init and a20 sequences : init will respond to: write 01h to i/o address 092h or feh to i/o address 064h. a20 toggle will respond to: write 02h to address 092h or write 00h to address 092h (bit 1 toggles, bit 0 held at 0), and write d1h to i/o address 064h then write a value to i/o address 060h that has bit 1 set to a value different than the a20state in hcecontrol register. trapping will insure the smi is taken on the instruction boundary. a keyboard init will not re spond to: write d1h to i/o address 064h followed by a write 02h to i/o address 060h (set bit 0 to 0). 5.10.11 keyboard emulation logic msrs in addition to hce_control (kel memory offset 100h), there is a kel extended control msr, msr_kelx_ctl (msr 5140001fh), to provide additional features. a ?snoop? feature is used when an external lpc based keyboard controller is used (while the kel is not enabled). all i/o accesses to i/o addresses 060h and 064h proceed to the lpc, but the kel snoops or watches for the a20 and init sequences. if these occur, kel sets kel_a20_asmi_flag or ke l_init_asmi_flag in the divil if enabled. ees may be routed such that they generate an irq or asmi. in the case of emulation irq, the clearing is done by an operation on the appropriate hce_control or hce_status registers. reading the ee routing bit is not required for emulation processing via irq. this bit does not effect asmis associated with a20 and init operations. all asmi signals are a single clock pulse wide. sofevent (start of frame even t) is establis hed with bits [3:2] of msr 5140001fh . these bits provide alternative sources for sofevent. the sofevent can be sourced from usb1, usb2, or the pit. a 00 value selects the test mode. the port a enable bit is a mask bit for port a and its default state is high. 126 amd geode? cs5535 companion device data book keyboard emulation logic 31506b 5.10.12 related diverse device functions fa20# and init are not passed directly to the processor. ssm code manipulates equivalent functions in the proces- sor. the hce registers are consi dered part of the usb opera- tional register set for some software and hence share the same memory mapped register space. the gliu descrip- tor for the usbs, msr_lbar_kel1, and msr_lbar_kel2 must all be set to the same base. the gliu will route accesses at memory offset 100h and above to the diverse device and accesses below 100h to the usb. the address decoder in the divil routes accesses to i/o addresses 060h and 064h to the kel or lpc based on the value of emulationenable in hce_control (kel memory offset 100h). if snoop mode is enabled and the emulation- enable bit is not set, writes are made directly to both the kel and lpc. the lpc irq1 and irq12 outputs are connected to both kel and the pic subsystem. masking logic in the sub- system allows the lpc interrupts to be used directly or the kel set can be used. the kel asmi is routed through the diverse device?s standard gld_msr_smi (msr 51400002h). it may be masked off there, but it is only cleared via msr_kelx_ctl (msr 5140001fh). 5.10.13 emulation event decode emulation events are of two types: frame synchronous and asynchronous. the conditions for a frame synchronous interrupt are sampled by the kel at each sof interval and, if an event condition exists, it is signaled at that time. for asynchronous events, the event is signaled as soon as the condition exists. the equation for the synchronous emulation event condi- tion is: synchronousevent = hce_control.emulationenable (kel memory offset 100h[0]) and hce_control.characterpending (kel memory offset 100h[2]) and not hce_status.outputfull (kel memory offset 10ch[0]). when this decode is true, an emulation event is generated at the next sof. the event condition is latched until the decode becomes false. the equation for the asynchronous emulation event condi- tion is: asynchronousevent = hce_control.emulationenable (kel memory offset 100h[0]) and hce_status.inputfull (kel memory offset 10ch[1]), or hce_control.externlirqen (kel memory offset 100h[4]) and hce_control.irq1active (kel memory offset 100h[6]) or hce_control.irq12active (kel memory offset 100h[7]). amd geode? cs5535 companion device data book 127 system management bus controller 31506b 5.11 system management bus controller the system management bus (smb) controller is a two- wire synchronous serial interface compatible with the sys- tem management bus physical layer. the smb controller is also compatible with intel's smbus and philips? i 2 c. the smb controller can be configured as a bus master or slave, and can maintain bidirectional communication with both multiple master and slave devices. as a slave device, the smb controller may issue a request to become the bus master. the smb controller allows easy interfacing to a wide range of low-cost memories and i/o devices, including: eeproms, srams, timers, adc, dac, clock chips, and peripheral drivers. this chapter describes the g eneral smb controller func- tional block. a device may include a different implementa- tion. a block diagram of the s ystem management bus (smb) controller is shown figure 5-23. the smb controller is upward compatible with previous industry standard two-wire interfaces as detailed in table 5-18 on page 128. the smb controller?s protocol uses a two-wire interface for bidirectional communication between the ics connected to the bus. the two interface lines are the serial data line (sdl) and the serial clock line (scl). these lines should be connected to a positive supply via an internal or external pull-up resistor, and remain high even when the bus is idle. each ic has a unique address and can operate as a trans- mitter or a receiver (though some peripherals are only receivers). during data transactions, the master device initiates the transaction, generates the clock signal, and terminates the transaction. for example, when the smb controller ini- tiates a data transaction with an attached smb compliant peripheral, the smb controller becomes the master. when the peripheral responds and transmits data to the smb controller, their master/slave (data transaction initiator and clock generator) relationship is unchanged, even though their transmitter/receiver functions are reversed. figure 5-23. smb block diagram data in data in local bus interface ccu pic busy irq clock i/o enable data out clock out smb controller 128 amd geode? cs5535 companion device data book system management bus controller 31506b table 5-18. comparison of smb, i 2 c, and access.bus symbol parameter smb i 2 c access.bus min max min max min max f operating frequency 10 khz 100 khz 0 khz 100 khz 10 khz 100 khz t buf bus free time between stop and start condition 4.7 s 4.7 s 4.7 s t hd :sta hold time after (repeated) start condition. after this period the first clock is generated 4.0 s 4.0 s 4.0 s t su :sta repeated start condition setup time 4.7 s 4.7 s 4.7 s t su :sto stop condition setup time 4.0 s 4.0 s 4.0 s t hd :dat data hold time 300 ns 0 s 3.45 s 300 ns t su :dat data setup time 250 ns 250 ns 250 ns t timeout detect clock low time-out 25 ms 35 ms 25 ms 35 ms t low clock low period 4.7 s 4.7 s 4.7 s t high clock high period 4.0 s 50 s 4.0 s 4.0 s 50 s t low :sext cumulative clock low extend period (slave) 25 ms 25 ms t low :mext cumulative clock low extend period (master) 10 ms 10 ms t f clock/data fall time 300 ns 300 ns 300 ns t r clock/data rise time 1000 ns 1000 ns 1000 ns tpor time that device must be opera- tional after power-on reset 500 ms v il smbus signal input low voltage 0.8v -0.5v 1.5v -0.5v 0.6v v ih smbus signal input high voltage 2.1v vdd 3.0v 1.4v 5.5v v ol smbus signal output lo w voltage 0.4v 0v 0.4v 0v 0.4v i leak_bus input leakage per bus segment -200 a 200 a i leak_pin input leakage per device pin -10 a 10 a -10 a 10 a 10 a v dd nominal bus voltag e 2.7v 5.5v 2.0v 5.0v i pullup current sinking, v ol = 0.4v (smbus) 4.0 ma 100 a 350 a c bus capacitive load per bus segment 400 pf c i capacitance for smbdat or smbclk pin 10 pf 10 pf v noise signal noise immunity from 10 to 100 mhz 300 mv p-p amd geode? cs5535 companion device data book 129 system management bus controller 31506b 5.11.1 data transactions one data bit is transferred during each clock pulse. data is sampled during the high state of the serial clock (scl). consequently, throughout the clock?s high period, the data should remain stable (see figure 5-24). any changes on the sda line during the high state of scl and in the middle of a transaction aborts the current transaction. new data should be sent during the low scl state. this protocol per- mits a single data line to transfer both command/control information and data, using the synchronous serial clock. each data transaction is composed of a start condition, a number of byte transfers (set by the software), and a stop condition to terminate the transaction. each byte is transferred with the most signifi cant bit first, and after each byte (8 bits), an acknowledge signal must follow. the fol- lowing subsections provide further details of this process. during each clock cycle, the slave can stall the master while it handles the previous data or prepares new data. this can be done for each bit transferred, or on a byte boundary, by the slave holding scl low to extend the clock-low period. typically, slaves extend the first clock cycle of a transfer if a byte read has not yet been stored, or if the next byte to be transmitted is not yet ready. some microcontrollers, with limited hardware support for smb, extend the smb after each bi t, thus allowing the software to handle this bit. figure 5-24. smb bit transfer 5.11.1.1 start and stop conditions the smb master generates start and stop conditions (control codes). after a start condition is generated, the bus is considered busy and reta ins this status for a certain time after a stop condition is generated. a high-to-low transition of the data line (sda) while the clock (scl) is high indicates a start condition. a low-to-high transition of the sda line while the scl is high indicates a stop condition (see figure 5-25). in addition to the first start condition, a repeated start condition can be generated in the middle of a transaction. this allows another device to arbitrate the bus , or a change in the direction of data transfer. figure 5-25. smb start and stop conditions sda scl data line stable: data valid change of data allowed sda scl s p start condition stop condition 130 amd geode? cs5535 companion device data book system management bus controller 31506b 5.11.1.2 acknowledge (ack) cycle the ack cycle consists of two signals: the ack clock pulse sent by the master with each byte transferred, and the ack signal sent by the receiving device (see figure 5- 26). the master generates the ack clock pulse on the ninth clock pulse of the byte transfer. the transmitter releases the sda line (permits it to go high) to allow the receiver to send the ack signal. the receiver must pull down the sda line during the ack clock pulse, signalling that it has cor- rectly received the last data byte and is ready to receive the next byte. figure 5-27 on page 130 illustrates the ack cycle. figure 5-26. smb data transaction figure 5-27. smb acknowledge cycle s p start condition stop condition sda scl msb ack ack 12 3 - 6 7 8 9 1 23 - 8 9 acknowledge signal from receiver byte complete interrupt within receiver clock line held low by receiver while interrupt is serviced s start condition scl 12 3 - 6 7 8 9 transmitter stays off bus during acknowledge clock acknowledge signal from receiver data output by transmitter data output by receiver amd geode? cs5535 companion device data book 131 system management bus controller 31506b 5.11.1.3 acknowledge after every byte rule according to this rule, the master generates an acknowl- edge clock pulse after each byte transfer, and the receiver sends an acknowledge signal after every byte received. there are two exceptions to this rule: when the master is the receiver, it must indicate to the transmitter the end of data by not acknowledging (nega- tive acknowledge) the last byte clocked out of the slave. this negative acknowledge still includes the acknowl- edge clock pulse (generated by the master), but the sda line is not pulled down. when the receiver is full, otherwise occupied, or a problem has occurred, it sends a negative acknowledge to indicate that it cannot accept additional data bytes. 5.11.1.4 addressing transfer formats each device on the bus has a unique address. before any data is transmitted, the master transmits the address of the slave being addressed. the slave device should send an acknowledge signal on the sda line, once it recognizes its address. the address consists of the first seven bits after a start condition. the direction of the data transfer (r/w ) depends on the bit sent after the address, the eighth bit. a low-to- high transition during an scl high period indicates the stop condition, and ends the transaction of sda (see fig- ure 5-28). when the address is sent, each device in the system com- pares this address with its own. if there is a match, the device considers itself addressed and sends an acknowl- edge signal. depending on the state of the r/w bit (1 = read, 0 = write), the device acts either as a transmitter or a receiver. the smb protocol allows a general call address to be sent to all slaves connected to the bus. the first byte sent spec- ifies the general call address (00h) and the second byte specifies the meaning of the general call (for example, write slave address by software only). those slaves that require data acknowledge the call, and become slave receivers; other slaves ignore the call. figure 5-28. smb complete data transaction s p start condition stop condition sda scl 1 - 7 8 9 1 - 7 8 9 1 - 7 8 9 address r/w ack data ack data ack 132 amd geode? cs5535 companion device data book system management bus controller 31506b 5.11.1.5 arbitration on the bus multiple master devices on the bus require arbitration between their conflicting bus smb demands. control of the bus is initially determined according to address bits and clock cycle. if the masters are trying to address the same slave, data comparisons determine the outcome of this arbitration. in master mode, the device immediately aborts a transaction if the value sampled on the sda line differs from the value driven by the device. (an exception to this rule is sda while receiving data. the lines may be driven low by the slave without causing an abort.) the scl signal is monitored for clock synchronization and to allow the slave to stall the bus. the actual clock period is set by the master with the longest clock period, or by the slave stall period. the clock high period is determined by the master with the shortest clock high period. when an abort occurs during the address transmission, a master that identifie s the conflict should give up the bus, switch to slave mode, and continue to sample sda to check if it is being addressed by the winning master on the bus. 5.11.1.6 master mode this discussion and section 5.11.1.7 "slave mode" refer- ence several bits in the smb native register set (e.g., smbctl1.stastre, smbst.master, etc.). table 5-19 provides the bit map for the smb native registers for the reader?s convenience. for full bit descriptions, refer to sec- tion 6.11.1 "smb native registers" on page 371. requesting bus mastership an smb transaction starts with a master device requesting bus mastership. it asserts a start condition, followed by the address of the device that wants the bus. if this trans- action is successfully complete d, the software may assume that the device has be come the bus master. for the device to become the bus master, the software should perform the following steps: 1) configure smbctl1.inten to the desired operation mode (polling = 0 or interrupt = 1) and set smbctl1.start. this caus es the smb controller to issue a start condition on the bus when the bus becomes free (smbcst.bb is cleared, or other condi- tions that can delay start). it then stalls the bus by holding scl low. 2) if a bus conflict is detected (i.e., another device pulls down the scl signal), smbst.ber is set. 3) if there is no bus conflict, smbst.sdast and smbst.master are set. 4) if smbctl1.inten is set and either smbst.ber or smbst.sdast is set, an interrupt is issued. sending the address byte when the device is the active master of the bus (smbst.master is set), it can send the address on the bus. the address sent should not be the device?s own address, as defined by the addr bits of the smbaddr register if the smbaddr.saen is set, nor s hould it be the global call address if the smbcst.gcmtch is set. to send the address byte, use the following sequence: 1) for a receive transaction, where the software wants only one byte of data, it should set smbctl1.ack. if only an address needs to be sent or if the device requires stall for some other reason, set the smbctl1.stastre. 2) write the address byte (7-bit target device address) and the direction bit to smbsda. this causes the smb controller to generate a transaction. at the end of this transaction, the acknowledge bit received is copied to smbst.negack. during the transaction, the sda and scl lines are continuously checked for conflict with other devices. if a conflict is detected, the transaction is aborted, smbst.ber is set, and smbst.master is cleared. table 5-19. smb native registers map smb i/o offsetname 76543210 00h smbsda smbsda 01h smbst slvstp sdast ber negack stastr nmatch master xmit 02h smbcst rsvd tgscl tsda gcmtch match bb busy 03h smbctl1 stastre nminte gcmen ack rsvd inten stop start 04h smbaddr saen smbaddr 05h smbctl2 sclfrq en 06h smbctl3 sclfrq en amd geode? cs5535 companion device data book 133 system management bus controller 31506b 3) if smbctl1.stastre is set and the transaction was successfully completed (i .e., both smbst.ber and smbst.negack are cleared), the stastr bit is set. in this case, the smb controller stalls any further bus operations (i.e., holds scl low). if smbctl1.inten is set, it also sends an interrupt request to the host. 4) if the requested direction is transmit and the start transaction was completed su ccessfully (i.e., neither smbst.negack nor smbst.ber is set, and no other master has arbitrated the bus), smbst.sdast is set to indicate that the smb controller awaits atten- tion. 5) if the requested direction is receive, the start trans- action was completed successfully and smbctl1.stastre is clea red, the smb controller starts receiving the first byte automatically. 6) check that both smbst.ber and smbst.negack are cleared. if smbctl1.inten is set, an interrupt is generated when either smbst.ber or smbst.negack is set. master transmit after becoming the bus master, the device can start trans- mitting data on the bus. to transmit a byte in an interrupt or polling controlled oper- ation, the software should: 1) check that both smbst.ber and smbst.negack are cleared, and that smbst.sdast is set. if smbctl1.stastre is set, also check that the smbst.stastr is cleared (and clear it if required). 2) write the data byte to be transmitted to smbsda. when either smbst.negack or smbst.ber is set, an interrupt is generated. when the slave responds with a negative acknowledge, smbst.negack is set and smbst.sdast remains clea red. in this case, if smbctl1.inten is set, an interrupt is issued. master receive after becoming the bus master, the device can start receiv- ing data on the bus. to receive a byte in an interrupt or polling operation, the software should: 1) check that smbst.sdast is set and that smbst.ber is cleared. if smbctl1.stastre is set, also check that smbst.stastr is cleared (and clear it if required). 2) set smbctl1.ack, if the next byte is the last byte that should be read. this causes a negative acknowl- edge to be sent. 3) read the data byte from smbsda. before receiving the last by te of data, set smbctl1.ack. before generating a stop condition or generating a repeated start condition, it is necessary to perform an sda read and clear the smbst.sdast bit. master stop to end a transaction, set smbctl1.stop before clearing the current stall flag (i.e., the sdast, negack, or stastr bit of smbst). this causes the smb to send a stop condition immediately, and to clear smbctl1.stop. a stop condition may be issued only when the device is the active bus master (smbst.mas- ter is set). master bus stall the smb controller can stall the bus between transfers while waiting for the host resp onse. the bus is stalled by holding the scl signal low after the acknowledge cycle. note that this is interpreted as the beginning of the follow- ing bus operation. the user must make sure that the next operation is prepared before th e flag that causes the bus stall is cleared. the flags that can cause a bus stall in master mode are: negative acknowledge after sending a byte (smbst.negack = 1). smbst.sdast bit is set. smbctl1.stastre = 1, af ter a successful start (smbst.stastr = 1). repeated start a repeated start is performed when the device is already the bus master (smbst.master is set). in this case, the bus is stalled and the smb controller awaits host handling due to: negative acknowledge (smbst.negack = 1), empty buffer (smbst.sdast = 1), and/or a stall after start (smbst.stastr = 1). for a repeated start: 1) set (1) smbctl1.start. 2) in master receive mode, read the last data item from smbsda. 3) follow the address send sequence, as described in ?write the address byte (7-bit target device address) and the direction bit to smbsda. this causes the smb controller to generate a transaction. at the end of this transaction, the acknowledge bit received is copied to smbst.negack. during the transaction, the sda and scl lines are continuously checked for conflict with other devices. if a conflict is detected, the transaction is aborted, smbst.ber is set, and smbst.master is cleared. 4) if the smb controller was awaiting handling due to smbst.stastr = 1, clear it only after writing the requested address and direction to smbsda. 134 amd geode? cs5535 companion device data book system management bus controller 31506b master error detection the smb controller detects illegal start or stop condi- tions (i.e., a start or stop condition within the data transfer, or the acknowledge cycle) and a conflict on the data lines of the bus. if an illegal condition is detected, smbst.ber is set and master mode is exited (smbst.master is cleared). bus idle error recovery when a request to become the active bus master or a restart operation fails, smbst.ber is set to indicate the error. in some cases, both the device and the other device may identify the failure and leave the bus idle. in this case, the start sequence may be incomplete and the bus may remain deadlocked. to recover from deadlock, use the following sequence: 1) clear smbst.ber and smbcst.bb. 2) wait for a time-out period to check that there is no other active master on the bus (i.e., smbcst.bb remains cleared). 3) disable, and re-enable the smb controller to put it in the non-addressed slave mode. this completely resets the functional block. at this point, some of the slaves may not identify the bus error. to recover, the smb controller becomes the bus master: it asserts a start condition, sends an address byte, then asserts a stop condi tion that syn chronizes all the slaves. 5.11.1.7 slave mode a slave device waits in idle mo de for a master to initiate a bus transaction. whenever the smb controller is enabled and it is not acting as a master (i.e., smbst.master is cleared), it acts as a slave device. once a start condition on the bus is detected, the device checks whether the address sent by the current master matches either: the smbaddr.addr value if smbaddr.saen = 1, or the general call address if smbctl1.gcmen = 1. this match is checked even when smbst.master is set. if a bus conflict (on sda or scl) is detected, smbst.ber is set, smbst.master is cleared and the device contin- ues to search the received message for a match. if an address match or a global match is detected: 1) the device asserts its sda line during the acknowl- edge cycle. 2) smbcst.match and smbst .nmatch are set. if smbst.xmit = 1 (i.e., slave transmit mode) smbst.sdast is set to indicate that the buffer is empty. 3) if smbctl1.inten is set, an interrupt is generated if both smbctl1.inten and smbctl1.nminte are set. 4) the software then reads smbst.xmit to identify the direction requested by the master device. it clears smbst.nmatch so future byte transfers are identi- fied as data bytes. slave receive and transmit slave receive and transmit are performed after a match is detected and the data transfer direction is identified. after a byte transfer, the smb controller extends the acknowledge clock until the software reads or writes the smbsda regis- ter. the receive and transmit sequences are identical to those used in the master routine. slave bus stall when operating as a slave, the device stalls the bus by extending the first clock cycle of a transaction in the follow- ing cases: smbst.sdast is set. smbst.nmatch and smbctl1.nminte are set. slave error detection the smb controller detects an illegal start and stop conditions on the bus (i.e., a start or stop condition within the data transfer or the acknowledge cycle). when this occurs, smbst.ber is set and smbcst.match and smbcst.gmatch are cleared, setting the smb control- ler as an unaddressed slave. 5.11.1.8 configuration sda and scl signals the sda and scl are open-drain signals. the device per- mits the user to define whether to enable or disable the internal pull-up of each of these signals. smb clock frequency the smb permits the user to set the clock frequency for the system management bus cloc k. the clock is set by the smbctl2.sclfrq field and the smbctl3 register, which determines the scl clock period used by the device. this clock low period may be extended by stall periods ini- tiated by the smb or by anot her system management bus device. in case of a conflict with another bus master, a shorter clock high period may be forced by the other bus master until the conflict is resolved. amd geode? cs5535 companion device data book 135 system management bus controller 31506b 5.11.1.9 transaction types byte write sequence of events (see figure 5-29): 1) start 2) address phase 3) acknowledge 4) word address 5) acknowledge 6) data 7) acknowledge 8) stop page write sequence of events (see figure 5-30): 1) start 2) address 3) acknowledge 4) word address 5) acknowledge 6) data1 7) acknowledge 8) data(n) 9) acknowledge 10) data(n+1) 11) acknowledge 12) data(n+x) 13) acknowledge 14) stop current address read sequence of events (see figure 5-31): 1) start 2) device address - 8 bit 3) acknowledge 4) data 5) no acknowledge 6) stop figure 5-29. smb byte write figure 5-30. smb page write figure 5-31. smb current address read start msb lsb write r/w ack device word address msb lsb ack data stop address sda ack line start msb lsb write r/w ack device word address (n) msb lsb ack data (n) stop address sda ack line data (n + 1) data (n + x) ack ack start msb lsb read r/w ack device data no ack stop address sda line 136 amd geode? cs5535 companion device data book system management bus controller 31506b random read sequence of events (see figure 5-32): 1) start 2) device address 3) acknowledge 4) word address(n) 5) acknowledge 6) start 7) device address 8) acknowledge 9) data(n) 10) no acknowledge 11) stop sequential reads sequence of events (see figure 5-33): 1) start 2) device address 3) acknowledge 4) data(n) 5) acknowledge 6) data(n+1) 7) acknowledge 8) data(n+2) 9) acknowledge 10) data(n+x) 11) no acknowledge 12) stop figure 5-32. smb random read figure 5-33. smb sequential reads start msb lsb write r/w ack device word address (n) ack start address sda line msb lsb msb lsb read device address ack data (n) no ack stop dummy write start msb lsb read r/w ack device data (n) ack address sda line ack data (n + x) no ack stop data (n+1) data (n+2) ack amd geode? cs5535 companion device data book 137 uart and ir port 31506b 5.12 uart and ir port the uart and ir port (uart/ir controller) is an enhanced serial port with fast ir (infrared). the uart/ir controller provides advanced, versatile serial communica- tions features with ir capabilities and supports: uart (section 5.12.1.1 "uart mode" on page 140) sharp-ir (section 5.12.1.2 "sharp-ir mode" on page 140) irda 1.0 sir (section 5.12.1.3 "sir mode" on page 140) consumer electronic ir (ceir); also called tv remote or consumer remote control (section 5.12.1.4 "ceir mode" on page 141) in uart mode, the functional block can act as a standard 16450 or 16550, or in extended mode. existing 16550-based legacy software is completely and transparently supported. organization and specific fall- back mechanisms switch the functional block to 16550 compatibility mode upon reset, or when initialized by 16550 software. this functional block has tw o dma channels, of which the device can use one or both. one channel is required for ir- based applications, since ir communication works in half- duplex fashion. two channels are normally needed to han- dle high-speed, full duplex, uart-based applications. figure 5-34 shows the serial port connections to the peripheral devices and host, as well as the device configu- ration. features fully compatible with 16550 and 16450 devices (except modem) extended uart mode sharp-ir irda 1.0 sir with up to 115.2 kbaud data rate consumer-ir mode uart mode data rates up to 1.5 mbps full duplex infrared frame transmission and reception transmit deferral automatic fallback to 16550 compatibility mode selectable 16 and 32 level fifos 12-bit timer for infrared protocol support dma handshake signal routing for either 1 or 2 channels support for power management virtual dongle interface figure 5-34. uart/ir overview diagram microprocessor master bus local bus interface dma controller virtual dongle interface superi/o bus and register bank tx and rx uart/ir logic uart interface ir interface msr_don msr_config msr_rsvd msr_mod local bus to superi/o bus converter and control logic id[3:0] irsl0_ds irsl[2:0] modem/control signals uart/ir controller sout sin irtx irrx1 irq interrupt controller busy ccu mhz48_clk dma interface 138 amd geode? cs5535 companion device data book uart and ir port 31506b 5.12.1 operational modes this section describes the operation modes of the uart/ir controller. although each mode is unique, certain system resources and features are common. this discussion references several bits in the uart/ir controller native register set. table 5-20 provides the bit map for the uart/ir controller native registers for the reader?s convenience. for full bit descriptions, refer to sec- tion 6.12.2 on page 383. table 5-20. uart/ir controller native register bit map i/o offsetname76543210 bank 0 00h rxd rxd7 rxd6 rxd5 rxd4 rxd3 rxd2 rxd1 rxd0 00h txd txd7 txd6 txd5 txd4 txd3 txd2 txd1 txd0 01h ier ( note 1 ) rsvd ms_ie ls_ie txldl_ie rxhdl_ie ier ( note 2 ) rsvd txemp_ie dma_ie ms_ie ls_ie txldl_ie rxhdl_ie 02h eir (note 1) fen[1:0] rsvd rxft ipr[1:0] ipf eir (note 2) rsvd txemp_ev dma_ev ms_ev ls_ev/ txhlt_ev txldl_ev rxhdl_ie fcr rxfth[1:0] txfth[1:0] rsvd txsr rxsr fifo_en 03h lcr bkse sbrk stkp eps pen stb wls[1:0] bsr bkse bsr[6:0] 04h mcr (note 1) rsvd loop isen or dcdlp rilp rts dtr mcr (note 2) mdsl[2:0] ir_pls tx_dfr dma_en rts dtr 05h lsr er_inf txemp txrdy brk fe pe oe rxda 06h msr dcd ri dsr cts ddcd teri ddsr dcts 07h spr (note 1) scratch data ascr (note 2) cte txur rxact rxwdg rsvd s_oet rsvd rxf_tout bank 1 00h lbgd_l lbgd[7:0] 01h lbgd_h lbgd[15:8] 02h rsvd rsvd 03h lcr bkse sbrk stkp eps pen stb wls1 wls0 bsr bkse bsr[6:0] 04-07h rsvd rsvd bank 2 00h bgd_l bgd[7:0] 01h bgd_h bgd[15:8] 02h excr1 rsvd edtlbk loop dmaswp dmath dmanf ext_sl 03h bsr bkse bsr[6:0] 04h excr2 lock rsvd presl[1:0] rf_siz[1:0] tf_siz1[1:0] 05h rsvd rsvd 06h txflv rsvd tfl[5:0] 07h rxflv rsvd rfl[5:0] amd geode? cs5535 companion device data book 139 uart and ir port 31506b bank 3 00h mrid mid[3:0] rid[3:0] 01h sh_lcr rsvd sbrk stkp eps pen stb wls1 wls0 02h sh_fcr rxfth[1:0] txfth[1:0] rsvd txsr rxsr fifo_en 03h bsr bkse bsr[6:0] 04h- 07h rsvd rsvd bank 4 00h- 01h rsvd rsvd 02h ircr1 rsvd ir_sl[1:0] rsvd 03h bsr bkse bsr[6:0] 04h- 07h rsvd rsvd bank 5 00h- 02h rsvd rsvd 03h bsr bkse bsr[6:0] 04h ircr2 rsvd rsvd rsvd aux_irrx rsvd rsvd irmssl ir_fdplx 05h- 07h rsvd rsvd bank 6 00h ircr3 shdm_ds shmd_ds rsvd 01h rsvd rsvd 02h sir_pw rsvd spw3 spw2 spw1 spw0 03h bsr bkse bsr[6:0] 04h- 07h rsvd rsvd bank 7 00h irrxdc dbw[2:0] dfr[4:0] 01h irtxmc mcpw[2:0] mcfr[4:0] 02h rccfg r_len t_ov rxhsc rcdm_ds rsvd txhsc rc_mmd[1:0] 03h bsr bkse bsr[6:0] 04h ircfg1 strv_ms rsvd set_irtx irrx1_lv rsvd iric[2:0] 05h- 06h rsvd rsvd 07h ircfg4 rsvd irsl0_ds rxinv irsl21_ds rsvd note 1. non-extended mode. note 2. extended mode. table 5-20. uart/ir controller native register bit map (continued) i/o offsetname76543210 140 amd geode? cs5535 companion device data book uart and ir port 31506b 5.12.1.1 uart mode uart mode supports serial data communication with a remote peripheral device using a wired interface. this func- tional block provides receive and transmit channels that can operate concurrently in full-duplex mode. this func- tional block performs all functions required to conduct par- allel data interchange with the system and composite serial data exchange with the external data channel. it performs parallel-to-serial conversion on data characters received from the processor or a dma controller, and serial-to-parallel conversion on data characters received from the serial interface. figure 5-35 shows the serial data stream. a data character contains five to eight data bits. it is preceded by a start bit and is followed by an optional parity bit and a stop bit. data is transferred in little endian order (lsb first). uart mode can be implemented in standard 16450 and 16550 compatibility (non-extended) and extended mode. uart 16450 compatibility mode is the default after power- up or reset. when extended mode is selected, the func- tional block architecture changes slightly and a variety of additional features are made available. the interrupt sources are no longer prioriti zed, and an auxiliary status and control register (ascr) replaces the scratch pad register (spr). the additional features include: transmitter fifo (tx_fifo) thresholding, dma capability, and inter- rupts on transmitter empty states and dma events. the clock for both transmit and receive channels is pro- vided by an internal baud generator that divides its input clock by any divisor value from 1 to 2 16 -1. the output clock frequency of the baud generator must be programmed to be 16 times the baud rate value. the baud generator input clock is derived from a 24 mhz clock through a program- mable prescaler. the prescaler value is determined by the presl bits in the excr2 register. its default value is 13. this allows all the standard baud rates, up to 115.2 kbaud, to be obtained. smaller prescaler values allow baud rates up to 921.6 kbaud (standard) and 1.5 kbaud (non-stan- dard). before operation can begin, both the communication for- mat and baud rate must be programmed by the software. the communication format is programmed by loading a control byte into the lcr (link control register), while the baud rate is selected by loading an appropriate value into the baud generator divisor register. the software can read the status of the functi onal block at any time during operation. the status information includes full/empty states for both transmit and receive channels, and any other condition detec ted on the received data stream, such as a parity error, framing error, data overrun, or break event. 5.12.1.2 sharp-ir mode this mode supports bidirectional data communication with a remote device, using ir radiation as the transmission medium. sharp-ir uses digital amplitude shift keying (dask) and allows serial co mmunication at baud rates up to 38.4 kbaud. the format of the serial data is similar to that of the uart data format. each data word is sent seri- ally, beginning with a 0 value start bit, followed by up to eight data bits (lsb first), an optional parity bit, and ending with at least one stop bit, with a binary value of 1. a logi- cal 0 is signalled by sending a 500 khz continuous pulse train of ir radiation. a logical 1 is signalled by the absence of an ir signal. this functional block can perform the mod- ulation and demodulation operations internally, or can rely on the external optical module to perform them. sharp-ir device operation is similar to operation in uart mode. the difference being that data transfer operations are normally performed in half-duplex fashion, and the modem control and status signals are not used. selection of the sharp-ir mode is controlled by the mode select (mdsl) bits in the mcr when the functional block is in extended mode, or by the ir_s l bits in the ircr1 register when the functional block is in non-extended mode.) this prevents legacy software, running in non-extended mode, from spuriously switching the functional block to uart mode when the software writes to the mcr. 5.12.1.3 sir mode sir mode supports bidirectional data communication with a remote device, using ir radiation as the transmit medium. sir allows serial communication at baud rates up to 115.2 kbaud. the serial data format is similar to that of the uart data format. each data word is sent serially, beginning with a 0 value start bit, followed by eight data bits (lsb first), an optional parity bit, and ending with at least one stop bit, with a binary value of 1. a 0 value is signalled by sending a single ir pulse. a 1 value is sig- nalled by the absence of a pulse. the width of each pulse can be either 1.6 s (3/16 the time required to transmit a single bit at 115.2 kbps). this way, each word begins with a pulse at the start bit. operation in sir is similar to that of the uart mode. the difference being that data transfer operations are normally performed in half-duplex fashion. selection of the irda 1.0 sir mode is controlled by the mdsl bits in the mcr when the uart is in extended mode, or by the ir_sl bits in the ircr1 register when the uart is in non-extended mode. this prevents legacy software, running in non-extended mode, from spuriously switching the functional block to uart mode when the software writes to the mcr. figure 5-35. uart serial data stream format start -lsb- data[5:8] -msb- parity stop amd geode? cs5535 companion device data book 141 uart and ir port 31506b 5.12.1.4 ceir mode the consumer electronics ir circuitry is designed to opti- mally support all major protocols presently used in the fol- lowing remote-controlled home entertainment equipment: rc-5, rc-6, recs 80, nec, and rca. this module, in conjunction with an external optical device, provides the physical layer functions necessary to support these proto- cols. such functions include: modulation, demodulation, serialization, de-serialization, data buffering, status report- ing, interrupt generation, etc. the software is responsible for the generation of ir code transmitted, and the interpre- tation of received code. ceir transmit operation the transmitted code consists of a sequence of bytes that represents either a bit string or a set of run-length codes. the number of bits or run-length codes needed to repre- sent each ir code bit depends on the ir protocol used. the rc-5 protocol, for example, needs two bits or between one and two run-length codes to represent each ir code bit. transmission is initiated when the processor or dma con- troller writes code bytes into the empty tx_fifo. trans- mission is completed when the processor sets the s_eot bit of the ascr, before writing the last byte, or when the dma controller activates the terminal count (tc). trans- mission also terminates if the processor simply stops trans- ferring data and the transmitter becomes empty. in this case, however, a transmitter-underrun condition is gener- ated that must be cleared in order to begin the next trans- mission. the transmission bytes are either de-serialized or run- length encoded, and the resulting bit-string modulates a carrier signal that is sent to the transmitter led. the trans- fer rate of this bit-string, like in uart mode, is determined by the value programmed in the baud generator divisor register. unlike a uart transmission, start, stop, and parity bits are not included in the transmitted data stream. a logic 1 in the bit-string keeps the led off, so no ir signal is transmitted. a logic 0 generates a sequence of modulating pulses that turn on the transmitter led. fre- quency and pulse width of the modulating pulses are pro- grammed by the mcfr and mcpw fields in the irtxmc register, as well as the txhs c bit of the rccfg register. the rc_mmd field of rccfg selects the transmitter mod- ulation mode. if the c_pls mode is selected, modulating pulses are generated continuously for the entire logic 0 bit time. if 6_pls or 8_pls mode is selected, six or eight pulses are generated each time a logic 0 bit is transmitted following a logic 1 bit. c_pls modulation mode is used for rc-5, rc-6, nec, and rca protocols. 8_pls or 6_pls modulation mode is used for the recs 80 protocol. the 8_pls or 6_pls mode allows minimization of the number of bits needed to represent the recs 80 ir code sequence. the current transmitter implementation s upports only the modulated modes of the recs 80 protocol; it does not support the flash mode. note: the total transmission time for the logic 0 bits must be equal to or greater than six or eight times the period of the modulation subcarrier, otherwise fewer pulses will be transmitted. ceir receive operation the ceir receiver is significantly different from a uart receiver. the incoming ir signals are dask modulated; therefore, demodulation may be necessary. also, there are no start bits in the incoming data stream. the operations performed by the receiver, whenever an ir signal is detected, are slightly different, depending on whether or not receiver demodulation is enabled. if demod- ulation is disabled, the receiver immediately becomes active. if demodulation is enabled, the receiver checks the carrier frequency of the incoming signal and becomes active only if the frequen cy is within the programmed range. otherwise, the signal is ignored and no other action is taken. when the receiver enters the active state, the rxact bit of the ascr is set to 1. once in the active state, the receiver keeps sampling the ir input signal and generates a bit-string, where a logic 1 indicates an idle condition and a logic 0 indicates the presence of ir energy. the ir input is sampled regardless of the presence of ir pulses at a rate determined by the value loaded into the baud genera- tor divisor registers. the received bit-string is either de- serialized and assembled into 8-bit characters, or is con- verted to run-length encoded values. the resulting data bytes are then transferred into the receiver fifo (rx_fifo). the receiver also sets the rxwdg bit of the ascr each time an ir pulse signal is detected. this bit is automatically cleared when the ascr is read. it is intended to assist the software in determining when the ir link has been idle for a period of time. the software can then stop data from being received by writing a 1 into the rxact bit to clear it, and return the receiver to the inactive state. the frequency bandwidth for the incoming modulated ir signal is selected by the dfr and dbw fields in the irrxdc register. there are tw o ceir receive data modes: oversampled and programmed t period. for either mode, the sampling rate is determined by the setting of the baud generator divisor registers. 142 amd geode? cs5535 companion device data book uart and ir port 31506b oversampled mode can be used with the receiver demodu- lator either enabled or disabled. it should be used with the demodulator disabled when a detailed snapshot of the incoming signal is needed; for example, to determine the period of the carrier signal. if the demodulator is enabled, the stream of samples can be used to reconstruct the incoming bit-string. to obtain good resolution, a fairly high sampling rate should be selected. programmed t period mode should be used with the receiver demodulator enabled. the t period represents one-half bit time for protocols using biphase encoding or the basic unit of pulse dist ance for protocols using pulse distance encoding. the baud is usually programmed to match the t period. for long periods of logic low or high, the receiver samples the demodulated signal at the pro- grammed sampling rate. when a new ir energy pulse is detected, the receiver syn- chronizes the sampling process to the incoming signal tim- ing. this reduces timing-related errors and eliminates the possibility of missing short ir pulse sequences, especially with the recs 80 protocol. in addition, the programmed t period sampling minimizes the amount of data used to rep- resent the incoming ir signal, therefore reducing the pro- cessing overhead in the host cpu. 5.12.1.5 fifo timeouts timeout mechanisms are prov ided to prevent received data from remaining in the rx_fifo indefinitely, in case the programmed interrupt or dma thresholds are not reached. an rx_fifo timeout generates a receiver data ready interrupt and/or a receiver dma request if bit 0 of the ier register and/or bit 2 of th e mcr register (in extended mode) are set to 1, respectively. an rx_fifo timeout also sets bit 0 of the ascr register to 1 if the rx_fifo is below the threshold. when a receiver data ready interrupt occurs, this bit is tested by the software to determine whether a number of bytes indicated by the rx_fifo threshold can be read without checking bit 0 of the lsr register. the conditions that must exist for a timeout to occur in the modes of operation are described below. when a timeout has occurred, it can only be re set when the fifo is read by the processor or dma controller. timeout conditions for uart, sir, and sharp-ir modes rx_fifo timeout conditions: at least one byte is in the rx_fifo. more than four character times have elapsed since the last byte was loaded into the rx_fifo from the receiver logic. more than four character times have elapsed since the last byte was read from the rx_fifo by the processor or dma controller. timeout conditions for ceir mode the rx_fifo timeout in ceir mode is disabled while the receiver is active. the conditio ns for this timeout to occur are as follows: at least one byte has been in the rx_fifo for 64 s or more. the receiver has been inactive (rxact = 0) for 64 s or more. more than 64 s have elapsed since the last byte was read from the rx_fifo by the processor or dma controller. 5.12.1.6 transmit deferral this feature allows software to send short, high-speed data frames in pio mode without the risk of generating a trans- mitter underrun. transmit deferral is available only in extended mode and when the tx_fifo is enabled. when transmit deferral is enabled (tx_dfr bit of the mcr register set to 1) and the transmitter becomes empty, an internal flag is set and locks the transmitter. if the processor now writes data into the tx_fifo, the transmitter does not start sending the data until the tx_fifo level reaches either 14 for a 16- level tx_fifo or 30 for a 32-level tx_fifo, at which time the internal flag is cleared. the internal flag is also cleared and the transmitter starts transmitting when a timeout con- dition is reached. this prevents some bytes from being in the tx_fifo indefinitely if the threshold is not reached. the timeout mechanism is implemented by a timer that is enabled when the internal flag is set and there is at least one byte in the tx_fifo. whenever a byte is loaded into the tx_fifo, the timer is reloa ded with the initial value. if no byte is loaded for a 64 s time, the timer times out and the internal flag is cleared, thus enabling the transmitter. amd geode? cs5535 companion device data book 143 uart and ir port 31506b 5.12.1.7 automatic fallback to 16550 compatibility mode this feature is designed to support existing legacy software packages, using the 16550 serial port. for proper opera- tion, many of these software packages require that the module look identical to a plain 16550, since they access the serial port registers directly. because several extended features and new operational modes are provided, make sure the module is in the proper state before executing a legacy program. the fallback mechanism eliminates the need to change the state when a legacy program is executed following comple- tion of a program that used extended features. it automati- cally switches the module to 16550 compatibility mode and turns off any extended features whenever the baud gener- ator divisor register is ac cessed through the lbgd_l or lbgd_h ports in register bank 1. in order to avoid spurious fallbacks, baud generator divisor ports are provided in bank 2. baud generator divisor access through these ports changes the baud rate setting but does not cause fallback. new programs designed to take advantage of the extended features should not use lbgd_l and lbgd_h to change the baud rate. instead, they should use bgd_l and bgd_h. a fallback can occur in either extended or non-extended modes. if extended mode is selected, fallback is always enabled. in this case, when a fallback occurs, the following happens: tx_fifo and rx_fifo switch to 16 levels. a value of 13 is selected for the baud generator pre- scaler. etdlbk and btest of the excr1 register are cleared. uart mode is selected. the functional block switches to non-extended mode. when fallback occurs from non-extended mode, only the first three of the above actions occur. if either sharp-ir or sir infrared modes were selected, no switching to uart mode occurs. this prevents spurious switching to uart mode when a legacy program, running in infrared mode, accesses the baud generator divisor register from bank 1. fallback from non-extended mode can be disabled by set- ting lock in the excr2 register to 1. when lock is set and the functional block is in non-extended mode, two scratch pad registers overlaid with lbgd_l and lbgd_h are enabled. any attempted processor access of the baud generator divisor register through lbgd_l and lbgd_h accesses the scratch pad regist ers, without affecting the baud rate setting. this feature allows existing legacy pro- grams to run faster than 1 15.2 kbaud, without realizing they are running at this speed. 5.12.2 modem support an msr (msr_uart[x]_mod) (uart1 msr 51400038h and uart2 msr 5140003ch) mimics modem input sig- nals for making it compatible with the software having modem support. the hardware of this module has all the required functionality fo r modem compatibility. 144 amd geode? cs5535 companion device data book uart and ir port 31506b 5.12.3 dongle interface the dongle interface on the geode cs5535 companion device is not a fully hardware compatible interface. the real dongle interface requires six external interface signals and the geode cs5535 companion device only supports three. with only three signals, the dongle interface sup- ports a subset of the real dongle interface through virtual- ization. 5.12.3.1 real dongle the real dongle interface uses six multiplexed pins for don- gle identification, data transfe r, and transceiver configura- tion. figure 5-36 on page 144 illustrates the real dongle interface and table 5-21 provides the interface signals and their descriptions. only three signals (irtx, irrx, and id0/irsl0/irrx2) are used for the ir interface. it has three phases: phase 1: change the id0-id3 bits to input mode, and read the status to complete primary identification of the dongle. phase 2: change id1 and id2 as output and read the status of id0 and id3 to complete the secondary dongle identifi- cation phase. this phase provides information about the connected dongle. phase 3: configure mode: change irsl[2:0] as an output and configure the transceiver for the required mode. if two infrared inputs are required, change irsl0 to an input to give the second rece iver channel irrx2. the irsl2 and irsl1 are configured as outputs to keep the transceiver in the required mode. figure 5-36. real dongle interface table 5-21. real dongle interface signals signal name type description irtx o infrared transmit data irrx i infrared receive data id0/irsl0/irrx2 i/o identification signal 0 infrared mode select 0 infrared receive data for transceivers with two rx channels id1/irsl1 i/o identification signal 1 infrared mode select 1 id2/irsl2 i/o identification signal 2 infrared mode select 2 id3 i/o identification signal 2 shielded cable irda-data transceiver with receive channels tx rx-a rx-b ir controller transceiver select logic resistance pull-up v cc irtx irrxi id0/irsl0/irrx2 id1/irsl1 id2/irsl2 id3 asic boundary amd geode? cs5535 companion device data book 145 uart and ir port 31506b 5.12.3.2 virtual dongle the virtual dongle interface is used due to the unavailability of pins for dongle identification and configuration (see fig- ure 5-37). the virtual dongle interface is a method used to run legacy software on the uart/ir controller. the virtual dongle interface uses dedicated uart/ir msrs. (see section 6.12.1 "uart/ir controller specific msrs" on page 380 for complete register and bit formats.) the virtual dongle imitates the real dongle as fa r as legacy software is con- cerned, and there are no plug-and-play requirements for ir transceivers. the software inputs the dongle's id to the id[0:3] bits of msr_uart[x]_mod (uart1 msr 51400038h and uart2 msr 5140003ch) as the primary id encoding. for dongles that use a non-serial transceiver, it identi- fies the consumer ir capabilities. the software should switch id1 and id2 to output mode (so they become irsl1 and irsl2), irsl1 and irsl2 will or will not behave differently (i.e., inv [invert] or nch [no change]) from the previous step and the software should respond by driving the appropriate level on id0 and id3 in the msr_uart[x]_dong register. the operational mode of an infrared dongle that uses a non-serial transceiver is selected by the driving the irsl[2:0] signals. features uses only three pins to connect to ir transceiver. fully supports legacy software written for real dongle, with some manual intervention. all real dongle modes can be supported by changing the msr. limitations no plug-and-play features available. irsl1 and irsl2 pins need to be tied in the ir trans- ceiver for the required mode. msr contents must be changed when changing the transceiver mode. if bios is used to change the msr contents, it must be a factory setting. if the legacy software supports ir transceiver configura- tion, the contents of irsl[2:0] are to be read from the msr and the required bit tieing needs to be done in the transceiver board. figure 5-37. virtual dongle interface mux ir controller id1 id2 id0 id3 uart/ir controller msr_uart[x]_mod msr_uart[x]_dong irsl0 irsl1 irsl2 irtx irrx1 asic boundary ir transceiver tie irsl1 and irsl2 irsl1 irsl2 id1 id2 id0 id3 id0_sec id3_sec 146 amd geode? cs5535 companion device data book low pin count port 31506b 5.13 low pin count port the low pin count port is based on intel?s low pin count (lpc) interface specification v1.0 . in addition to the required pins, the geode cs5535 companion device also supports two optional pins: ldrq# and serirq. the lpc interface supports memory, i/o, dma, and intel?s firmware hub interface. figure 5-38 shows the block diagram of the lpc port. features based on intel?s low pin count (lpc) specification v1.0. serial irq support. supports memory, i/o, and dma cycle types. bus master cycles not supported. clkrun# and lpcpd# not supported. smi# and pme# supported via gpios. on-chip dma transfers through lpc. supports intel?s firmware hub (fwh) interface: ? 5 signal communication interface supporting byte-at- a-time reads and writes. ? lad[3:0] called as fwh0-fwh3 and lframe# as fwh4. figure 5-38. lpc block diagram geodelink? adapter local bus local bus slave local bus master lpc master drq ldrq sirq lpc reg to p i c lframe# ldrq# lad[3:0] serirq to d m a from dma lpc to/from local bus busy lpc master initiates all transactions on lpc bus, takes/issues requests from local bus. local bus master takes request from lpc master and dma. local bus slave issues request to lpc master from local bus. sirq decodes serirq into irq to be passed on to pic. ldrq decodes ldrq# into drq sets and clears. drq combines multiple ldrq# outputs and passes results to dma. lpc reg contains all the lpc i/o registers. lpc to/from local bus lpc to local bus interface module. busy generates busy signal for clock controls. amd geode? cs5535 companion device data book 147 low pin count port 31506b 5.13.1 lpc protocol lpc supports memory read/write, i/o read/write, dma read/write, and firmware hub interface (see table 5-22). data transfers on the lpc bus are serialized over a 4-bit bus. lframe# is used by the host to start or stop transfers. no peripherals drive this signal. a cycle is started by the host when it drives lframe# active and puts information related to the cycle on the lad[3:0] signals. the host drives information such as address or dma channel num- ber. for dma and target cycles, the host drives cycle type (memory or i/o), read/write dire ction, and size of the trans- fer. the host optionally drives data, and turns around to monitor peripherals for completion of the cycle. the periph- eral indicates the completion of the cycle by driving appro- priate values on the lad[3:0] signals. the lad[3:0] signals communic ate address, control, and data information over the lpc bus between the host and the peripheral. the information carried on the lad signals are: start, stop (abort a cycle), transfer type (memory, i/o, dma), transfer direction (re ad/write), address, data, wait states, and dma channel number. the following sections give an overview of fields used. detailed field descriptions are provided in table 5-23 on page 148. start: this field indicates the start or stop of a transac- tion. the start field is valid on the last clock that lframe# is active. it is used to indicate a device number, or start/stop indication. cyctyp: the cycle type field is driven by the host when it is performing dma or target accesses. bits [3:2] are used for cycle type and bit 1 is used for direction. bit 0 is reserved. size: this field is one clock. it is driven by the host on memory and dma transfers to determine how many bytes are to be transferred. bits [1:0] are used to determine size and bits [3:2] are reserved. tar: the turn around field is two clocks, and is driven by the host when it is turning control over to a peripheral and vice versa. in the first clock a host or a peripheral drives the lad[3:0] lines to 1111b, on the second cycle the host or peripheral tri-states the lad[3:0] lines. these lines have weak pull-ups so they will remain at a logical high state. addr: the address field is four clocks for i/o cycles and eight clocks for memory cycles. it is driven by the host on target accesses. this field is not driven on dma cycles. the most significant nibble is driven first. channel/terminal count: the channel field is one clock and driven by the host on dma cycles to indicate the dma channel. only 8-bit channels are supported (0, 1, 2, 3). dma channel is communicated on lad[2:0] and termi- nal count (tc) is communicated through lad3. tc indi- cates the last byte of transfer, based upon the size of the transfer. if an 8-bit transfer and tc is set, then this is the last byte. data: this field is two clocks, representing one byte data. it is driven by the host on target and dma cycles when data is flowing to the peripheral, and by the peripheral when data is flowing to the host. the lower nibble is driven first. sync: this field can be several clocks in length and is used to add wait states. driven by the peripheral on target or dma cycles. sync timeout: 1) the host starts a cycle, but no device ever drives sync valid. if the host observes three consecutive clocks without a valid sync, it can abort the cycle. 2) the host starts a cycle, a device drives a sync valid to insert wait states (lad[3:0] = 0101b or 0110b), but never completes it. this could happen if the peripheral locks up for some reason. the peripheral should be designed to prevent this case: ? if the sync pattern is 0101b, then the maximum number of sync clocks is eight. if the host sees more than eight, it may abort the cycle. ? if the sync pattern is 0110b, then no maximum number of sync clocks took place, the peripheral must have protection mechanisms to complete the cycle. table 5-22. cycle types supported cycle type size size supported intel fwh read 1 byte yes intel fwh write 1 byte yes memory read 1 byte yes memory write 1 byte yes i/o read 1 byte yes i/o write 1 byte yes dma read 1, 2, 4 bytes 1 byte only dma write 1, 2, 4 bytes 1 byte only bus master mem read 1, 2, 4 bytes no bus master mem write 1, 2, 4 bytes no bus master i/o read 1, 2, 4 bytes no bus master i/o write 1, 2, 4 bytes no 148 amd geode? cs5535 companion device data book low pin count port 31506b when the host is driving sync, it may insert a very large number of wait-states depending on pci latencies. the peripheral must not assume any timeouts. sync error indication: a peripheral can report an error via the lad[3:0] = 1010b encoding. if the host was reading data from a peripheral, the data will still be transferred in the next two nibbles, even though this data is invalid, the peripheral must transfer it. if the host was writing, data had already been transferred. in dma if it was a multiple byte cycle, an error sync termi- nates the cycle. for more info on sync timeout and sync error details, refer to the lpc specification . table 5-23. cycle field definitions: target memory, i/o, and dma field # clocks comment start 1 start of cycle. 0000b indicates a start of a cycle. cyctyp 1 cycle type. indicates the type of cycle. bits [3:0] definition 000x i/o read 001x i/o write 010x memory read 011x memory write 100x dma read 101x dma write 1100 reserved 1101 fwh read 1110 fwh write 1111 reserved channel 1 channel #. used only for dma cycles to indicate channel number being granted. the lad[2:0] bits indicate the channel number being granted, and lad[3] indicates the tc bit. the encoding on lad[2:0] for channel number is as follows: lad[2:0] definition 000 i/o read 001 i/o write 010 memory read 011 memory write 100-111 reserved only 8-bit channels are supported. ta r 2 turn-around. the last component driving lad[3:0] will drive it high during the first clock and tri-state during the second clock. size 1 size of transfer. used only for dma cycles. bits [3:0 ] are reserved and must be ignored by the peripheral. lad[1:0] definition 00 8-bit 01-11 reserved only 8-bit is supported for all transfers. data 1 byte dma: 1 byte data phase. the data byte is transferred with the least significant nibble first (d[3:0] on lad[3:0], then d[7:4] on lad[3:0]). dma. the data byte is transferred with the least si gnificant nibble first (d[3:0] on lad[3:0], then d[7:4] on lad[3:0]). only one byte data transfer is supported. addr 8 for memory, 4 for i/o address phase. address is 32-bit for memory, 16-bit fo r i/o. it is transferred most significant nibble first. dma cycles do not use the addr field. amd geode? cs5535 companion device data book 149 low pin count port 31506b sync 1-n sync: allows peripheral or host to synchronize ( add wait-states). generally, the peripheral or host drives 0101 or 0110 until no more wait-states are needed. at that point it will drive 0000. all other combinations are reserved. 0000 sync achieved with no error. dma. sync achieved with no error. also indi cates no more transfer desired for that chan- nel, and dma request is de-asserted. 0101 indicates that sync not achieved ye t, but the part is driving the bus. dma. part indicating wait states. 0110 indicates that sync not achieved yet, but th e part is driving the bus, and expect long sync. dma. part indicating wait states, and many wait states will be added. 1010 special case. peripheral indicating errors, see sync section in protocol overview. dma. sync achieved with error. also indi cates no more transfers desired for that chan- nel, and dma request is de-asserted. 1001 dma (only). sync achieved with no error and more dma transfer desired to continue after this transfer. table 5-23. cycle field definitions: ta rget memory, i/o, and dma (continued) field # clocks comment 150 amd geode? cs5535 companion device data book low pin count port 31506b 5.13.2 cycle protocol start of cycle (see figure 5-39): the host asserts lframe# for one or more clocks and drives a start value on lad[3:0], all peripherals stop driving the lad[3:0] signals even if in the middle of a transfer. the peripheral must always use the last start value when lframe# was active. on the clock after the start value, the host de-asserts lframe#. abort mechanism (see figure 5-40): the host can cause an abort on the lpc interface by driving lframe# active with a start value of 1111b. the host must keep lframe# active for at least four consecutive clocks and drive lad[3:0] to 1111b no later than the fourth clock after lframe# goes active. the host must drive lframe# inactive for at least one clock after an abort. an abort typically occurs on sync timeouts. figure 5-39. start of cycle timing diagram figure 5-40. abort mechanism timing diagram start cyctyp lclk lad[3:0]# lframe# addr tar sync data start tar 1 1 - 8 2 1 - n 2 2 1 1 start cyctyp lclk lad[3:0]# lframe# addr tar sync 11 - 82 1 too many syncs causes timeout peripheral must stop driving chip set will drive high amd geode? cs5535 companion device data book 151 low pin count port 31506b 5.13.2.1 host initiated cycles memory cycles: memory read or write cycles are intended for memory-mapped devices. the addr field is a full 32 bits, and transmitted with most significant nibble first. typically a memory device supports much less addressing and ignores address bits above which it is capable of decoding. i/o cycles: i/o read or write cycles are intended for peripherals. these cycles are gen erally used for register or fifo accesses and have minimal sync times. data trans- fers are assumed to be exactly 1 byte. the host is respon- sible for breaking up larger data transfers into 8-bit cycles. the minimum number of wait states between bytes is 1. the host initiated cycles are shown in table 5-24. 5.13.2.2 dma initiated cycles dma on lpc is handled through the ldrq# line from peripherals and special encodin g on lad[3:0] for the host. single, demand, verify, and increment mode are supported on the lpc interface. block, decrement, and cascade are not supported. channels 0 through 3 are 8-bit channels. only 8-bit channels are supported. asserting dma requests: peripherals need the dma service to encode their request channel number on the ldrq# signal. ldrq# is synchronous with lclk. periph- erals start the sequence by asserting ldrq# low. the next 3 bits contain the encoded dma channel number with the msb first. and the next bit (act) indicates whether the requested channel is active or not. the case where the act is low (inactive) will be rare, and is only used to indi- cate that a previous request for that channel is being aban- doned. after indication, ldrq# should go high for at least one clock. after that one clock ldrq# can be brought low for next encoding sequence (see figure 5-41.) dma transfer: arbitration for dma channels is performed through the 8237 within the host. once the host won the arbitration, it asserts lframe# on the lpc bus. the host starts a transfer by asse rting 0000b on lad[3:0] with lframe# asserted. the host?s assert ?cycle type? and direction is based on the dma transfer. in the next cycle it asserts channel number and in the following cycle it indi- cates the size of the transfer. dma reads: the host drives 8 bits of data and turns the bus around, then the peripheral acknowledges the data with a valid sync. dma writes: the host turns the bus around and waits for data, then the peripheral indicates data is ready through valid sync and transfer of the data. the dma initiated cycles ar e shown in table 5-25. figure 5-41. dma cycle timing diagram table 5-24. host initiated cycles memory or i/o driven by read cycle write cycle start host host cyctyp + dir host host addr host host tar host host sync peripheral peripheral data peripheral host tar peripheral peripheral table 5-25. dma initiated cycles dma driven by read cycle (host to peripheral) write cycle (peripheral to host) start host host cyctyp host host channel host host size host host data host host tar host peripheral sync peripheral peripheral tar peripheral peripheral start msb lsb act start lclk ldrq# 152 amd geode? cs5535 companion device data book low pin count port 31506b 5.13.3 serial irq the lpc supports a serial irq scheme. this allows a sin- gle signal to be used to report isa-style interrupt requests. because more than one device may need to share the sin- gle serial irq signal, an open collector signaling scheme is used. serial interrupt information is transferred using three types of frames: a start frame, one or more irq data frames, and one stop frame (see figure figure 5-42, figure 5-43, and figure 5-44 on page 153). there are also two modes of operation. quiet mode, initiated by the peripheral, and continuous mode, initiated by the host: 1) quiet (active) mode: to indicate an interrupt, the peripheral brings the serirq signal active for one clock, and then places the signal in tri-state mode. this brings all the state machines from the idle state to the active state. the host then takes control of the serirq signal by driving it low on the next clock, and continues driving it low for 3-7 clocks more (programmable). thus, the total number of clocks low will be 4-8. after those clocks, the host drives serirq high for one clock and then places serirq into the tri-state mode. 2) continuous (idle) mode: in this mode, the host ini- tiates the start frame, rather than the peripherals. typ- ically, this is done to update irq status (acknowledges). the host drives serirq low for 4-8 clocks. this is the default mode after reset; it can be used to enter the quiet mode. data frame once the start frame has been initiated, all of the serial interrupt peripherals must start counting frames based on the rising edge of the serirq. each of the irq/data frames has exactly three phases of one clock each: a sam- ple phase, a recovery phase, and a turn around phase. during the sample phase, the device drives serirq low if the corresponding interrupt signals should be active. if the corresponding interrupt is inactive, then the devices should not drive the serirq signal. it will remain high due to pull- up registers. during the other two phases (turn around and recovery), no device should drive the serirq signal. the irq/data frames have a specific order and usage as shown in table 5-26. stop frame after all of the data frames, a stop frame is performed by the host. this is accomplished by driving serirq low for two to three clocks. the number of clocks determines the next mode: if the serirq is low for two clocks, the next mode is the quiet mode. any device may initiate a start frame in the second clock (or more) after the rising edge of the stop frame. if serirq is low for three clocks, the next cycle is the continuous mode. only the host may initiate a start frame in the second clock (or more) after the rising edge of the stop frame. table 5-26. irq data frames date frame number usage 0irq0 1irq1 2 smi# (not supported) 3irq3 4irq4 5irq5 6irq6 7irq7 8irq8 9irq9 10 irq10 11 irq11 12 irq12 13 irq13 14 irq14 15 irq15 31-16 unassigned amd geode? cs5535 companion device data book 153 low pin count port 31506b figure 5-42. start frame waveform figure 5-43. irq frame waveform figure 5-44. stop frame waveform start rec ta r drivers host slave host controller none lclk serirq or start: start pulse width can be from 4-8 cycles, the wi dth is determined by t he value of start width. rec: recover, host actively drives serirq high. tar: turn around cycle. dead cycl e to prevent bus contention. irq set: irq clear: serirq lclk samp rec ta r none irqx serirq samp rec ta r driver none driver samp: sample, slave drives low or leaves high . rec: recover, slave actively drives serirq high if driven low during sample . tar: turn around cycle. dead cycl e to prevent bus contention. stop rec tar host controller none drivers serirq lclk quiet mode: continues mode: stop rec tar serirq host controller none drivers rec: recover, host actively drives serirq high. tar: turn around cycle. dead cycl e to prevent bus contention. 154 amd geode? cs5535 companion device data book low pin count port 31506b 5.13.4 firmware hub interface the firmware hub (fwh) relies on the intel firmware hub interface to communicate with the outside world. this inter- face consists of four bidirectional signals and one ?control? input. the timing and the electrical parameters of the fwh interface are similar to those of the lpc interface. the intel fwh interface is designed to use an lpc-compatible start cycle, with a reserved cycle type code. this ensures that all lpc devices present on the shared interface will ignore cycles destined for the fwh, without becoming ?confused? by the different protocols. when the fwh interface is active, information is trans- ferred to and from the fwh by a series of ?fields? where each field contains four bits of data. many fields are one clock cycle in length but can be of variable length, depend- ing upon the nature of the field. field sequences and con- tents are strictly defined fo r read and write operations. 5.13.4.1 fwh cycles a cycle is started on the ri sing edge of lclk when lframe# is asserted and a valid cycle type is driven on lad[3:0] by the host. vali d cycle types for the fwh are 1101b (read) and 1110b (write). fwh read cycles: a read cycle is initiated by asserting 1101b on lad[3:0] with lframe# low. all data transfers are valid on the rising edge of the lclk. the cycle is illus- trated in figure 5-45 and described in table 5-27. fwh write cycles: a write cycle is initiated by asserting 1110b on lad[3:0] with lframe # low. all data transfers are valid on the rising edge of the lclk. the cycle is illus- trated in figure 5-46 and described in table 5-28. abort operation: lframe# (fwh4) active (low) indi- cates either that a start cycle will eventually occur or that an abort is in progress. in either case, if lframe# (fwh4) is asserted, the intel fwh will ?immediately? tri-state its outputs and the fwh state machine will reset. during a write cycle, there is a possibility that an internal flash write or erase operation is in progress (or has just been initiated). if lframe# (fwh4) is asserted during this frame, the internal operation will not abort. the software must send an explicit flash command to terminate or sus- pend the operation. the internal fwh state machine will not initiate a flash write or erase operation until it has received the last data nibble from the chip set. th is means that lframe (fwh4) can be asserted as late as this cycle (?cycle 12") and no internal flash operation will be attempted. however, since the intel fwh will start ?processing? incoming data before it generates its sync field, it should be considered a non- buffered peripheral device. figure 5-45. fwh read cycle lclk lframe lad[3:0] (fwh3-fwh0) number of clock cycles start idsel addr msize tar sync data ta r 1723 11 2 2 (fwh4) amd geode? cs5535 companion device data book 155 low pin count port 31506b figure 5-46. fwh write cycle table 5-27. fwh read cycle signal clock cycle lad[3:0] peripheral i/o description start 1 1101b i on the rising edge of clk with lframe# low, the contents of lad[3:0] indicate the start of an fwh cycle. idsel 1 0000 i indicates which fwh peripheral is selected. the value on the lad[3:0] is compared to the idsel strapping on the fwh device pins to select which device is being addressed. note: from intel 82802 specification - the boot device must have an id (determined by id strapping pins id[3:0]) of 0. it is advisable that subsequent devices use incremental numbering. addr 7 xxxx i a 28-bit address phase is tran sferred starting with the most signifi- cant nibble first. msize 1 0000b i always 0000b (single byte transfer). tar 1 1111b i the lpc host drives lad[3:0] to 1111b to indicate a turnaround cycle. tar 1 1111b (float) o the fwh device takes control of lad[3:0] during this cycle. wsync 2 0101b o the fwh device drives lad[3: 0] to 0101b (short wait-sync) for two clock cycles, indicating that th e data is not yet available. rsync 1 0000b o the fwh device drives lad[3: 0] to 0000b, indicating that data will be available during the next clock cycle. data 2 xxxx o data transfer is two cycles, st arting with least si gnificant nibble. tar 1 1111b o the fwh device drives lad[3:0] to 1111b, to indicate a turnaround cycle. tar 1 1111b (float) n/a the fwh device floats its output and the lpc host takes control of lad[3:0]. lclk lframe# lad[3:0] (fwh0-fwh3) number of clock cycles start idsel addr msize ta r sync data tar 1722 11 2 1 (fwh4) 156 amd geode? cs5535 companion device data book low pin count port 31506b table 5-28. fwh write cycle signal clock cycle lad[3:0] peripheral i/o description start 1 1110b i on the rising edge of clk with lframe# low, the contents of lad[3:0] indicate the start of an fwh cycle. idsel 1 0000 i indicates which fwh peripheral is selected. the value on the lad[3:0] is compared to the idsel strapping on the fwh device pins to select which device is being addressed. note: from intel( r ) 82802 spec - the boot device must have an id (determined by id strapping pins id[3 :0]) of 0. it is advisable that subsequent devices use incremental numbering. addr 7 xxxx i a 28-bit address phase is tran sferred starting with the most signifi- cant nibble first. msize 1 0000b i always 0000b (single byte transfer). data 2 xxxx i data transfer is two cycles, st arting with least si gnificant nibble. tar 1 1111b i the lpc host drives lad[3:0] to 1111b to indicate a turnaround cycle. tar 1 1111b (float) o the fwh device takes control of lad[3:0] during this cycle. sync 1 0000b o the fwh device drives lad[3:0] to 0000b to indicate it has received data or a command. tar 1 1111b o the fwh device drives lad[3:0] to 1111b, indicating a turnaround cycle. tar 1 1111b (float) n/a the fwh device floats its output and the lpc host takes control of lad[3:0]. amd geode? cs5535 companion device data book 157 real-time clock features 31506b 5.14 real-time clock features the real-time clock (rtc) consists of three main blocks: the digital section, the analog section, and the level-shifter block (see figure 5-47). the digital section contains the bus interface, ram, voltage control, time generator, and the time keeper. the analog section contains the voltage switch and low power crystal oscillator. finally, the level shifter block provides the appropriate voltage level transla- tion of signals to and from the rtc block. level shifters are needed because the rtc is powered by the v pp (output of the analog section), which is different from the v core and v core_vsb power domains. features accurate timekeeping and calendar management alarm at a predetermined time and/or date three programmable interrupt sources valid timekeeping during power-down, by utilizing external battery backup 242 bytes of battery-backed ram ram lock schemes to protect its content internal oscillator circuit (the cr ystal itself is off-chip), or external clock supply for the 32.768 khz clock a century counter additional low-power features such as: ? automatic switching from battery to v sb ? internal power monitoring on the vrt bit ? oscillator disabling to save battery during storage software compatible with the ds1287 and mc146818 figure 5-47. rtc block diagram rtc_seconds rtc_minutes rtc_hours rtc_monthday rtc_months rtc_years time keeper index_reg ctrl_reg a, b, c, d ram i/f gated clocks bus interface q q q time generator update 242x8 bit ram voltage control voltage switch low power osc. 32 khz clock v pp v io_vsb v bat khz32_xci write index read local bus data & ctrls #0 #1 #14 khz32_xco level shifter rtc_weekday data data clock voltage sense voltage select 158 amd geode? cs5535 companion device data book real-time clock features 31506b 5.14.1 external use recommendations it is recommended that the external components for the oscillator be connected as illustrated in figure 5-48. the recommended specifications for those external compo- nents are listed in table 5-29. capacitors c1 and c2 should be chosen to match the crys- tal?s load capacitance. the load capacitance c l ?seen? by the crystal y is comprised of c1 in series with c2 in parallel with the parasitic capacitance of the circuit. the parasitic capacitance is caused by the chip package, board layout, and socket (if any). the rule of thumb in choosing these capacitors is: c l = (c1 * c2)/(c1 + c2) + c parasitic c1 can be trimmed to achieve precisely 32.768 khz. to achieve high time accuracy, use crystal and capacitors with low tolerance and temperature coefficients. figure 5-48. recommended external component connections to other modules r1 y c1 c2 internal external khz32_xci khz32_xco table 5-29. external component recommended specifications component parameters values tolerance crystal resonance 32.768 khz parallel mode user-defined type n-cut or xy-bar serial resistance 40 k ? max q factor 35000 min shunt capacitance 2 pf max load capacitance, c l 9-13 pf temperature coefficient user-defined resistor, r1 resistor 20 m ? ( note 1 ) 5% capacitor, c1 capacitor 22 pf 5% capacitor, c2 capacitor 22 pf 5% note 1. a single 20 m ? resistor may be difficult to acquire. substituting two 10 m ? resistors in series is acceptable. amd geode? cs5535 companion device data book 159 general purpose input/output 31506b 5.15 general pur pose input/output proper use and understanding of the general purpose input/output (gpio) subsystem is the key to applying the geode cs5535 companion device in a custom system design. by totalizing the optional features of the geode cs5535 companion device gpios, system functions such as soft buttons, dd c monitoring, timers, system interrupts, and others, may be implem ented. the system designer should pay careful attention to the suite of features avail- able through the gpio s ubsystem and, because the gpios are multiplexed with other on-chip functions, must make careful trade-offs to obtai n the features desired in the system. the register space for contro l of the gpio subsystem con- tains space for control of 32 gpios. since only 28 gpios are realized, the control bits for the non-existent gpio[31:29], and gpio[23] are marked ?reserved?. gpio[22:16] are multiplexed wit h the lpc bus; therefore, if the system requires an lpc bus, gpio[22:16] are not available as gpios. likewise, gpio[15:14] are multiplexed with the smb (system management bus); if the system requires the smb, gpio[15:14] will be dedicated to this function and not available as gpios. other gpios are mul- tiplexed with individual functions as indicated in table 3-8 "gpio options" on page 47. features input features: ? each of the available gpios may be configured as an input. a block of eight input conditioning func- tions, providing edge detection, event counting, and input filtering, may be configured for use by any eight of the 28 gpios, though all 28 may have edge detec- tion. the optionally-conditioned input may then be fed to steering logic that can connect it to an inter- rupt, or power-management input event (pme). output features: ? each of the available 28 gpios has a configurable output cell. the output cell for each gpio may be independently configured to provide a variety of inter- face options. the cell may be enabled or disabled, configured as a totem-pole or open-drain type, have internal pull-up or pull-down resistors applied, or be inverted. ? as indicated in table 3-8 "gpio options" on page 47, the gpios have differing output driver types and reset defaults. when choosing a gpio for a given function, choose one with a compatible output driver type, and one that the use of, does not make another desired function inaccessible. careful study of this table will assist the system designer in making proper selections of the desired fu nctionality of the suite of gpios. auxiliary functions: ? most of the 28 gpios have additional hard-wired internally-connected functions that may be selected by choosing either the aux_1 or aux_2 outputs. use of these allows internal functions to be accessed at the device pins. table 3-8 "gpio options" on page 47 identifies these auxiliary functions, including access to the uarts and multi-function timers, as well as certain power-management controls. output mapping: ? after passing through the optional input conditioning circuits, any gpio may be mapped (connected) to one of eight pic-level interrupts, or to one of eight power management event (pme) inputs. a given gpio may not be simultaneously mapped to both an interrupt and a pme. the pic subsystem interrupt inputs may be configured to cause the generation of an asmi-type interrupt from any or all of the mapped gpio signals. power domains: ? the gpio circuits are distributed into the working and standby power domains. those circuits in the standby power domain may be used for system wakeup events, since they remain powered when the working power is removed. as indicated in table 3-8 "gpio options" on page 47, gpio[28:24] are located in the standby power domain ; all others are in the working power domain. event/filter pairs 6 and 7 are located in the standby domain; pairs [5:0] are in the working power domain. auto-sense: ? gpio5 and gpio6 have a feature called auto-sense. when reset is applied to th e system, a weak internal pull-up is applied to the pad. when reset is de- asserted, the auto-sense value is used to establish the pull-up/down state on t he de-assertion edge. if nothing pulls down the pad, then the weak pull-up continues to be applied. if the pad is pulled down, then pull-up is set to ?no? and pull-down is set to ?yes?. the output driver does not actively drive the pad, that is, it remains in tri-state mode. if an auto-sensed pull-down is desired, a diode between the reset signal and the gpio pin will pull it down during the auto-sense operation but will have no effect during normal operation. recommended functions: ? system designers at amd have created a list of recommended uses for selected gpios, see table 3- 8 "gpio options" on page 47. the desired functions were matched up with gpios by selecting appro- priate buffer types and multiplexing options to create an optimal list of recommended uses for the gpios. designers may use these recommended functions as a starting point and make modifications to the list as needed to fit the particulars of their system. 160 amd geode? cs5535 companion device data book general purpose input/output 31506b 5.15.1 programming for recommended functions table 3-8 "gpio options" on page 47 includes an ?recommended use? column. shown below are the register settings to achieve the example. example use getting example use note --------------------------------------------------------------------------------------- pci_inta# input_enable = 1 setup gpio interrupt mapper ac_beep out_enable = 1 out_aux1_select = 1 ide_irq0 input_enable = 1 in_aux1_select = 1 ddc_scl out_enable = 1 software write out_value ddc_sda out_enable = 1 software write out_value mfgpt0 out_enable = 1 out_aux1_select = 1 mfgpt1 out_enable = 1 out_aux1_select = 1 pci_intb# input_enable = 1 setup gpio interrupt mapper uart1_tx out_enable = 1 out_aux1_select = 1 uart1_rx input_enable = 1 in_aux1_select = 1 thrm_alrm# input_enable = 1 in_aux1_select = 1 input_invert = 1 slp_clk# out_enable = 1 out_aux1_select = 1 gpio in input_enable = 1 software read read_back gpio in input_enable = 1 software read read_back smb_clk input_enable = 1 in_aux1_select = 1 out_aux1_select = 1 smb_data input_enable = 1 in_aux1_select = 1 out_aux1_select = 1 lpc_ad0 hardware default table 3-6 "divil_ball_opt (msr 51400015h)" on page 34 lpc_ad1 hardware default table 3-6 "divil_ball_opt (msr 51400015h)" on page 34 lpc_ad2 hardware default table 3-6 "divil_ball_opt (msr 51400015h)" on page 34 lpc_ad3 hardware default table 3-6 "divil_ball_opt (msr 51400015h)" on page 34 lpc_drq# hardware default table 3-6 "divil_ball_opt (msr 51400015h)" on page 34 lpc_serirq hardware default table 3-6 "divil_ball_opt (msr 51400015h)" on page 34 lpc_frame# hardware default table 3-6 "divil_ball_opt (msr 51400015h)" on page 34 w ork_aux out_enable = 1 out_aux1_select = 1 low_bat# input_enable = 1 in_aux1_select = 1 amd geode? cs5535 companion device data book 161 general purpose input/output 31506b 5.15.2 register strategy the register set for the gpio subsystem has been arranged in such a way as to eliminate the need for read- modify-write operations. individual gpio control bits may be directly and immediately altered without requiring knowledge of any other gpio states or bit settings. previ- ous systems required the curre nt settings for all gpios to be read, selected pins changed, and the result written back. if this read-modify-write operation was interrupted by another process that also used the gpios, then erroneous operation could result. to avoid the read-modify-write operation, two data bits are used to control each gpio feat ure bit, wherein a feature is enabled or disabled. one register bit is used to establish a logic 1, while a second register bit is used to establish a logic 0. a 1 in a register bit changes the feature bit?s value, while a 0 does nothing. since there are two register bits for each feature bit, for each gpio, there are four combina- tions of register bits possible. the two control bits operate in an exclusive-or pattern, as illustrated in table 5-30. an example 16-bit register co ntrolling a feature bit for eight gpios is illustrated in table 5-31. note that the real regis- ters are 32 bits; 16 bits are used here as an illustrative example. assume that the register in table 5-31 allows setting and clearing of an unspecified ?feature bit? for gpio[7:0]. assume that the 16-bit value given in the example has just been written into the register. in this example, all four pos- sible bit combinations fromtable 5-30 are examined. gpio5 has a 0 in the logic 0 bit position (register bit 13), and a 1 in the logic 1 bit position (register bit 5), so the gpio5 feature bit would become a 1. gpio4 has a 1 in the logic 0 bit position (register bit 13), and a 0 in the logic 1 bit position (register bit 5), so the gpio4 feature bit would become a 0. gpio7 has a 1 in both bit positions 15 and 7. writing a 1 to both the logic 1 and logic 0 bit positions causes no change to the gpio7 feature bit. gpio6 has a 0 in both bit positions 14 and 6. writing a 0 to both the logic 1 and logic 0 bit positions causes no change to the gpio6 control bit. gpio[3: 0], also have 0s in both bit positions, so they experience no change. reads produce a normal and an inverted value. for exam- ple, assume the output enable is set only for gpio4 in the above register. a read would return the value ef10h. actual gpio registers associated with feature bit settings are 32 bits wide and each handle 16 gpios. they are organized into low and high banks. the low bank deals with gpio[15:0], while the high bank deals with gpio[28:24] and gpio[22:16]. in addition to these ?bit registers?, there are value registers for the input conditioning functions. 5.15.3 lock bits many gpio registers are pr otected against accidental changes by lock enable registers that prevent further changes. once a lock bit is set, the associated register can not be changed until the corresponding lock bit is cleared. there are two lock bit registers, one for the high bank (gpioh_lock_en, gpio i/o offset 8ch) and one for the low bank (gpioh_lock_en, gpio i/o offset 3ch). all gpio registers are protected by lock bits except the high and low bank read back registers, (gpio[x]_read_back), high and low bank positive edge status registers (gpio[x]posedge_sts), the high low bank negative edge status registers (gpio[x]negedge_sts), and of course the lock enable registers themselves. table 5-30. effect on feature bit logic 0 bit position logic 1 bit position effect on feature bit 0 0 no change 1 0 feature bit is cleared to 0 0 1 feature bit is set to 1 1 1 no change table 5-31. 16-bit gpio control register example bit no. ?1? sets control bit to 0 ? 1? sets control bit to 1 1514131211109876543210 value 1001000010100000 gpio # 7654321076543210 162 amd geode? cs5535 companion device data book general purpose input/output 31506b 5.15.4 gpio basic i/o configuration the general purpose input and output (gpio) interface is illustrated in figure 5-49. t he figure represents one of twenty-eight gpios potentially available. note the gpios [31:29] and [23] are non- existent. table 3-8 "gpio options" on page 47 provides a complete list of features for each gpio and should be consulted when configuring a system. each gpio has basic configuration options used to set up the characteristics of the gpio for either input or output. each of the functions in the list below follows the gpio reg- ister strategy outlined insection 5.15.2 "register strategy" on page 161 unless otherwise noted. this strategy allows individual gpios to be modified without accidentally changing the characteristi cs of unrelated gpios, and with- out requiring ?read-modify-write? cycles. all values are active high. out_en. when high, enables this gpio/out_aux for output. a pad may be configur ed for output, input, or both. in_en. enables this gpio/in_aux for input. a pad may be configured for input , output, or both. out_val. this will establish the value driven to the pad when it is selected as an output, unless either out_aux1 or out_aux2 are selected. the value driven to the gpio pad is subject to an optional inver- sion. out_invrt_en. when high, inverts the gpio/out_aux output value. in_invrt_en. inverts the signal applied to the ball, and presents the inverted value to all follow-up circuitry (i.e., input conditioning functions). affects both gpio and in_aux. out_od_en. configures this gpio/out_aux for open-drain operation. when the output pad is to be driven low, the pad is driven low. when the output pad is to be driven high, the pad is allowed to float and is not driven. out_aux1_sel and out_ aux2_sel. selects an internal auxiliary source for the output value. table 3-8 "gpio options" on page 47 identifies all the possible internal connections for these two auxiliary sources. in_aux1_sel. selects an internal destination other than the gpio for the ball. table 3-8 "gpio options" on page 47 lists all the functions that may be connected in this manner. pu_en. applies a weak pull-up to the pad. the effect of this control is independent of all other settings except pd_en. if pu_en is set by software, pd_en is auto- matically cleared. affects both gpio and in_aux. pd_en. applies a weak pull-down to the pad. the effect of this control is independent of all other settings except pu_en. if pd_en is set by software, pu_en is auto- matically cleared. affects both gpio and in_aux. figure 5-49. gpio configuration event counter digital filter ball pull-down enable open-drain enable output enable output invert enable read status [7:0] [7:0] input invert input enable pull-up enable positive edge enable event count event count enable filter amount filter enable input conditioning functions (1 of 8) aux1 aux2 negative edge enable pme interrupts event enable x,y,z,w interrupt mapping registers x,y,z,w pme mapping registers output value enable aux1 amd geode? cs5535 companion device data book 163 general purpose input/output 31506b 5.15.5 input conditioning functions gpios and their corresponding in_aux function in the geode cs5535 companion device may have their inputs conditioned by configurable circuitry as illustrated in figure 5-49 on page 162. any gpio may be connected to one of eight input conditioning functions, each consisting of a digital filter and an event co unter (known as an event/fil- ter pair). each gpio is followed by an edge detection func- tion that may be set for either positive or negative going edges. as shown in figure 5-49, the edge detection func- tion may be used to monitor the output of th e event/filter pair that has been associated wit h that particular gpio, or it may be used independently of the event /filter pair. these functions are enabled as follows: in_fltr_en. enables the input filter function of the associated gpio. evntcnt_en. enables the event counter function of the associated gpio. in_posedge_en and in_negedge_en. enables the edge detection function and mode. the final input value may be read back by a software accessible register (gpio[x] _read_back). it may also be used as an interrupt or a power management event. there are a total of eight digit al filter/event counter pairs that are shared by 28 gpios. there is a selection function to associate a given filter/counter pair with a given gpio. all gpios incorporate edge detection. 5.15.5.1 input filter conditioning function the digital filter is one-half of a filter/event conditioning cir- cuit. (the other half is the even t counter.) the filter is used to produce a stable output from an unstable input. mechan- ical switch de-bounce is a typical use. to use one of the eight digital filters, it must first be assigned to one of the gpio inputs using one of the gpio_fe[x]_sel registers (g pio i/o offsets f0h-f7h); where ?x? is the number of the filter/event pair, 0 to 7. then the filter function must be enabled through either the gpiol_in_fltr_en (gpio i/o offset 28h) or the gpioh_in_fltr_en (gpio i/o offset a8h) registers, depending on whether the selected gpio is in the high [28:16] or low [15:0] bank. finally, a gpio_fltr[x]_amnt (gpio i/o offsets 50h, 58h, 60h, 68h, 70h, 78h, d0h, and d8h) must be determined and then programmed to estab- lish the filter?s stability period. the associated gpio input must ultimately remain stable for a fltr_amnt number of 32 khz clock edges in order for the output to change. a fltr_amnt of 0 effectively disables the filtering function, because the counter will not roll over from 0 to all 1s. the maximum fltr_amnt is ffffh. the digital filter is based upon a 16-bit programmable down-counter. an initial count is loaded into the counter via the gpio_fltr[x]_amnt regi ster. when the associated gpio input changes, the counter begins counting down from fltr_amnt towards 0. if the associated gpio input remains stable for the length of the count-down period, then the counter reaches 0 and produces an output pulse to whatever the gpio is internally connected to. if the associated gpio input changes during the count-down period, then the counter reloads the initial count from the gpio_fltr[x]_amnt register and begins counting down towards 0 again. direct access to the counter?s state is provided by the r/w register gpio_fltr[x]_cnt, that may be read at any time to determine the current value of the counter. the gpio_fltr[x]_cnt register may also be written to at any time, thereby jamming the c ounter state forward or back- ward from the current count. reads and writes of the gp io_fltr[x]_cnt register are internally synchronized to avoid false read values and cor- rupted writes, that is, reads and writes may occur to a filter circuit without concern of the phasing or timing of the 32 khz clock edges. when gpio[x]_in_fltr_en is low the filter circuit is not clocked. the filter circuit is used to pr oduce a stable output from an unstable input. mechanical switch de-bounce is a typical use. the default value for all flip-flops, the down counter, and the filter amount register is zero. software estab- lishes the filter amount. as lo ng as the preliminary input on the left matches the filtered input on the right, the circuit is stable and the counter contin uously loads the filter amount value. when the preliminary input changes, the counter begins to count. if the input remains steady, then the counter reaches zero and enables loading the value flip- flop. this brings the circuit back to the stable point. if the input does not remain steady , then the counter reloads. the preliminary input on the left must remain steady the ?filter amount? number of clock edges for the final input on the right to change. a filter amount of zero effectively dis- ables the filtering function because the down counter will not roll over backwards to all ones. the maximum filter amount is ffffh 164 amd geode? cs5535 companion device data book general purpose input/output 31506b 5.15.5.2 input even t counter conditioning function the event counter is one half of a filter/event conditioning circuit, and is in series with it s associated filter. (the other half is the digital filter.) it counts events and can produce an output when a predefined count is reached. the event counter may be down-counted by writing to a particular address. it may be used as a rate counter that may be peri- odically read, and that produces no output at all. to use one of the eight event counters, it must first be assigned to one of the gpio inputs using one of the gpio_fe[x]_sel registers (wher e x is the number of the filter/event pair, 0 to 7). then the associated digital filter must be enabled, through ei ther the gpiol_in_fltr_en or gpioh_in_fltr_en regi sters, depending on whether the selected gpio is in the high [28:16] or low [15:0] bank. if digital filtering is not required, program the associated gpio_fltr[x]_amnt registers to 0000h. finally, the desired ?compare valu e? (gpio_evntcnt[x] _compare) must be determined and then programmed to establish the number of ev ents that will produce an out- put when that count has been reached. the event counter is based upon a 16-bit programmable up/down counter. the up-down counter counts positive edges of the selected gpio input and produces a constant or level output when the gpio_evntcnt[x] (counter value) exceeds the cpio_evntcnt[x]_compare (com- pare value). the output can be read as the gpio and/or used to drive an auxiliary input. the counter may be counted down one count by writing to one of two addresses, depending on which bank (high or low) the associated gpio resides in. knowledge of which gpio is associated with th e event counter is required, since these two decrementer registers have a dedicated bit for each gpio. when counted down, this counter, unlike the counter in the digital filter, will roll over from 0000h to ffffh. typically, decrementing is used to clear an inter- rupt or power management event as part of the associated service routine. 5.15.5.3 uses of the event counter such an auxiliary input could be used to drive an asmi or maskable interrupt. assume th e compare value is set to 0. the service routine clears the asmi by decrementing the counter via the mechanism illustrated. if additional events have occurred, the count does not decrement to 0 and the asmi remains asserted. the count up and down inputs are synchronized such that false values are not created if up and down pulses occur at or near the same instant in time. the counter will not decrement through 0. alternatively, the compare value could be set to a higher value to trigger an asmi or interrupt when a certain number of events has occurred. in this case, the asmi or interrupt is cleared by writing the counter to 0. lastly, the input value may be ignored and the event counter used as a rate indicator. if software reads the counter at a fixed periodic interval, an input pulse rate may be measured. such an approach may be used to imple- ment a tachometer function . the counter will increment past all fs back to 0. as suggested above, the counter may be read or written under software control. the read and write operations are synchronized such that false values are not created if count up pulses occur at or near the same instant in time. 5.15.5.4 input edge conditioning function the edge detection function is illustrated as part of figure 5-49 on page 162 . it is normally used to generate an asmi or maskable interrupt on each positive and/or negative edge of an input signal. use of this function simultaneously with the event counter function is somewhat logically mutu- ally exclusive, but is not prevented in hardware. each gpio has the optional edge detection function. the reset default for the detection circuit establishes a 0 level on gpio[x]_posedge_en and gpio[x]_negedge_en. when both are set to 0, the edge detection function is disabled. if either a positive or nega- tive edge detection is enabled, an active high output is pro- duced when the appropriate edge occurs. this level must be cleared by writing to either the gpio[x]_posedge_sts or the gpio[x]negedge_sts registers, whichever is appropriate. if another edge occurs before clearing, the active high output is not af fected. if the clear action occurs at the ?same time? as another edge, the result is not defined. each edge detection function is controlled by four registers as follows: positive edge enable (gpio[x]_posedge_en). enabled if feature bit is high. negative edge enable (gpio[x]_negedge_en). enabled if feature bit is high. positive edge status (g pio[x]_posedge_sts). set indicates edge. write 1 to clear. negative edge status (g pio[x]_posedge_sts). set indicates edge. write 1 to clear. amd geode? cs5535 companion device data book 165 general purpose input/output 31506b 5.15.5.5 output steering (mapping) outputs from the internal gpio circuits, driven by inputs to the geode cs5535 companion device from the system, may be steered (or ?mapped?) to either interrupts, or power management events (pme). suff icient steering logic exists in the geode cs5535 companion device to provide for eight independent interrupts and simultaneously for eight independent pmes. the eight gpio interrupts are all in working power domain; of the eight pmes, [7:6] are in standby power domain and [5:0] are in working domain. those in the standby power domain are intended to be used to awaken the system when the working power domain is off, however, they may also be used when the working power domain is on. the interrupts are connected to the pic subsystem, and the pmes are connected to t he power management sub- system. four 32-bit steering registers control the routing of the gpios? internal output (that produced by an input to the chip from an external source, or from one of the internally- connected aux inputs) to either an interrupt or pme. the set of four registers taken together, contain a nibble for each gpio. the upper bit of each nibble selects either a pme (if high) or an interrupt (if low). the remaining three bits of each nibble select which of the eight possible inter- rupts or pmes the gpio will be steered to. the four registers are identifie d as gpio mapper x, y, z, and w. their gpio associations are as follows: gpio_map_x = gpio[7:0] gpio_map_y = gpio[15:8] gpio_map_z = gpio[23:16] gpio_map_w = gpio[31:24] the steering logic does not prohibit mapping of two or more gpios to the sa me output, but it is impossible to cre- ate a single gpio that functi ons simultaneously as both an interrupt and a pme. registers x, y, z, and w default to all 0s, as do both the high and low evnt_en registers. thus, all gpios are mapped to int[0] after a reset, but none are enabled. 5.15.5.6 auto-sense two gpios (gpio5 and gpio6) have a function called ?auto-sense?. auto-sense is a method of automatically determining whether or not to apply a pull-up or pull-down to the corresponding gpio input. auto-sensed inputs behave as follows: when reset is applied to the system, a weak pull-up is applied to the pad. when reset is de-asserted, the sensed value is used to establish the pull-up/down st ate on the de-assertion edge. if nothing pulls down the pad, then the pull-up continues to be applied. if the pad is pulled down, then the pull-up is cleared to 0 and the pull-down is set to 1. if a pull-down is desired, a diode between the reset signal and the gpio pin will pull it down during the auto-sense operation but have no effect during normal operation. disabling the auto-sensed pull-up or pull-down requires more program operation than just disabling the pull-up or pull-down through the gpiol_pu_en or gpiol_pd_en. if the pullup was enabled through auto-sense, the proce- dure to disable is: 1) disable the pull-up in gpiol_pu_en. 2) enable the pull-down in gpiol_pd_en. 3) disable the pull-down in gpiol_pd_en. if the pull-down was enabled through auto-sense, the pro- cedure to disable is: 1) disable the pull-down in gpiol_pd_en. 2) enable the pull-up in gpiol_pu_en. 3) disable the pull-up in gpiol_pu_en. 166 amd geode? cs5535 companion device data book multi-function general purpose timer 31506b 5.16 multi-function g eneral purpose timer the multi-function general purpose timer module con- tains eight multi-function general purpose timers (mfgpts). six of the eight mfgpts are in the working power domain running off a 32 khz clock or a 14.318 mhz clock, while the other two are in the standby power domain running off a 32 khz clock. the working power domain contains the following blocks: six mfgpts each split into three blocks, one containing i/o registers, one containing the clock switch, and one containing the timer logic. 15-bit prescaler to divide down the 14.318 mhz clock and generate 15 carry-out signals. 15-bit prescaler to divide down the 32 khz clock and generate 15 carry-out signals. logic to implement local bus interface, control logic, msr registers, and nmi, irq, and reset output events. two blocks containing i/o registers to write into the two mfgpts in the standby power domain. the standby power domain contains the following blocks: tw o m f g p t s . 15-bit prescaler to divide down the 32 khz clock and generate 15 carry-out signals. interface for signals going between standby and working power domains. figure 5-50 shows the top level block diagram of the multi- function general purpose timer module. features each mfgpt operates independently and can have the following features: 32 khz or 14.318 mhz clock selectable by software (mfgpt0 to mfgpt5 only; mfgpt6 and mfgpt7 use 32 khz clock). programmable input clock prescaler divisor to divide input clock by 2 i , where i = 0 to 15. watchdog timer (trigger gpio output, interrupt, or reset). pulse width modulation (pwm). pulse density modulation (pdm). blink (low frequency pulse for led). general purpose timer. generate gpio outputs. provide outputs for generating reset (limited to mfgpt0 to mfgpt5), irqs, nmi, and asmi (indirectly through pic). figure 5-50. mfgpt top level block diagram working domain control and msr registers mfgpt0 mfgpt6 bus interface reset and interrupt generation power domain crossing i/f standby domain 14.318 mhz 32 khz prescaler prescaler 32khz prescaler i/o reg clock switch timer mfgpt1 i/o reg clock switch timer mfgpt2 i/o reg clock switch timer mfgpt3 i/o reg clock switch timer mfgpt4 i/o reg clock switch timer mfgpt5 i/o reg clock switch timer i/o reg i/f mfgpt7 i/o reg i/f mfgpt6 timer mfgpt7 timer amd geode? cs5535 companion device data book 167 multi-function general purpose timer 31506b 5.16.1 prescaler the 15-bit prescaler is a binary down counter, dividing down the incoming clock, and provides 15 outputs for the mfgpts. the frequency of th ese outputs ranges from 2 -1 to 2 -15 of the input frequency and each pulse is one incom- ing clock high, so these outputs function as increment enables for the mfgpts. the prescaler resets to 0000 16 and starts decrementing after reset. the prescaler output vector, psclr_out[14:0], is based on prescaler counter psclr_cnt[14:0], where psclr_out[i] = &(~psclr_cnt[i:0]) (i.e., prescaler output bit i is asserted if the prescaler counter from bit i down to bit 0 are all low). when the prescaler reaches 0000 16 , all prescaler outputs are asserted at that time. the external clock for the prescaler is activated if there is one or more mfgpts activated using it as its clock source; it is also activated for mfgpt i/o register writes and syn- chronous counter reads (onl y for 14.318 mhz) when the mfgpt being written has already selected the 14.318 mhz clock as its clock source. whenever the external clock is activated, the prescaler counts. therefore, multiple mfgpts and register access can affect the prescaler counting. from the point of view of the mfgpt, once the mfgpt is disabled and then re-enabled, it cannot be determined exactly when the prescaler carry-out occurs as it does not know how long the prescaler has been stopped, if at all. 5.16.2 i/o registers block the i/o register write data is fi rst stored in i/o register sub- modules before being transferred over to the mfgpts. there are two types of i/o register sub-modules, one for the working power domain and one for the standby power domain. the main difference is that for the working power domain, except for the counter register, the register values here and the register values in the timer are the same. for the standby power domain, the register values in the i/o register sub-module cannot be relied upon except during write, as this logic could have been powered down in standby mode and the register data is therefore invalid. for the standby power domain, the read always comes from the timer directly. 5.16.2.1 mfgpt register set there are four software accessible i/o registers per mfgpt: up counter, comparator 1 value, comparator 2 value, and setup registers. (s ee section 6.17 "multi-func- tion general purpose timer register descriptions" on page 483 for register details.) writes to these registers are first stored here and then transferred to a separate copy of the register in the timer. for mfgpt0 to mfgpt5, read of these registers, except for the counter, comes from the registers here, while read of the counter register comes from the timer. for mfgpt6 and mfgpt7, reads of these registers comes from the copy inside the timer. (tw note: restate reason or be more precise in reference.) 5.16.2.2 setup register the setup register contains the following control fields that control the mfgpt operation: counter enable. enables the up counter to count (it does not enable/disable other mfgpt functions). clock select. instructs the clock switch logic to use the 32 khz clock as the mfgpt clock if low or the 14.318 mhz clock if high, once this register has been written (only for mfgpt0 to mfgpt5). scale factor. selects the prescaler divide scale factor for up counter to increment. stop enable. enables the up counter to stop counting during a system power m anagement sleep mode (for mfgpt0 to mfgpt5) or st andby mode (for mfgpt6 and mfgpt7). external enable. enables the up counter to be cleared and restarted rather than performing the next increment each time there is a low to high transition detected on the gpio input associated with the timer. an asynchro- nous edge-detector catches t he transition; the signal is then synchronized and sent to clear the counter synchronously. therefore, the clear does not occur immediately on the transition. reverse enable. flips the order of the up counter outputs going to the compare 1 circuit so that bit 0 becomes bit 15, bit 1 becomes bit 14, etc. this allows the timer logic to generate a pdm signal instead of a pwm signal. to properly generate a pdm signal, the compare 2 value should be set to ffff 16 to allow the compare 1 value to establish the density. compare 1 mode. controls the compare 1 output. there are four cases: 00: disabled. output is low. 01: compare on equal. the compare output goes high when the up counter value, after going through bit reverse logic, is the same value as the compare 1 value. 10: compare on ge. the compare output goes high when the up counter value, after going through bit reverse logic, is greater than or equal to the compare 1 value. 11: event. same as ?compare on ge?, but an event is also created. this event can be read and cleared via the mfgpt setup register and is used to generate interrupt and reset. compare 2 mode. same as compare 1 mode, except this controls the compare 2 output. the up counter is directly compared against the compare 2 value (i.e., without going through bit reverse logic). all of the above fields, except count enable, are write-once only. 168 amd geode? cs5535 companion device data book multi-function general purpose timer 31506b compare status/event bits the setup register also contains two status bits: one from compare 1 and one from compare 2. if event mode is selected, then these two stat us bits represent the events from the two compare circuits, and writing a 1 to one of the bits would clear that particular event. if event mode is not selected, then the status bi ts read back the compare out- puts, and writing to those bits has no effect. note that since this logic is in the working power domain, mfgpt6 and mfgpt7 would lose these events when v core is powered off. in order for events to be c aptured again, the chip has to have v core powered up out of standby mode and then come out of reset. the compare 1 and compare 2 outputs may change simultaneously on the same mfgpt clock edge. however, when checking the outputs through the two status bits after this occurred, on rare occasions the read may find only one of the two outputs changed to the new value. this could occur when the two outputs change at about the same time they are synchronized, by separate synchronizers to the local bus clock domain, and one synchronizer captured the new value in time while the other one does not. a subse- quent read can show that both outputs did change states. 5.16.2.3 register initializat ion sequence for event mode if the setup register is written before the other three i/o registers, and if event mode is selected for compare 1 mode or compare 2 mode, then events will be triggered immediately. this is because the compare outputs will look for a compare register value greater than or equal to the counter, and the result will be true as those registers are all 0. to avoid triggering these events on setup register initial- ization, first initialize the compare 1 value and compare 2 value registers before initializing the setup register. 5.16.2.4 register data tr ansfer to/from mfgpt only word writes and dword writes are accepted for i/o register accesses; byte wr ites to i/o registers are ignored. the dword write w ould cause the two i/o regis- ters located within the dword boundaries to be written in parallel. if up counter, compare 1 value, or compare 2 value registers are written while the mfgpt is running, it could cause the compare outputs to change in the middle of a prescaler period (i.e., not at a clock cycle where the prescaler signals a counter increment). for mfgpt0 to mfgpt5, the clock switch circuitry disables all clocks to mfgpt until the setup register has been written. there- fore, even if the up counter, compare 1 value, and/or compare 2 value registers are written before the setup register; these register values would get transferred to the timer at the same time as the setup register values. all reads and writes to mf gpt registers can be done by software at any time and are completed without requiring any additional software operation and without affecting the proper operation of the mfgpt as long as a clock to the mfgpt has been selected by writing to the setup register. on a write, the write transfer on the bus is considered com- plete when the write to the register in the i/o register sub- module is complete. this occurs before the register data is transferred to the timer. however, a subsequent read or write to the same register will be held up until that first write transfer to the timer is complete. the setup register, except for bits 13 and 14, are handled in the same way as the compare 1 value and compare 2 value registers. bits 13 and 14 write and read were dis- cussed earlier, where the entire logic is in the working power domain. 5.16.2.5 register re -initialization if it is necessary to re-initialize the up counter, compare 1 value, or compare 2 value, the following sequence should be followed to prevent any spurious reset, interrupt, or out- put pulses from being created: 1) clear counter enable bit to 0. 2) clear interrupt enable, nmi enable, and reset enable bits in msrs; disable gpio inputs and outputs. 3) update up counter, compare 1 value, and compare 2 value registers as desired. 4) when updates are completed, clear any event bits that are set. 5) set up interrupt enable, nmi enable, and reset enable bits in msrs; enable desired gpio inputs and outputs. 6) set counter enable bit to 1. 5.16.3 clock switch the clock switch output is disabled at reset and selection can only be done one time after reset, at the first write to setup register. restriction on register r ead/write sequ ence due to clock switch note that because the timer clock is stopped until the first write to the setup register, a write to one of the other three i/o registers during this time could not complete its transfer to the timer. as a result, a se cond access, read or write, to the same register will cause the bus interface to hang, as the second access waits for th e first access (the initial write) to complete before completing its own operation. but since the first access cannot co mplete without a clock, the second access is in limbo. this means no more accesses can occur, so there is no way to write to the setup register to enable the timer clock. care should be taken to see that this situation does not occur. amd geode? cs5535 companion device data book 169 multi-function general purpose timer 31506b 5.16.4 single mfgpt figure 5-51 shows the functionality of one of these timers. there are two types of timers, one for the working power domain and one for the standby power domain. figure 5-51. mfgpt block diagram standby state/ 32 khz/14 mhz count_enable external enable gpio gpio input value little endian big endian bit reverse compare 1 compare 1 value compare 2 compare 2 value clear clear & re-start reverse enable compare 1 output compare 1 mode compare 2 mode sleep state compare 2 output 16 bit sync up counter stop enable count 14 mhz/32 khz prescaler_carry_outs compare 1 event compare 2 event 15 v core scale factor 0 4 170 amd geode? cs5535 companion device data book multi-function general purpose timer 31506b 5.16.4.1 clock selection and counter increment the mfgpt can use either the 32 khz clock or 14.318 mhz clock as the clock source (mfgpt6 and mfgpt7 in standby power domain are limited to the 32 khz clock). when the counter enable bit is high, the mfgpt is acti- vated and capable of counting. an actual increment is per- formed when the selected prescaler divide-by signals the increment; this is done through the scale factor selecting one of 16 signals. table 5-32 shows how the scale factor effectively divides down the incoming clock. 5.16.4.2 compare 1 an d compare 2 outputs when the up counter reaches the compare 1 value, the compare 1 output is asserted. when the compare 2 value is reached, the compare 2 output is asserted, and the up counter then synchronously clears and restarts. the mfgpt outputs coming from compare 1 and compare 2 are all glitch-free outputs. the compare outputs and events may change in the mid- dle of a prescaler period if new values are written to the up counter, compare 1 value, or compare 2 value registers. these compare outputs can be used to trigger their respective events and drive gpio outputs. the events are used to trigger interrupts, nmi, and reset. 5.16.4.3 gpio input the up counter could also be software selected to have a gpio input positive edge as an other source for the counter to clear and restart. the gpio input signal is asynchronous to the timer and the timer uses a flip-flop to capture the gpio rising edge. it takes up to one prescaler clock period plus two mfgpt clock periods from the gpio rising edge for the clear to take effect. once the counter is cleared, this edge detect circuit can then accept a new gpio edge. each individual pulse can be as short as a few nanosec- onds wide for the rising edge to be captured. if this feature is not selected or the counter is disabled, the clear counter output and the edge detector are kept de-asserted. 5.16.4.4 bit reverse and pulse density modulation figure 5-52 shows how the little endian/big endian bit reverse functions. table 5-33 on page 171 shows a 3-bit example of pulse density modulation; note that the mfgpt has a 16-bit implementation. if the desired pulse train is of the opposite polarity, this can be inverted in the gpio or generated with a different compare 1 value. figure 5-52. mfgpt bit reverse logic table 5-32. mfgpt prescaler clock divider scale factor input clock divide-by 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 input word from up counter output word to compare circuit amd geode? cs5535 companion device data book 171 multi-function general purpose timer 31506b 5.16.5 working power domain logic the working power domain logic consists of the local bus interface, control logic, msrs, and nmi, irq, and reset output events. when event mode is enabled, the nmi, irq, and reset output events logic gathers the event outputs of all eight mfgpts and then generates the interrupt and resets out- puts based on msr settings. the interrupt outputs go to the pic that can then trigger an irq or asmi. note that mfgpt6 and mfgpt7 cannot trigger reset. these outputs are controlled by msr bits, and the nmi output can be fur- ther controlled by the msb of i/o address 070h. 5.16.6 power domain crossing interface logic the asynchronous internal standby state signal will dis- able/enable the working power domain interface immedi- ately. therefore, any bus operation active at that time will have an indeterminate result. table 5-33. mfgpt pulse density modulation example up counter output bit reverse output pulse train output for given compare 1 value (note 1) 12456 000 000 0 0 0 0 0 001 100 1 1 1 0 0 010 010 1 1 0 0 0 011 110 1 1 1 1 1 100 001 1 0 0 0 0 101 101 1 1 1 1 0 110 011 1 1 0 0 0 111 111 1 1 1 1 1 note 1. compare 2 value must be set to all 1s for pulse density modulation. 172 amd geode? cs5535 companion device data book power management control 31506b 5.17 power management control the power management control (pmc) module is a geodelink? device whose function is to control all aspects of power management. power management is event driven meaning that, in general, any action that the pmc performs is predicated on some event. these events can come from other geodelink devices, including the cpu module inside the geode gx processor for example, or events coming from other off-chip sources. the pmc is compatible with the industry standard power management capabilities as defined in the advanced con- figuration and power interface (acpi) v2.0 specification . an os that conforms to acpi can take advantage of the geode cs5535 companion device acpi support hardware. advanced power management (apm) is another power management approach that the pmc supports. apm is a subset of acpi and therefore will not be directly discussed. components in a geodelink architecture based system have hardware and software means of performing power management which the pmc controls. a high performance computing system consumes mu ltiple watts of power when fully on. however, with geodelink architecture, system power consumption is significantly lower on average through the use of power states that reduce power needs when the system is idle. 5.17.1 power domains the pmc module consists of three blocks: working, standby and rtc. the working block contains all circuits and functions associated with the working power domain. it includes the working state machine, local bus interface, acpi power management registers, and power management supporting logic (i.e., counters, timer, ccu, etc.). the main function of the workin g block is to put the system into sleep, that is, turn off clocks to the system and disable i/os to reduce power consumption. the standby block contains all circuits and functions associated with the standby power domain. it includes the standby state machine, acpi registers, and power management supporting logic (i.e., counters, reset, ccu, etc.). the function of the standby logic is to control power to the working power domain. the pmc disables all interfaces between the standby and working domains while the working power is off. a special feature of the standby state machine is called skip which allows the system to power up immediately when power is applied. see the signal description for the pwr_but# in table 3-9 "gpiox available functions descriptions" starting on page 49 for additional details. the rtc block contains the timing circuits for keeping real time. these circuits are powered by v bat (ball a3). it is not a device requirement that the rtc block be powered during mechanical of f. if a system design does not require that real time be kept, then v bat should be tied to ground. 5.17.2 power states table 5-34 shows the supported acpi power states and how they relate to the geode gx processor/cs5535 com- panion device system. acpi power states not described are not supported. table 5-34. supported acpi power management states acpi states hardware states global system state sleep state c state geode gx processor state geode cs5535 companion device working logic system main memory geode cs5535 companion device standby logic g0: working s0 c0 fo fo fo on ahcg ahcg ahcg c1 suspend on halt ahcg ahcg g1: idle s1: sleeping c2 sleep sleep auto-refresh on (sleep) s3: save-to-ram off off off auto-refresh standby s4: save-to-disk off off off off g2: soft off s5 off off off off standby g3: mechanical off off off off off off off amd geode? cs5535 companion device data book 173 power management control 31506b 5.17.2.1 acpi system power states g0/s0: not sleeping. software is executing code or could be halted waiti ng for a system event. g1/s1: requires explicit software action to enter this state. all geode gx processor, geode cs5535 companion device, and main memory states main- tained. all system clocks may be turned off except 32 khz or selected additional clocks may be left on as required. the pmc provides generic controls sleep_x and sleep_y that may be used to control the ?d? states of external system devices (not described in this data book, see acpi specification for details). two additional internal signals control pci and ide input and outputs. a wakeup event brings the system back to the opcode following the one that initiated entry into s1. context restore operation is not r equired on the geode gx processor, geode cs5535 companion device, or main memory. g1/s3: save-to-ram state. requires explicit software action to enter this st ate. the geode cs5535 companion device and other system context are lost. system state is saved in the main memory. to properly support this state, main memory power must be controlled by working power while the geode cs5535 companion device, geode gx processor, and all other system components power must be controlled by work_aux power. note that this applies only to the working domain of the geode cs5535 companion device. the standby domain must be continuously supplied from standby power. g1/s4: suspend-to-disk state. requires explicit soft- ware action to enter this state. same as s3 state, but the system state is ?saved? on the hard drive or other mass storage device. only standby power is on while in this state. g2/s5: requires explicit software action to enter this state. all system context is lost and not saved. oper- ating system re-boot is requ ired. the 32 khz clock is kept running for standby pmc and selected gpio and mfgpt circuits. g3: software action is not required to enter this state. working power and standby power are removed. the only domain that may be powered is the rtc. it is not a requirement that the rtc be powered. 5.17.2.2 cpu power states g0/s0/c0: processor actively executing instructions and clock running. cache snoops supported. g0/s0/c1: hlt instruction executed. usually occurs in the operating system?s idle loop. operating system waiting for power management event (pme), interrupt, or asmi. cache snoops are supported while in this state, so bus mastering activity can safely occur. g1/s1/c2: processor is in the lowest power state that maintains context in a software invisible fashion. entered as part of the s1 sequence. the susp#/suspa# signaling protocol indicates entry. susp# is not an explicit external signal, it is part of the cis packet. (see section 5.2.14 "cpu interface serial (cis)" on page 87 for further details.) no explicit soft- ware action required. however, this state can be entered by explicit software action by reading the acpi p_lvl2 register provided by the geode gx processor?s glcp. 5.17.2.3 hardware power states fo (full on): from a hardware reset, all clocks come up full on or always ru nning. generally, the system should not be left in this state. the ahcg state should be used. ahcg (active hardware clock gating): this is the desired mode of operation; it utilizes automatic hard- ware clock gating. latency to turn on a clock is near 0. this hardware state should be established at system initialization by bios code; after initialization it needs no additional support. ahcg is invisible to the operating system, acpi, or other software based power manage- ment facilities. suspend on halt: see cpu power state g0/s0/c1. sleep: see cpu power state g1/s1/c2. auto-refresh: the memory controller issues an auto- refresh command to the drams. in this state, the drams perform refresh cycles on their own without any additional commands or ac tivity from the memory controller or the interface. as long as power to the drams is maintained, the memory contents are retained. 5.17.2.4 pmc control under s3, s4, and s5 power management states, all working domain circuits, as well as the geode gx proces- sor, are turned off to conserve power. under s3, the sys- tem memory is powered by v io_vsb in standby auto- refresh mode but otherwise, all other system components are also turned off. the pmc is used to establish overall system power states. normally, the standby domain voltages are present any- time the system is plugged into the wall; if portable, any- time the battery is plugged in. generally, g3 mechanical off (see table 5-34 on page 172) only applies during stor- age or maintenance. therefore, operationally speaking, the pmc standby controller is always available to manage power. there is a class of system designs that do not require g1 and g2 global power states. these systems usually power-up working and standby power domains simultaneously when power is applied. for supporting ?save-to-ram? (g1/s3) the working out- put is used to switch off/on the working domain sources for system memory while the work_aux output is used to switch off/on the working domain sources for everything else. thus, the pmc can comp letely control the system power states via these outputs. 174 amd geode? cs5535 companion device data book power management control 31506b 5.17.3 software power management actions the hardware comes up from hardware system reset in the full on (fo) state. as part of system initialization, the power management msrs (see section 6.18.1 on page 496) are written to establish the active hardware clock gating (ahcg) state. the ahcg state is the nominal oper- ational state. 5.17.3.1 sleep/standby sequence entering the states under g1 and g2 requires explicit soft- ware action. that action star ts a hardware chain of events in which some of the chain is determined by registers that must be programmed previous to the start of the sequence. the block diagram of the hardware involved in this sequence is illustrated in figure 5-53. figure 5-54 and fig- ure 5-55 graphically show the sleep/standby sequence. the sequence is as follows: 1) the ?explicit software action? begins with a write to pm1_cnt (acpi i/o offset 08h) starting the sleep/standby sequence. 2) the pmc issues a sleep request to the geode cs5535 companion device glcp and it passes the request as susp# to the geode gx processor?s glcp. 3) the geode gx processor?s glcp issues a suspend request to the processor. after the processor has shut- down operation it provides a suspend acknowledge back to the geode gx processor?s glcp. 4) the geode gx processor?s glcp processes a sleep sequence similar to that described in step 5 while issu- ing a suspa# to the geode cs5535 companion device glcp. figure 5-53. pmc power management elements gliu activity counters geodelink? device (1 of n) pm msr glcp dsmi, smi, nmi, irq susp# suspa# processor clock control turn off pci/ide inputs turn off pci/ide outputs external i/o sleep request sleep acknowledge internal wakeup events external wakeup and thermal events including buttons sleep_x, sleep_y, slp_clk_en#, working, and work_aux system reset if wakeup from standby power low indicator pml & reset (with standby power) notes: *at least one per geodelink? device. #global signal, one per system. (cis packet) amd geode? cs5535 companion device data book 175 power management control 31506b 5) the geode cs5535 companion device glcp pro- cesses a sleep sequence. this is done in one of the three ways: a) if the clk_dly_en bit in glcp_glb_pm (msr 5170000bh[1]) is 0 and the clk_delay value in the glcp_clk_dis_delay (msr 51700008h[23:0]) is 0, then wait until the clk_active flags specified in glcp_clk4ack (msr 51700013h[33:0]) have gone to 0. b) if the clk_dly_en bit is 1 and the clk_delay value is non-zero, then wait the amount of time of the clk_delay value. c) if the clk_dly_en is 0 and the clk_delay value is non-zero, then wait as in (a) but no longer than (b). 6) at the completion of the wait above, de-assert the clk_dis bits specified in glcp_pmclkdisable (msr 51700009h[33:0]) and assert sleep acknowl- edge to the pmc. 7) when the sleep acknowledge is received, the pmc can optionally issue additional external generic con- trols sleep_x and sleep_y as well as slp_clk# to turn off external clocks. the completion of this step takes the system to s1. the system is now in sleep. 8) if the sleep request was to enter s3 (save-to-ram) then the pmc moves beyond s1 and removes main power by de-asserting work_aux and leaving working asserted. working is used to power main memory, while work_aux is used for every- thing else in the system. 9) if the sleep request was to enter s4 (save-to-disk) or s5 (soft off) then the pmc moves beyond s1 and removes main power by de-asserting both work_aux and working. 10) an external or internal wakeup event reverses the events above to bring the system back to the s0 state. figure 5-54. pmc system sleep sequence sleep request susp# suspa# gl device clock control sleep acknowledge pci/ide input control sleep_x/sleep_y pci/ide output control slp_clk_en# indicates a variable delay. note: external signals are not necessarily active high. shown as active high for clarity. slp_clk_en# signal must be the last control to assert because it turns off all system clocks. 176 amd geode? cs5535 companion device data book power management control 31506b figure 5-55. pmc system wakeup sequence sleep request susp# suspa# gl device clock control sleep acknowledge pci/ide input control sleep_x/sleep_y pci/ide output control slp_clk_en# sleep_x/sleep_y controls should de-assert between pci/ide input and output controls. indicates a variable delay. note: external signals are not necessarily active high. shown as active high for clarity. slp_clk_en# de-asserts at wakeup event and turns on system clocks. wakeup sequence begins with a sleep wakeup event. amd geode? cs5535 companion device data book 177 power management control 31506b 5.17.3.2 sleep controls sleep request/sleep acknowledge handshake (see figure 5-53 on page 174) between the glcp and pmc controls the transitions into and out of the sleep and standby states. the pmc starts the sleep sequence by asserting sleep request to the glcp. the glcp requests the pro- cessor to enter c2 by asserting the susp# signal. when suspa# from the processor is received, the glcp informs the internal geodelink devices of a pending shutdown and waits until the geodelink devi ces? clock control indicates that they are ready. the length of time it takes for each device to respond is programmable (glcp msr 51700008h, 51700013h, and 5170000bh). after all desig- nated geodelink devices have responded, the glcp asserts sleep acknowledge to the pmc. the pm_in_slpctl (pms i/o offset 20h) register and the pm_out_slpctl (pms i/o offse t 0ch) are used to dis- able pci/ide inputs and outputs respectively during sleep. generally, they are asserted at the end of a sleep sequence and de-asserted at the beginning of a wakeup sequence. when ?disabled?, some of the outputs are forced to tri-state with an active internal pull-down resistor while the rest are simply pulled low. see section 4.8.5 "msr address 4: power management" on page 78 for specific details on pci/ide i/o controls during sleep. 5.17.3.3 power controls in response to sleep acknowledge from the glcp, the pmc can assert five controls/enables: sleep_x, sleep_y, slp_clk_en#, working, and work_aux. these can control external electronic power switches and enables. each control?s assertion and de-assertion is sub- ject to an enable and a programmable delay (pms i/o off- set 04h to 3ch). controls sleep_x and sleep_y are generic and have no specific use. asserting control slp_clk_en# is assumed to turn off the system (board) clocks. it is always de- asserted by the wakeup event. the following conditions apply to the timing of selected output control (see section 5.17.3.2 "sleep controls "), sleep_x, sleep_y and slp_clk_en#. when going to sleep: a) if not enabled, sleep_x and sleep_y do not assert at all. if they are enabled, the delay should be set to occur between the delays programmed in the pm_in_slpctl and pm_out_slpctl registers. b) if slp_clk_en# is enabled, any delays associated with the pm_out_slpctl, sl eep_x, and sleep_y regis- ters must be less than the slp_clk_en# delay. c) if slp_clk_en# is enabled, then sleep wakeup is pos- sible only after slp_clk_en# asserts. d) if slp_clk_en# is not enabled, and if at least one of the following pm_out_slpctl, sleep_x, or sleep_y registers is enabled, then sleep wakeup is possible only after the longest delay of the three. the delays could be zero. e) if slp_clk_en# is not enabled, and the pm_out_slpctl, sleep_x, or sleep_y registers are not enabled, then sleep wakeup is possible immediately. f) if slp_clk_en# is enabled and the delay associated with the pm_out_slpctl register is longer than or equal to the delay associated with slp_clk_en#, then the pci/ide outputs will not be disabled. if enabled, the de-assertion of working is assumed to remove working power and all clock sources except 32 khz; that is, the sta ndby state is entered. in this state, the pmc, disables its interface to all circuits connected to working power and asserts reset_out# before de- assertion of working. reset_out# remains asserted throughout standby. work_aux is an auxiliary control for the standby state with no specific use. it can be de-asserted any time before or after working. working and work_aux are independent controls, but the use of either implies t hat standby state is to be entered. in both cases, the pmc disables all circuits con- nected to working power and asserts reset. however, since they are independent, one may be left on while the other is de-asserted. 178 amd geode? cs5535 companion device data book power management control 31506b 5.17.3.4 wakeup events if the system has been put to sleep, only preprogrammed wakeup events can get the system running again. the pmc contains the controls that allow the system to respond to the selected wakeup events. on wakeup from sleep (not standby, but sleep wakeup) (see figure 5-53 on page 174), the pmc immediately de- asserts slp_clk_en# to turn system clocks back on. it also re-enables pci/ide outputs to allow output drivers to return to their operational levels. next it de-asserts sleep_x and sleep_y based on programmable delays. alternate sleep_x and sleep_y interactions are shown as dotted lines. lastly, the pmc, re-enables pci/ide inputs after a programmable delay and de-asserts sleep request. the glcp starts any on-chip plls and waits for them to become stable. then the glcp de-asserts susp# to the processor. when the processor de-asserts suspa#, the glcp de-asserts sleep acknowledge. the pmc allows the wakeup event to a ssert a system control inter- rupt (sci). after a wakeup event: a) pci/ide outputs are re-enabled after slp_clk_en# is de-asserted. b) pci/ide inputs are re-enabled at sleep wakeup or after a programmable delay. generally, pci/ide inputs are nor- mally used with a delay and that delay is longer than any de-assertion delay associated with sleep_x and/or sleep_y. re-enabling pci/ide inputs is generally not useful at the beginning of a wakeup sequence. c) sleep request is de-asserted at sleep wakeup or after a programmable delay. sleep request is kept de-asserted until the pci/ide inputs are re-enabled. generally, the enable and delay values in pm_sed (pms i/o offset 14h) and pm_in_slpctl (pms i/o offset 20h) should always be the same. d) if used, sleep_x/sleep_y delay should be set to occur between the delays programmed in pm_out_slpctl (pms i/o offset 0ch) and pm_in_slpctl (pms i/o offset 20h). if the delays for sleep_x/sleep_y are longer than the pm_in_slpctl delay, then sleep_x/sleep_ y de-assert at the same time as the pci/ide inputs are re-enabled. on wakeup from standby (not sleep, but standby wakeup) the pmc asserts working and performs a sys- tem reset. reset_out# is de- asserted after a program- mable delay and the normal software start-up sequence begins. however, early in the sequence, the software checks the pmc state to determine if waking from standby (pms i/o offset 54h[ 0]). if yes, then the system state is potentially restored from non-volatile storage. if enabled, work_aux may be asserted before or after reset_out# is de-asserted. 5.17.3.5 fail-safe power off the pmc provides the support logic to implement an acpi compliant fail-safe power off bu tton. this logic uncondition- ally de-asserts the working and work_aux signals if the on/off button is held down for a programmable delay. for acpi compliance, this dela y should be set to four sec- onds. 5.17.3.6 wake events status and sci when enabled, a wake event from the general wake events register (see section 6.16.4 "gpio interrupt and pme registers" on page 479) set its status bit and the ?wak_sts? bit and causes a system control interrupt (sci). the sleep button, rtc alarm, and power button when asserted, always set th eir status bit. they set the ?wak_sts? bit and generate an sci only when their enable bit is set. when overflowed, the pm timer sets its status bit. this overflow condition does not cause a wakeup event but if enabled, it generates an sci. the event?s status is cleared by writing a one to it. 5.17.4 pmc power management states the pmc state machines support the fundamental hard- ware states: power off, reset standby, working, sleep, and controlled standby. reset standby state: from power off, reset is applied to the standby domain by the external input pin reset_stand# or through the low volt age detect (lvd) circuit. once reset, and the skip feature is not enabled, the reset standby state de-asserts working and work_aux outputs and waits for a reset standby wakeup event. if the skip feature is enabled, the state machine will proceed to the working state immediately. to enable skip, see the signal description for the pwr_but# in table 3-9 "gpiox available functions descriptions" starting on page 49. working state: the working state c an be entered from reset standby, sleep, or controlled standby states. working state is established when working power is applied and all system clocks are enabled. once in this state, registers and function s in the pmc can be initial- ized, programmed, enabled/disabled, and the potential exists for the system to proc eed to the sl eep state or standby state. sleep state: the system initiates the entry to the sleep state with a sleep sequence. under the sleep state, working and standby power are maintained. pci/ide inputs are disabled when sleep acknowledge asserts. pci/ide outputs are disabled when sleep acknowledge asserts or after a programmable delay. sleep_x, sleep_y, and slp_clk_en# may be asserted if enabled. a sleep wakeup event returns the system to working state. amd geode? cs5535 companion device data book 179 power management control 31506b controlled standby state: can be entered ?normally?, ?fault condition?, or by a ?restart?. a normal entry is by way of a system initiated sequence as in the sleep case. this method of entry requires the standby state machine to monitor slp_clk_en# and look for an enable of the ?working de-assert delay and enable? register (pm_wkd, pms i/o offset 30h[30]) or the work_aux de-assert delay and enable register (pm_wkxd, pms i/o offset 34h[30]). this signals the controlled standby state normal entry. a standby wakeup event returns the system to working state after a program- mable delay (pm_nwkd, pms i/o offset 4ch). if enabled, a faulted entry can be initiated by a low power off, thermal off, or fail-safe off. it can also be initiated by working power fail asserted. a default wakeup event returns the system to the work ing state afte r a programma- ble delay (pm_fwkd, pms i/o offset 50h). if a power loss occurs and power is restored, the system can be returned to the working state automatically by soft- ware setting the pi (power immediate bit, read, cleared, and set through pms i/o offset 54h[18:16]). the pi bit is powered by the rtc block, so it remains valid as long as v bat remains connected. pi behaves similarly to skip. a re-start can be initiated by any of these resets: glcp soft reset, soft re set, shutdown reset, watchdog reset, or bad packet type reset. the syst em returns to the working state when reset is de-asserted and the faulted_to_work delay (pm_fwkd) expired. working and work_aux are not de-asserted. when a controlled standby state is entered by a faulted condition or restart event, software control is assumed lost and the software established state is assumed to be poten- tially wrong. therefore, the st andby domain returns to the state associated with ?standby state entry from power off?; that is, standby domain reset defaults are used. the only exceptions are registers from the following list; these are locked and not subject to change by software: pm_rd de-assert reset delay from standby (pms i/o offset 38h) pm_wkxa work_aux assert delay from standby (pms i/o offset 3ch) pm_fsd fail-safe delay and enable (pms i/o offset 40h) pm_tsd thermal safe delay and enable (pms i/o offset 44h) pm_psd power safe delay and enable (pms i/o offset 48h) pm_nwkd normal to work delay and enable (pms i/o offset 4ch) pm_fwkd faulted to work delay and enable (pms i/o offset 50h) the faulted to work delay and enable (pm_fwkd) regis- ter is the only one of the ab ove registers that potentially applies during a re-start entry. lastly, note that any normal entry operation in process is aborted. wakeup from faulted entry is the same as that associated with standby state entry from po wer off; that is, it acts as if the power button has been pushed. other possible wakeup events such as rtc alarm and pmes are ignored. however, the system can be he ld in the standby state for the following reasons: 1) if enabled and locked, low_bat# is still asserted. 2) if lvd_en# is tied to ground and v core is not at a valid voltage, or if reset_work # is asserted. note: if enabled and locked, the thermal alarm does not keep the system in the standby state if it is asserted. the thermal alarm circuitry resides in the working domain, and its state is ignored by the standby state. once out of standby, the thermal alarm again comes into play. if it is still asserted, its timer would start again. the power management control (pmc) has two state machines: working state machine: operates under working power and runs on a 14 mhz clock from the ccu. its function is to generate control signals used to turn off/on systems clocks and i/os based on events coming from on or off the chip. standby state machine: operates under standby power and runs on the 32 khz clock. its function is to power-up and down the working power to the working domain based on events coming from on or off the chip. 180 amd geode? cs5535 companion device data book power management control 31506b 5.17.5 pmc power management events a large number of inputs to the pmc are used to monitor and create system power managements events. some of these inputs apply the working state machine while the remainder apply to the standby state machine. 5.17.5.1 pm sleep events sleep: ? sleep sequence initiated by software wakeup: ? assertion of the sleep button (sleep_but) ? assertion of the power button (pwr_but#) ?rtc alarm ? working power domain pmes ? standby power domain pmes 5.17.5.2 pm standby events standby: ? sleep sequence initiated by software ? lvd detection of low voltage on v core (system fault) ? assertion of the power button for 4 seconds (pwr_but#, system fault) ? thermal alarm (thrm_alrm#, system fault) ? low battery (low_bat#, system fault) ? hardware reset (system restart) ? software initiated reset (system restart) ? shutdown initiated reset, cpu triple fault (system restart) ? watchdog initiated reset (system restart) ? glcp software initiated reset (system restart) ? bad packet type reset (system restart) ? reset standby state machine reset_stand# (standby) wakeup: ? assertion of the power button (pwr_but#) ?rtc alarm ? standby power domain pmes table 5-35 provides a complete list of the power manage- ment inputs and describes their function. the system can only be in one of three states : working, sleep, or standby. the activity of the inputs is to move the system from one state to another. table 5-35. pm events and functions event current state function the following events are sleep and/or standb y wakeup events (except for acpi timer). pwr_but# (also serves as a standby event) working sets the status bit (pwrbtn_sts) in pm1_sts (acpi i/o offset 00h[8] = 1). if pwrbtn_en is enabled (acpi i/o offset 02h[8] = 1), an sci is generated. sleep sets the status bit (p wrbtn_sts) in pm1_sts (acpi i/o offset 00h[8] = 1). if pwrbtn_en is enabled (acpi i/o offset 02h[8] = 1), sci generation and wakeup from this event is enabled (i.e., sets the wak_sts bit, acpi i/o offset 00h[15] = 1). standby sets the status bit (p wrbtn_sts) in pm1_sts (acpi i/o offset 00h[8] = 1). if pwrbtn_en is enabled (acpi i/o offset 02h[8] = 1), sci generation and wakeup from this event is enabled (i.e., sets the wak_sts bit, acpi i/o offset 00h[15] = 1). slp_btn working sets the status bit (slpbtn_st s) in pm1_sts (acpi i/o offset 00h[9] = 1). if slpbtn_en is enabled (acpi i/o offs et 02h[9] = 1), an sci is generated. sleep sets the status bit (slpbtn_sts) in pm1_sts (acpi i/o offset 00h[9] = 1). if slpbtn_en is enabled (acpi i/o offset 02h[9] = 1), sci generation and wakeup from this event is enabled (i.e., sets the wak_sts bit, acpi i/o offset 00h[15] = 1). rtc alarm working sets the status bit (rtc_sts ) in pm1_sts (acpi i/o offset 00h[10] = 1). if rtc_en is enabled (acpi i/o offset 02h[10] = 1), an sci is generated. sleep sets the status bit (rtc_sts) in pm1_sts (acpi i/o offset 00h[10] = 1). if rtc_en is enabled (acpi i/o offset 02h[10] = 1), sci generation and wakeup from this event is enabled (i.e., sets the wak_sts bit, acpi i/o offset 00h[15] = 1). standby sets the status bit (rtc_sts) in pm1_sts (acpi i/o offset 00h[10] = 1). if rtc_en is enabled (acpi i/o offset 02h[10] = 1), sci generation and wakeup from this event is enabled (i.e., sets the wak_sts bit, acpi i/o offset 00h[15] = 1). acpi timer (internal timer) working sets the status bit (tmr_sts) in pm1_sts (acpi i/o offset 00h[0] = 1). if tmr_en is enabled (acpi i/o offset 02h[0] = 1), an sci is generated. amd geode? cs5535 companion device data book 181 power management control 31506b gpe[23:0] (general purpose power manage- ment events in working domain) working if gpe_en[23:0] are enabled (acpi i/o offset 1ch[23:0] = 1), the corresponding status bit (gpe_sts[23:0]) in gpe0_sts (acpi i/o offset 18h[23:0]) is set and an sci is generated. sleep if gpe_en[23:0] are enabled (acpi i/o offset 1ch[23:0] = 1), sci generation and wakeup from the event is enabled (i.e., sets the wak_sts bit, acpi i/o offset 00h[15] = 1). gpe[31:24] (general purpose power manage- ment events in standby domain) working if gpe_en[31:24] are enabled (acpi i/o offset 1ch[31:24] = 1), the corresponding status bit (gpe_st s[31:24]) in gpe0_sts (acpi i/o offset 18h[23:0]) is set and an sci is generated. sleep if gpe_en[31:24] are enabled (acpi i/o offset 1ch[23:0] = 1), sci generation and wakeup from the event is enabled (i.e., sets the wak_sts bit, acpi i/o offset 00h[15] = 1). standby if gpe_en[31:24] are enabled (acpi i/ o offset 1ch[31:24] = 1), the corresponding status bit (gpe_sts[31:24]) in gpe0_sts (acpi i/o offset 18h[23:0]) is set, and sci generation and wakeup from the event is enabled (i.e., sets the wak_sts bit, acpi i/o offset 00h[15] = 1). the following events caused a standby state entry. reset_stand# working if asserted, the corresponding stat us bit (off_flag) in pm_ssc (pms i/o offset 54h[0]) is set and causes a reset standby state entry. no working or standby power. sleep if asserted, the corresponding status bi t (off_flag) in pm_ssc (pms i/o offset 54h[0]) is set and causes a reset standby state entry. no working or standby power. standby if asserted in restart, or normal or fa ulted standby state, the corresponding status bit (off_flag) in pm_ssc (pms i/o offs et 54h[0]) is set and causes a reset standby state entry. lvd circuit detects low voltage on v core working if de-asserted, the status bit (lvd_flag) in pm_ssc (pms i/o offset 54h[2]) is set and causes an faulted standby state entry. working power is turned-off. sleep if de-asserted, the status bit (lvd_flag) in pm_ssc (pms i/o offset 54h[2]) is set and causes an faulted standby state entry. working power is turned-off. standby if de-asserted in restart state, the st atus bit (lvd_flag) in pm_ssc (pms i/o off- set 54h[2]) is set and causes an faulted standby state entry. pwr_but# working if enabled and asserted for four seconds (fail-safe), the status bit (pwrbut_flag) in pm_ssc (pms i /o offset 54h[3]) is set and causes an faulted standby state entry. working power is turned-off. sleep if enabled and asserted for four seconds (fail-safe), the status bit (pwrbut_flag) in pm_ssc (pms i /o offset 54h[3]) is set and causes an faulted standby state entry. working power is turned-off. standby if enabled and asserted for four seconds (fail-safe) while in normal or restart state, the status bit (pwrbut_flag) in pm_ssc (pms i/o offset 54h[3]) is set and causes a faulted standby state entry. thrm_alrm# working if enabled and asserted for a programmable amount of time, the status bit (thrm_flag) in pm_ssc (pms i/o offset 54h[4]) is set and causes an faulted standby state entry. working power is turned-off. sleep if enabled and asserted for a programmable amount of time, the status bit (thrm_flag) in pm_ssc (pms i/o offset 54h[4]) is set and causes an faulted standby state entry. working power is turned-off. standby ignored. table 5-35. pm events and functions (continued) event current state function 182 amd geode? cs5535 companion device data book power management control 31506b low_bat# working if enabled and asserted for a programmable amount of time, the status bit (lowbat_flag) in pm_ssc (pms i/o offset 54h[5]) is set and causes an faulted standby state entry. working power is turned-off. sleep if enabled and asserted for a programmable amount of time, the status bit (lowbat_flag) in pm_ssc (pms i/o offset 54h[5]) is set and causes an faulted standby state entry. working power is turned-off. standby if asserted in normal or re-start state, the status bit (lowbat_flag) in pm_ssc (pms i/o offset 54h[5]) is set an d causes a faulted state entry. reset_work# working if asserted, the status bit (hrd_r st_flag) in pm_ssc (pms i/o offset 54h[6]) is set and causes a restart state entry . working power is not turned-off. sleep if asserted, the status bit (hrd_rst_fla g) in pm_ssc (pms i/o offset 54h[6]) is set and causes a restart state entry . working power is not turned-off. software initiated reset working if asserted, the status bit (sft_rst_f lag) in pm_ssc (pms i/o offset 54h[8]) is set and causes a restart state entry . working power is not turned-off. sleep if asserted, the status bit (sft_rst_fla g) in pm_ssc (pms i/o offset 54h[8]) is set and causes a restart state entry . working power is not turned-off. shutdown initiated reset (cpu triple fault) working if asserted, the status bit (shtdw n_rst_flag) in pm_ssc (pms i/o offset 54h[9]) is set and causes a re-start state entry. working power is not turned-off. sleep if asserted, the status bit (shtdwn_ rst_flag) in pm_ssc (pms i/o offset 54h[9]) is set and causes a restart stat e entry. working power is not turned-off. watchdog initiated reset working if asserted, the status bit (watchdo g_rst_flag) in pm_ssc (pms i/o offset 54h[10]) is set and causes a restart stat e entry. working power is not turned-off. sleep if asserted, the status bit (watchdog_ rst_flag) in pm_ssc (pms i/o offset 54h[10]) is set and causes a restart stat e entry. working power is not turned-off. glcp soft reset working if asserted, the status bi t (glcp_sft_rst_flag) in pm_ssc (pms i/o offset 54h[11]) is set and causes a restart stat e entry. working power is not turned-off. sleep if asserted, the status bit (glcp_sft_rst_flag) in pm_ssc (pms i/o offset 54h[11]) is set and causes a restart stat e entry. working power is not turned-off. bad packet type reset working if asserted, the status bit (badpack _rst_flag) in pm_ssc (pms i/o offset 54h[12]) is set and causes a restart stat e entry. working power is not turned-off. sleep if asserted, the status bit (badpack _rst_flag) in pm_ssc (pms i/o offset 54h[12]) is set and causes a restart stat e entry. working power is not turned-off. table 5-35. pm events and functions (continued) event current state function amd geode? cs5535 companion device data book 183 flash controller 31506b 5.18 flash controller the geode cs5535 companion device has a flash device interface that supports popular nor flash and inexpen- sive nand flash devices. this interface is shared with the ide interface (ata-5 controller (atac)), using the same balls. nor or nand flash may co-exist with ide devices using pio (programmed i/o) mode. the 8-bit interface supports up to four ?lanes? of byte-wide flash devices through use of four independent chip selects, and allows for booting from the array. hardware support is present for smartmedia-type ecc (error correction code) calcula- tions, off-loading software from having to support this task. if flash and ide are both operational, an external pull-up (10k) to ide_dreq0 (ball a14) is required and ide_dreq0 must not be connected to the ide device. to switch modes, explicit software actions must occur to dis- able one and enable the other. features supports popular nor flash and inexpensive nand flash devices on ide interface. no extra pins needed. nor flash and nand flash co-exist with ide devices with pio (programmed i/o) only mode. general purpose chip select pins support on-board isa- like slave devices. programmable timing supports a variety of flash devices. supports up to four byte-wide nor flash devices. ? address up to 256 kb boot roms using an external octal latch. ? address up to 256 mb linear flash memory arrays using external latches. ? boot rom capability. ? burst mode capability (dword read/write on pci bus). supports up to four byte-wide nand flash devices. ? hardware support for smartmedia-type ecc (error correction code) calculation off-loading software effort. supports four programmable chip select pins with memory or i/o addressable. ? up to 1 kb of address space without external latch. 5.18.1 nand flash controller to understand the functioning of the nand flash control- ler, an initialization sequence and a read sequence is pro- vided in the following sub-sections. the nand flash controller?s registers can be mapped to memory or i/o space. the following example is based on memory mapped registers. 5.18.1.1 initialization 1) program msr_lbar_flsh0 (msr 51400010h) to establish a base address (nand_start) and whether in memory or i/o space. the nand controller is memory mapped in this example and always occu- pies 4 kb of memory space. 2) set the nand timing msrs to the appropriate values (msrs 5140001bh and 5140001ch). 5.18.1.2 read 1) allocate a memory buffer. start at address bah in sys- tem memory. 2) fill the buffer with the following values: ? ba: 02h (assert ce#, cle) ? ba + 1: 00h (command: read mode) ? ba + 2: 04h (assert ce#, ale, de-assert cle) ? ba + 3: ca (start column address) ? ba + 4: 04h ? ba + 5: pa0 (page address byte 0) ? ba + 6: 04h ? ba + 7: pa1 (page address byte 1) ? ba + 8: 04h ? ba + 9: pa2 (page address byte 2) ? ba + 10: 08h (assert ce#, de-assert ale, enable interrupt) 3) for (i = 0; i < 11; i++), write the data in buffer [ba+i] to memory location [nand_start + 800h + i]. gener- ate the command and address phase on the nand flash interface. 184 amd geode? cs5535 companion device data book flash controller 31506b 4) nand flash device may pull down the rdy/busy# signal at this point. software sets the en_int bit and waits for the interrupt. 5) memory byte writes 03h to memory location [nand_start + 815h] to clear ecc parity and enable ecc engine. 6) for (i = 0; i < 256; i++), read data from [nand_start + i] to buffer [ba + i] (read data from nand flash to memory buffer. can use dword read to save time). 7) memory dword reads [nand_start + 810h] to get ecc parity [ecc0] of first 256 byte data. 8) memory byte writes 03h to memory location [nand_start + 815h] to clear ecc parity and enable ecc engine. 9) for (i = 256; i < 512; i++), read data from [nand_start + i] to buffer [ba + i] (read data from nand flash to memory buffer. can use dword read to save time). 10) memory dword reads [nand_start + 810h] to get ecc parity [ecc1] of second 256 byte data. 11) for (i = 512; i < 528; i++), read data from [nand_start + i] to buffer [ba + i] (read data from nand flash redundant data to memory buffer. can use dword read to save time). 12) write 01h to memory location [nand_start + 800h] (de-assert ce#, nand flash enters to idle state). 13) retrieve ecc parity data from redundant data area and compare them to ecc0 and ecc1. 14) correct data if data error is detected and can be fixed. figure 5-56 on page 184 shows a basic nand read cycle. figure 5-56. flash cont roller nand read cycle cle ce# we# ale re# i/o r/b# d0 d1 d2 d (n-1) pa2 pa1 pa0 ca 00h amd geode? cs5535 companion device data book 185 flash controller 31506b 5.18.1.3 nand ecc control module the nand ecc control module is part of the nand flash controller. it calculates 22-bit ecc parity for each of the 256 bytes of the nand flash?s data transferred on the local bus. the ecc calculation algorithm follows the smartmedia physical format specification . the ecc algo- rithm is capable of single-bit correction and 2-bit random- error detection. eccs are generated only for data areas and no ecc is generated for page-data redundant areas containing eccs as the page -data redundant area is dupli- cated for reliability. for ecc calculations, 256 bytes are handled as a stream of 2048-bi t serial data. in the event of an error, the error-correction feature can detect the bit location of the error based on the results of a parity check and correct the data. hardware operation the ecc engine treats 256-byte data as a block. each byte has an 8-bit address called a line address (la). each bit in a byte has a 3-bit address called a column address (ca). combining these two address fields forms an 11-bit unique address for every single bit in the 256-byte data block. the address uses the notation: llll_llll, ccc. this module contains an 8-bit counter to keep track of the la of each byte. each ecc parity bit calculation in the ecc engine produces even parity of half of the data bits in the block. different parity bits use different sets of the bits. for example, cp0 is the even parity bit of the bits with col- umn address bit 0 equals 0. cp1 is the even parity bit of the bits with column address bit 0 equals 1. both odd and even parity are supported for ecc. the ecc parity avail- able in the nand ecc column, lsb line, and msb line parity registers is the inverted output of the ecc parity from the ecc engine in the case of odd ecc parity and the non- inverted output in the case of even parity. table 5-36 lists the relationship between the parity bits and the corre- sponding bit addresses. the hardware ecc engine calcu- lates 22-bit ecc parity whenever there is a data write or data read to/from the nand flash device. on power-up, the ecc engine is configured to be odd parity. even or odd ecc parity is controlled by bit 2 of nand ecc control reg- ister (flash memory offset 815h). table 5-36. ecc parity/bit address relationship parity bit address cp0 xxxx_xxxx, xx0 cp1 xxxx_xxxx, xx1 cp2 xxxx_xxxx, x0x cp3 xxxx_xxxx, x1x cp4 xxxx_xxxx, 0xx cp5 xxxx_xxxx, 1xx lp00 xxxx_xxx0, xxx lp01 xxxx_xxx1, xxx lp02 xxxx_xx0x, xxx lp03 xxxx_xx1x, xxx lp04 xxxx_x0xx, xxx lp05 xxxx_x1xx, xxx lp06 xxxx_0xxx, xxx lp07 xxxx_1xxx, xxx lp08 xxx0_xxxx, xxx lp09 xxx1_xxxx, xxx lp10 xx0x_xxxx, xxx lp11 xx1x_xxxx, xxx lp12 x0xx_xxxx, xxx lp13 x1xx_xxxx, xxx lp14 0xxx_xxxx, xxx lp15 1xxx_xxxx, xxx 186 amd geode? cs5535 companion device data book flash controller 31506b software operation the nand flash contains a redundant data area contain- ing ecc fields. while writing to the nand flash, the hard- ware ecc engine calculates ecc parity, if it is enabled properly. software can write the ecc parity bits to the ecc field after writing the data area. when software reads the data from nand flash, the hardware ecc engine calcu- lates ecc parity. after the data is read from the nand flash, software can compare the ecc parity in the hard- ware ecc engine and the ecc parity in the ecc field of the nand flash to determine if the data block is correct. each data bit has 11 corresponding parity bits, which can be determined by the bit address. if one data bit is different from its original value, 11 ecc parity bits are changed from the original ecc parity bits. take the ecc parity from the hardware ecc engine and perform bit-wise exclusive or with it and the ecc parity field in nand flash. the result can be as follows. 1) all bits are 0. the data is correct. 2) eleven bits are 1. one bit error has been detected. use the eleven bits to identify the error bit position. 3) one bit is 1. one bit in ecc field is corrupt. data area should be ok. 4) otherwise, two or more data bits are corrupt. cannot be corrected. 5.18.2 nor flash controller/general purpose chip select the nor flash controller supports up to four independent chip selects that can be used for nor flash devices or general purpose chip selects (gpcs). up to 28 bits of address is supported for each chip select, allowing byte- wide linear arrays up to 256 mb in memory space. chips selects may also be located in i/o space, but the usable address bits are limited by the over all limits of i/o space. each chip select is independently programmable: address setup: defaults to seven local bus clocks read/write strobe width: defaults to seven local bus clocks address hold: defaults to seven local bus clocks cycles optional wait state insertion: defaults off, driven by an external input (flash_iochrdy) to be used by general purpose devices. optional write protect: defaults protected these settings are located in msr space and on hard reset default to the settings listed above. hence, virtually any nor device can be used immediately out of reset for first instruction fetch. after booting, delays can be pro- grammed as appropriate. special considerations must be made for nor flash write operations. depending on the manufacturer and write mode, each write can take from a few microseconds to a few hundred microseconds. specifically, the software per- forming the write must observe the following procedure: 1) write to device. 2) wait an amount of time dependent on manufacturer?s specifications. 3) repeat from #1 until all writes are completed. the ?wait? in step two is implemented using an appropriate time base reference. there is no reference within the flash controller subsystem. some nor devices provide a ready line that de-asserts during the ?wait? in step two. direct use of this signal is not supported by the flash controller. the nor write software should use an appropriate ti me base reference to deter- mine when the device is ready, that is, determine how long to wait for the current write to complete before starting another write. alternatively, the nor device internal status may be read to determine when the write operation is com- plete. refer to nor flash manufactures data sheets for additional write operation details. amd geode? cs5535 companion device data book 187 flash controller 31506b 5.18.3 flash controller interface timing diagrams 5.18.3.1 nor/gpcs the nor/gpcs timing has two phases: address phase and data phase. in the address phase, the address bus and data bus present a higher address, add[27:10]. board designers can use external latches, such as 74x373, to latch the address bits. in the data phase, the addre ss bus presents add[9:0], and the data bus is for data read or write. the flash controller is running off internal local bus clock, which is at the highest frequency of 33 mhz. the address phase is always two clock periods. the ale signal asserts high in the first-half clock period and de-asserts in the sec- ond clock period. a 74lcx373 only needs 4 ns setup time and 2 ns hold time (worst case). this timing provides a lot of flexibility for the designing of the board. in the data phase, the address bus and write data bus are available in the first clock period. in the second clock period of the data phase, chip select goes low. after the required hold time, chip select goes high, and write data bus change. after one local bus clock from chip select change (going high), address bus changes. the setup time, strobe pulse width, and hold time are programmable through the nor timing registers. see section 6.19.1.2 "nor flash timing msrs" on page 522. figure 5-57 and figure 5-58 provides some nor flash timing examples. figure 5-57. nor flash basic timing add[9:0] ale cs# we#, re# data (write) data (read) 01234xyy+1y+2zz+1z+2 address phase data phase tp ts th ts th data higher address higher address data ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? higher address lower address 188 amd geode? cs5535 companion device data book flash controller 31506b figure 5-58. nor flash with wait states timing add[9:0] ale cs# we#, re# data (write) data (read) 01234xyy+1y+2zz+1z+2 address phase data phase tp ts th ts th data higher address higher address data ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? wait states ? ? ? ? don?t care don?t care iochrdy ? ?? higher address lower address amd geode? cs5535 companion device data book 189 flash controller 31506b 5.18.3.2 nand the nand flash interface has three external timings that are controlled by nine timing registers. the timing parameters are described in table 5-37 and illustrated in figures 5-59 through 5-61. figure 5-59. nand flash command/address timing table 5-37. nand flash external timing parameters symbol description tcs control setup time: the setup time from the toggl e of the control signals to the falling edge of we#. tcp control pulse width: the we# active pulse width in the command/address phase. note that the command/address byte is put on the i/o bus at the same time that the we# is asserted. tch control hold time: the hold time from the rising edge of we# to the toggle of the control signals. note that the i/o bus is turn ed off when the tch expires. tws data write setup time: this timing is just for the internal state machine; no external reference point. can be set to 0 if the setup time is not needed. twp data write pulse width: the we# active pulse width in the data write phase. note that the data byte is put on the i/o bus at the same time that we # is asserted; no external reference point. can be set to 0 if the hold time is not needed. trp data read pulse width: the re# acti ve pulse width in the data read phase. trh data read hold time: this timing is just for the internal state machine; no external reference point. can be set to 0 if the hold time is not needed. tcs tch tcp tch command / address 012 xx+1yzz+1 ? ? ? ? ? ? ? ? ? we# 3 4 z+2 ctlr_busy i/o[7:0] ? ? ? note: ctlr_busy is bit 2 of the nand st atus register (flash memory offse t 810h or flash i/o offset 06h). 190 amd geode? cs5535 companion device data book flash controller 31506b figure 5-60. nand data timing with no wait states and no prefetch (for the first data read) figure 5-61. nand data ti ming with wait states tws / trs twp / trp twh / trp 0123xyy+1zz+1z+2 ? ? ? ? ? ? ? ? ? ? ? ? ? we# / re# i/o [7:0] (write) i/o [7:0] (read) tws / trs twp / trp twh / trh 0123xyy+1zz+1z+2 ? ? ? ? ? ? ? ? ? ? ? ? ? we# / re# i/o [7:0] (write) i/o [7:0] (read) ? ?? ? ? ? wait state flash_rdy/busy# amd geode? cs5535 companion device data book 191 geodelink? control processor 31506b 5.19 geodelink? control processor the geodelink? control processor (glcp) functionality is illustrated in figure 5-62 and is summarized as: serial to geodelink conversion to facilitate jtag accesses to geod elink devices power management support (reset and clock control) msrs together with a jtag controller, the glcp provides com- plete visibility of the register st ate that the chip is in. all reg- isters are accessible via the jtag interface. how the jtag controller interfaces with the glcp is beyond the scope of this document and is not explained here. the glcp also works with the ccu (clock control unit) blocks of other geodelink devices to provide clock control via its relevant msrs. the glcp supplies the clock enable signals to all the ccus , allowing clocks to be shut off if the power management logic generates a sleep request or if a debug event triggers a clock disable situation. figure 5-62. glcp block diagram 5.19.1 geodelink? power management support the main power management functions are performed by the power management logic, with the glcp playing a supporting role. (see section 5.17 "power management control" on page 172 for a complete understanding of power management.) 5.19.1.1 soft reset this is one of the active high soft reset sources going to the power management logic. it resides in the glcp_sys_rst register. when ac tive, all circuitry in the geode cs5535 companion device is reset (including the glcp_sys_rst register itself). 5.19.1.2 clock control the glcp provides a mechanism to shut off clocks. the busy signal from a module can control the clock gating in its ccu, however, clocks can also be enabled or disabled by the functional clock enable signals coming from the glcp. these enable signals are asynchronous to the modules and need to be synchronized in the ccu blocks before being used to enable or disable the functional clocks. the clocks can be disabled in one or a combination of the three ways below. all the msrs mentioned can be found in section 6.18 "power management controller register descriptions" on page 494 and section 6.20 "geodelink? control processor register descriptions" on page 531. 1) the power management circuitry disables the clocks when going into sleep. the sleep sequence is started by the assertion of sleep request from the power management logic. the glcp asserts sleep request and waits for the assertion of sleep acknowledge, which indicates that the clocks should be disabled. there are two ways to do this: a) if sleep acknowledge is asserted and the clock dis- able delay period has expired, disable the clocks spec- ified in glcp_pmclkdisable (msr 51700009h). each bit in glcp_pmclkdisable corresponds to a ccu, and when set, indicates that the clock going to that ccu should be disabled during a sleep sequence. the clock disable delay period is specified by the clk_delay bits in glcp_clk_dis_delay (msr 51700008h), and is enabled by the clk_dly_en bit in glcp_glb_pm (msr 5170000bh). it is clocked by the pci functional clock. serial to gl conversion msr registers power management support pci interface req req data data tap controller pci clock geodelink? interface out in out in 192 amd geode? cs5535 companion device data book geodelink? control processor 31506b b) if sleep acknowledge is asserted and the clock dis- able delay period is not enabled, check to see if all clocks specified by glcp_clk4ack (msr 51700013h) have become inactive. if glcp_clkactive (msr 51700011h) shows that those clocks are indeed inactive, disable the clocks specified in glcp_pmclkdisable (msr 51700009h). sleep acknowledge is asserted after the clocks have been disabled. the wakeup sequence is triggered by the de-assertion of the sleep request, which turns on all the clocks. 2) if a debug event in the debug circuitry triggers a clock disable, disable all the clocks specified in glcp_clkdisable. each glcp_clkdisable bit corresponds to a ccu, and when set, indicates that the clock going to that ccu should be disabled. 3) each bit in glcp_clkoff (msr 51700010h) corre- sponds to a ccu. when set, the bit indicates that the clock going to that ccu should be disabled. this is the simplest case. 5.19.2 glcp clocks the glcp has multiple clock domains, namely the geodelink clock and pci clock. the geodelink clock is the clock source for the msrs, the serial interface, and the geodelink interface. the pci clock is used in the power management support for the clock disable delay timer. both the geodelink and pci functional clocks come from primary inputs. all these clocks are handled by a ccu. even though the pci clock is always running in functional mode, a ccu is needed to be able to perform reset syn- chronization and to turn off the internal clock to support tapscan. the ccus used by the glcp are the asyn- chronous versions, since the glcp outputs asynchronous busy signals. amd geode? cs5535 companion device data book 193 tap controller 31506b 5.20 tap controller the tap controller is ieee 1149.1 compliant. a block dia- gram of the tap, boundary scan and internal scan is shown in figure 5-63. the jtag pins tck, tdi, tdo, tms, and reset_stand# are directly supported. the tap is programmable by means of tap control instruc- tions. the meanings of the various instructions are shown in table 5-38 on page 194 along with the length of the dr (data register) that can be a ccessed once the instruction is entered. all data registers shift in and out data lsb first. the instruction register and al l data registers are shift reg- isters, so if more bits are shifted in than the register can hold, only the last bits shift ed in - the msbs - will be used. this can be useful on systems t hat always shift in a multi- ple of 8 bits to the data or instruction registers. the instruction register is 24 bits wide and defined in table 5- 39 on page 195. the tap controller can be initialized synchronously or asynchronously. for a synchronous reset, holding tms high and clocking tck a minimum of five times will put the tap state machine into the test-logic-reset state. asyn- chronous reset is available too by asserting reset_stand# (tap controller reset) (see section 4.6 "reset considerations" on page 65). from reset_stand#, the tap state machine will immediately enter the test-logic-reset state. the tap has specific pre-assigned meanings to the bits in the 24-bit ir register. the meanings are summarized in table 5-39. note that the bits only affect the chip once the ?update-ir? jtag state occurs in the jtag controller - shifting through these bits will not change the state of inter- nal signals (e.g., test_mode). the details on jtag control- ler states are covered in the ieee 1149.1 standard. features tap control/access to the following: shift/capture of ccu scan chain gliu access via request-in, request-out packets tapscan access tri-state mode control memory bist control id code configures component for jtag bypass mode figure 5-63. tap controller, boundary scan block diagram internal scan registers boundary scan registers from bscan ta p to bscan tdi tdo tck tms serial interface with glcp memory bist interface from iscan to iscan reset_stand# or lvd standby reset 194 amd geode? cs5535 companion device data book tap controller 31506b table 5-38. tap controller instructions instruction dr length ir name description 000000h and ffffe8h 240 extest boundary scan ring. ieee 1149.1 specif ication compliant. (mapped twice in ir address space.) 01fffah through 1dfffah variable tapscan[0:28] tap scan chain 0 through chain 28. these are parts of the internal scan chain subdivided according to a common ccu clock. 01ffffh through 1dffffh 1 tapfunc[0:28] tap function chain 0 through chain 28. one capture cycle applied to the individual ccu scan chain clocked by the func- tional clock. 81fffah 70 gl_addr geodelink address. access geodelink request packet and data packet control bits. 83fffah 66 gl_data geodelink data. access geodelink data. 85fffah 4 padacc pad access. padtestmode for access to analog and memory bist signals. 87fffah 24 progmisr program instruction. this instruction provides direct access to an msr used for the rom memory bist test. not supported. 8bfffah 70 gl_addr_act geodelink address action. same data register as gl_addr, but no geodelink transactions are triggered by the access - only by glcp debug action. 8dfffah -- tst_iddq test iddq. put chip in a mode for running iddq tests. 8ffffah 8 revid revision id. the tap instruction used to access the current revision code (8 bits) for the chip. ffffdfh 1 tristate tri-state. put chip into tri-state and comparison mode. fffffdh 21 bistdr parallel ram bist. internal data register (for chip test). fffffeh 32 idcode id code. 0fe1101fh for the geode cs5535 companion device. msb lsb id[31:28] id27 id[12:11] id[1:0] version part number manuf. id 1 ffffffh 1 bypass bypass. ieee 1149.1 specification requires all 1s to be bypassed. amd geode? cs5535 companion device data book 195 tap controller 31506b table 5-39. tap controller instruction bits bit name description 23 tapscan tap scan. (also user[6].) this is a user bit added by amd. low indicates that an inter- nal scan chain will be accessed by the tap. 22:17 user[5:0] user bits 5 through 0. user bits used to identify an internal scan chain or, if bit 23 is high, to access a special internal dr. 16 bistenable[3] bist enable bit 3. works in conjunction with bits [9:7]. see bits [9:7] description for decode. 15:10 rsvd reserved. should always be high. 9:7 bistenable[2:0] bist enable bits 2 through 0. works in conjunction with bit 16. 0000: bisten12 0010: bisten11 0100: bisten10 0110: bisten9 0001: bisten8 0011: bisten7 0101: bisten6 0111: bisten5 1000: bisten4 1010: bisten3 1100: bisten2 1110: bisten1 1011: bisten0 1001: does nothing [normally used for logic bist] 1101: parallel scan 1111: scan through tap 6 rsvd reserved. should always be high. 5 forcedis force disable. active low bit that places all output pins in tri-state mode. see tristate for details. 4 selectjtagout select jtag output. active low bit that allows boundary scan cells to control pads. 3 selectjtagin select jtag output. active low bit that allows boundary scan cells to drive data into core logic of chip. 2:0 op[2:0] operation bits 2 through 0. selects for how the jtag chains are wired together. 000: tdi -> boundary scan -> tdo 001: tdi -> boundary scan -> internal scan -> device id -> bypass -> tdo 010: tdi -> internal scan -> tdo 011: tdi -> boundary scan -> internal scan -> device id -> bypass -> tdo 100: tdi -> internal scan -> tdo 101: tdi -> internal data register -> tdo 110: tdi -> device id -> tdo 111: tdi -> bypass -> tdo 196 amd geode? cs5535 companion device data book tap controller 31506b 5.20.1 extest the extest instruction a ccesses the boundary scan chain around the chip and controls the pad logic such that the boundary scan data will control the data and enable signals for the pads. ieee 1149.1 requires that an all-zero instruction access the boundary scan chain. 5.20.2 tapscan these instructions enable jtag access to the internal scan associated with a particular ccu clock. tck will then provide the scan clock to the ccu so that shifting occurs correctly during the shift-dr state of the tap. (see figure 5-64 and figure 5-65.) 5.20.3 tapfunc these instructions connect tdi and tdo to the 1-bit bypass register during dr access. they are useful in that during the capture-dr state, one functional clock can be applied to the specific ccu clock indicated by the instruc- tion. this mode works well with the fs2 jtag control soft- ware available with geode cs5535 companion device. the scan enable signal to the block will be inactive during this clock. figure 5-64. tap controller and parallel scan mode test mode = 1 scan in scan out pad pad geodelink? device tap scan in pad amd geode? cs5535 companion device data book 197 tap controller 31506b figure 5-65. tap controller and tapscan mode scan in[0] scan out[0] scan out[1] scan in[1] test mode = 0 tap_inst[23] = 0 select pad pad geodelink? device ta p tdo tdi tdo 198 amd geode? cs5535 companion device data book tap controller 31506b 5.20.4 gl_addr this register contains 53 bi ts for a geodelink? control packet and the 17 bits for a geodelink data packet. the 17 bits from the data packet are updated if a geodelink read is requested and is available for shifting out. the gl_data description discusses the various conditions under which a valid request packet is posted to the internal geodelink. note that sinc e only one gl_addr request packet can be sequenced in with jtag, the special ?read with byte enable? 2-packet requests that geodelink sup- ports cannot be triggered. of course, 8, 16, 32, and 64-bit reads can still be performed and reads of less than 64-bit sizes will generate the appropriate byte enables at the device. as with geodelink traffic, reads of less than 64 bits must be to an aligned address, but the data will return in the gl_data adjusted to 64-bit alignment (i.e., a 16-bit read to address 102h should have address bit 1 set and data will return in bits [31:16] of the 64-bit response). writes of less than 64 bits must always have 64-bit aligned addresses and should use the byte enables in the data packet (part of the gl_addr data register) to identify which specific bytes are to be written. 5.20.5 gl_data the data transfer rate in and out of the jtag port is limited to about 90% of the tck frequency by the glcp design. the glcp is designed for up to 50 mhz tcks, but typical tck rates for industry interfaces are about 15 mhz. as such, the glcp jtag data rate is 14 mbits/sec or 1.6 mbytes/sec. again, however, industry interface boxes will limit this rate to about 500 kbytes/sec. geodelink requests packets are triggered at these specific moments: if gl_addr has been accessed more recently than gl_addr_act and... ? the type of the request is a read and the update-dr jtag state is entered after loading the gl_addr register. ? the type of the request is a write and the update- dr jtag state is entered after loading the gl_data register. ? the type of the request is a read and the second tck in the shift-dr state for shifting out the gl_data register is received and the first two bits shifted in (gl_data dr bits 1 and 0) are non-zero and the first bit shifted out was non-zero. if gl_addr_act register has been accessed more recently than gl_addr and... ? the glcp debug logic triggers the geodelink_action due to a debug event occurring. note that if both msr accesses from the gliu and jtag accesses are interfacing to thes e registers, the results will be non-deterministic. 5.20.6 padacc provides a test mode whereby usb interface signals or memory bist signals can be accessed by input/output pads. this access is accomplished by writing to the auxil- iary test register. 5.20.7 progmisr this instruction provides direct access to an msr used for the rom memory bist test. at the conclusion of the test, the resulting signature is then checked. a correct test will result in mbist_go being logic-high. 5.20.8 mb_addr_act this is the same data register as gl_addr, but it disables any geodelink transaction from occurring either on this access or a following access to the gl_data register. only the glcp debug action that triggers a geodelink cycle will cause these bits to be used. 5.20.9 tst_iddq places the chip in a mode for running iddq tests (i.e., gen- erates an internal signal to disable pull-ups and pull downs). also the transceiver is powered off. 5.20.10 revid the tap instruction used to access the current 8-bit revi- sion code of the chip. 5.20.11 tristate this instruction will tri-state all of the tri-statable pri- mary outputs. the dr acce ssed is the bypass register. 5.20.12 bistdr can be used to run all memory bist controllers in parallel. 5.20.13 idcode this instruction accesses the 32-bit idcode register dur- ing dr access. 5.20.14 bypass in the ieee 1149.1 specification, shifting all 1s into the ir must connect the 1-bit bypass register. the register has no function except as a storage flip-flop. this instruction can also allow relatively easy connection of multiple glcp jtag interface chips. on a board with two glcp chips, tms and tck of each chip should be wired together and tdo of one chip should connect to tdi of the other chip. note: in parallel scan mode, ?input? pads provide data into the boundary scan cells (the boundary scan cells provide data into the core). ?cowrie? pads will behave as dictated by the internal core flops that normally control the pad; the output data and enable state will be latched into the boundary scan cells. ?cheroot? pads will drive out data as dictated by the internal core flop associated with the pad. amd geode? cs5535 companion device data book 199 6 register descriptions 31506b 6.0 register descriptions this chapter provides detailed information regarding the registers of the amd geode? cs5535 companion device. the register descriptions ar e documented at the module- level and briefly summarized below. geodelink? interf ace unit (gliu) standard geodelink? device (gld) msrs: accessed via rdmsr and wrmsr instructions. p2d descriptor msrs: accessed via rdmsr and wrmsr instructions. (memory base descriptor.) gliu specific msrs: accessed via rdmsr and wrmsr instructions. iod descriptor msrs: accessed via rdmsr and wrmsr instructions. (i/o base descriptor.) geodelink pci south bridge (glpci_sb) standard geodelink? device (gld) msrs: accessed via rdmsr and wrmsr instructions. glpci_sb specific msrs: accessed via rdmsr and wrmsr instructions. pci configuration registers: index accessed via pci configuration cycle. audio codec 97 controller (acc) standard geodelink? device (gld) msrs: accessed via rdmsr and wrmsr instructions. acc native registers: accessed as i/o offsets from a gliu iod descriptor. ata5 controller (atac) standard geodelink? device (gld) msrs: accessed via rdmsr and wrmsr instructions. atac specific msrs: accessed via rdmsr and wrmsr instructions. atac native registers: accessed as i/o offsets from a gliu iod descriptor. universal serial bus co ntrollers (usbc1, usbc2) standard geodelink device (gld) msrs: accessed via rdmsr and wrmsr instructions. usb specific msrs: accessed via rdmsr and wrmsr instructions. usb embedded pci configuration registers: accessed via rdmsr and wrmsr instructions. also requires gliu p2d descriptor. host controller native registers: accessed via a base address register at usb pci index 10h as memory offsets. diverse integration logic (divil) standard geodelink? device (gld) msrs: accessed via rdmsr and wrmsr instructions. divil specific msrs: accessed via rdmsr and wrmsr instructions. floppy port standard geodelink device msrs: accessed via rdmsr and wrmsr instructions. (shared with divil.) floppy port specific msrs: accessed via rdmsr and wrmsr instructions. programmable interval timer (pit) standard geodelink device msrs: accessed via rdmsr and wrmsr instructions. (shared with divil.) pit specific msrs: accessed via rdmsr and wrmsr instructions. pit native registers: accessed as i/o addresses. programmable interrupt controller (pic) standard geodelink device msrs: accessed via rdmsr and wrmsr instructions. (shared with divil.) pic specific msrs: accessed via rdmsr and wrmsr instructions. pic native registers: ac cessed as i/o addresses. keyboard emulation logic (kel) standard geodelink device msrs: accessed via rdmsr and wrmsr instructions. (shared with divil.) kel specific msrs: accessed via rdmsr and wrmsr instructions. kel native registers: accessed via a base address register, msr_lbar_kel1 (msr 51400009h) and/or msr_lbar_kel2 (msr 5140000ah), as memory offsets. system management bus (smb) standard geodelink device msrs: accessed via rdmsr and wrmsr instructions. (shared with divil.) smb native registers: accessed via a base address register, msr_lbar_smb (msr 5140000bh), as i/o offsets. 200 amd geode? cs5535 companion device data book register descriptions 31506b universal asynchronous receiver-transmitter (uart) standard geodelink device msrs: accessed via rdmsr and wrmsr instructions. (shared with divil.) uart/ir controller specific msrs: accessed via rdmsr and wrmsr instructions. uart/ir controller native registers: accessed via banks 0 through 7 as i/o offsets. see msr_leg_io (msr 51400014h) bits [22:20] and bits [18:16] for setting base address. direct memory access (dma) standard geodelink device msrs: accessed via rdmsr and wrmsr instructions. (shared with divil.) dma specific msrs: accessed via rdmsr and wrmsr instructions. dma native registers: accessed as i/o addresses. low pin count (lpc) standard geodelink device msrs: accessed via rdmsr and wrmsr instructions. (shared with divil.) lpc specific msrs: accessed via rdmsr and wrmsr instructions. real-time clock (rtc) standard geodelink device msrs: accessed via rdmsr and wrmsr instructions. (shared with divil.) rtc specific msrs: accessed via rdmsr and wrmsr instructions. rtc native registers: accessed as i/o addresses. general purpose input output (gpio) standard geodelink device msrs: accessed via rdmsr and wrmsr instructions. (shared with divil.) gpio native registers: accessed via a base address register, msr_lbar_gpio (msr 5140000ch), as i/o offsets. ? gpio low/high bank feature bit registers ? gpio input conditioni ng function registers ? gpio interrupt and pme registers multi-function general purpose timer (mfgpt) standard geodelink device msrs: accessed via rdmsr and wrmsr instructions. (shared with divil.) mfgpt specific msrs: accessed via rdmsr and wrmsr instructions. mfgpt native registers: accessed via a base address register, msr_lbar_mfgpt (msr 5140000dh), as i/o offsets. power management controller (pmc) standard geodelink device msrs: accessed via rdmsr and wrmsr instructions. (shared with divil.) pmc specific msrs: accessed via rdmsr and wrmsr instructions. acpi registers: accessed via a base address register, msr_lbar_acpi (msr 5140000eh), as i/o offsets. pm support registers: accessed via a base address register, msr_lbar_pms (msr 5140000fh), as i/o offsets. flash controller standard geodelink device msrs: accessed via rdmsr and wrmsr instructions. (shared with divil.) flash controller specific msrs: accessed via rdmsr and wrmsr instructions. flash controller native registers: accessed via a base address register as either memory or i/o offsets: ? msr_lbar_flsh0 (msr 51400010h) for use with flash_cs0#. ? msr_lbar_flsh1 (msr 51400011h) for use with flash_cs1#. ? msr_lbar_flsh2 (msr 51400012h) for use with flash_cs2#. ? msr_lbar_flsh3 (msr 51400013h) for use with flash_cs3#. geodelink control processor (glcp) standard geodelink? device (gld) msrs: accessed via rdmsr and wrmsr instructions. glcp specific msrs: accessed via rdmsr and wrmsr instructions. note that msrs for the floppy port, pit, pic, kel, smb, uart, dma, lpc, rtc, gpio, mfgpt, and flash con- troller modules are part of the divil (i.e., msr 51400000h- 514000ffh). hence, the standard geodelink device msrs (msr 51400000h-51400007h) are documented in the divil register description and the device specific msrs are documented in their appropriate register description chapter. the tables in this chapter use the following abbreviations: type description r/w read/write. r read from a specific address returns the value of a specific register. write to the same address is to a different register. wwrite. ro read only. wo write only. r/w1c read/write 1 to clear. writing 1 to a bit clears it to 0. writing 0 has no effect. amd geode? cs5535 companion device data book 201 geodelink? interface unit register descriptions 31506b 6.1 geodelink? interface un it register descriptions the geodelink? interface unit (gliu) registers are model specific registers (msrs) a nd are accessed through the rdmsr and wrmsr instructions. the msr address is derived from the perspective of the cpu core. see section 4.2 "msr addressing" on page 59 for more details. the msrs are split into the following groups: standard geodelink device (gld) msrs p2d descriptor msrs gliu specific msrs iod descriptor msrs tables 6-1 through 6-4 are gliu register summary tables that include reset values and page references where the bit descriptions are provided. reserved (rsvd) fields do not have any meaningful stor- age elements. they always return 0. table 6-1. standard geodelink? device msrs summary msr address type register name reset value reference 51010000h ro gld capabilities msr (gliu_gld_msr_cap) 00000000_000010xxh page 204 51010001h r/w gld master configuration msr (gliu_gld_msr_config) 0000000_00000004h page 204 51010002h r/w gld smi msr (gliu_gld_msr_smi) 00000000_00000001h page 205 51010003h r/w gld error msr (gliu_gld_msr_error) 00000000_00000001h page 206 51010004h r/w gld power management msr (gliu_gld_msr_pm) 00000000_00000000h page 208 51010005h r/w gld diagnostic msr (gliu_gld_msr_diag) 00000000_00000000h page 208 51010006h- 5101000fh r/w gliu reserved msrs (gld_msrs_rsvd) 00000000_00000000h --- table 6-2. p2d descriptor msrs summary msr address type register name reset value reference 51010020h r/w p2d base mask descriptor 0 (gliu_p2d_bm0) 000000ff_fff00000h page 209 51010021h r/w p2d base mask descriptor 1 (gliu_p2d_bm1) 000000ff_fff00000h page 209 51010022h r/w p2d base mask descriptor 2 (gliu_p2d_bm2) 000000ff_fff00000h page 209 51010023h r/w p2d base mask kel descriptor 0 (gliu_p2d_bmk0) 000000ff_fff00000h page 210 51010024h r/w p2d base mask kel descriptor 1 (gliu_p2d_bmk1) 000000ff_fff00000h page 210 51010025h- 5101003fh r/w p2d reserved descriptors (p2d_rsvd) 00000000_00000000h --- 202 amd geode? cs5535 companion device data book geodelink? interface unit register descriptions 31506b table 6-3. gliu specific msrs summary msr address type register name reset value reference 51010080h r/w coherency (gliu_coh) 00000000_00000000h page 211 51010081h r/w port active enable (gliu_pae) 00000000_0000ffffh page 211 51010082h r/w arbitration (gliu_arb) 00000000_00000000h page 212 51010083h r/w asynchronous smi (gliu_asmi) 00000000_00000000h page 212 51010084h r/w asynchronous error (gliu_aerr) 00000000_00000000h page 213 51010085h r/w debug (gliu_debug) 00000000_00000004h page 214 51010086h ro physical capabilities (gliu_phy_cap) 327920a0_80000003h page 215 51010087h ro n outstanding response (gliu_nout_resp) 00000000_00000000h page 216 51010088h ro number of outstanding write data (gliu_nout_wdata) 00000000_00000000h page 216 51010089h- 5101008ah r/w reserved (rsvd) 00000000_00000000h --- 5101008bh ro who am i (gliu_whoami) configuration dependent page 216 5101008ch r/w slave disable (gliu_slv_dis) 00000000_00000000h page 217 5101008dh- 5101008fh r/w reserved (rsvd) 00000000_00000000h --- 510100a0h wo descriptor statistic counter 0 (gliu_statistic_cnt0) 00000000_00000000h page 218 510100a1h r/w descriptor statistic mask 0 (gliu_statistic_mask0) 00000000_00000000h page 219 510100a2h r/w descriptor statistic action 0 (gliu_statistic_action0) 00000000_00000000h page 220 510100a3h r/w reserved (rsvd) 00000000_00000000h --- 510100a4h wo descriptor statistic counter 1 (gliu_statistic_cnt1) 00000000_00000000h page 218 510100a5h r/w descriptor statistic mask 1 (gliu_statistic_mask1) 00000000_00000000h page 219 510100a6h r/w descriptor statistic action 1 (gliu_statistic_action1) 00000000_00000000h page 220 510100a7h r/w reserved (rsvd) 00000000_00000000h --- 510100a8h wo descriptor statistic counter 2 (gliu_statistic_cnt2) 00000000_00000000h page 218 510100a9h r/w descriptor statistic mask 2 (gliu_statistic_mask2) 00000000_00000000h page 219 510100aah r/w descriptor statistic action 2 (gliu_statistic_action2) 00000000_00000000h page 220 510100abh- 510100bfh r/w reserved (rsvd) 00000000_00000000h --- 510100c0h r/w request compare value (gliu_rq_comp_val) 001fffff_ffffffffh page 221 510100c1h r/w request compare mask (gliu_rq_comp_mask) 00000000_00000000h page 222 amd geode? cs5535 companion device data book 203 geodelink? interface unit register descriptions 31506b 510100c2h- 510100cfh r/w reserved (rsvd) 00000000_00000000h --- 510100d0h r/w data compare value low (gliu_da_comp_val_lo) 00001fff_ffffffffh page 222 510100d1h r/w data compare value high (gliu_da_comp_val_hi) 0000000f_fffff fffh page 223 510100d2h r/w data compare mask low (gliu_da_comp_mask_lo) 00000000_00000000h page 223 510100d3h r/w data compare mask high (gliu_da_comp_mask_hi) 00000000_00000000h page 224 510100d4h- 510100dfh r/w reserved (rsvd) 00000000_00000000h --- table 6-4. iod descriptor msrs summary msr address type register name reset value reference 510100e0h r/w iod base mask 0 (gliu_iod_bm0); reserved for ata-5; defaults to 1fx 16 . 60000000_1f0ffff0h page 225 510100e1h r/w iod base mask 1 (gliu_iod_bm1) 000000ff_fff00000h page 225 510100e2h r/w iod base mask 2 (gliu_iod_bm2) 000000ff_fff00000h page 225 510100e3h r/w iod base mask 3 (gliu_iod_bm3) 000000ff_fff00000h page 225 510100e4h r/w iod base mask 4 (gliu_iod_bm4) 000000ff_fff00000h page 225 510100e5h r/w iod base mask 5 (gliu_iod_bm5) 000000ff_fff00000h page 225 510100e6h r/w iod base mask 6 (gliu_iod_bm6) 000000ff_fff00000h page 225 510100e7h r/w iod base mask 7 (gliu_iod_bm7) 000000ff_fff00000h page 225 510100e8h r/w iod base mask 8 (gliu_iod_bm8) 000000ff_fff00000h page 225 510100e9h r/w iod base mask 9 (gliu_iod_bm9) 000000ff_fff00000h page 225 510100eah r/w iod swiss cheese 0 (gliu_iod_sc0) 60000000_403003f0h page 226 510100eah r/w iod swiss cheese 0 (gliu_iod_sc0); reserved for ata-5; defaults to 3f6 16 . 60000000_403003f0h page 226 510100ebh r/w iod swiss cheese 1 (gliu_iod_sc1) 00000000_00000000h page 226 510100ech r/w iod swiss cheese 2 (gliu_iod_sc2) 00000000_00000000h page 226 510100edh r/w iod swiss cheese 3 (gliu_iod_sc3) 00000000_00000000h page 226 510100eeh r/w iod swiss cheese 4 (gliu_iod_sc4) 00000000_00000000h page 226 510100efh r/w iod swiss cheese 5 (gliu_iod_sc5) 00000000_00000000h page 226 510100f0h r/w iod swiss cheese 6 (gliu_iod_sc6) 00000000_00000000h page 226 510100f1h r/w iod swiss cheese 7 (gliu_iod_sc7) 00000000_00000000h page 226 510100f2h- 510100ffh r/w reserved (rsvd) 00000000_00000000h --- table 6-3. gliu specific msrs summary (continued) msr address type register name reset value reference 204 amd geode? cs5535 companion device data book geodelink? interface unit register descriptions 31506b 6.1.1 standard geodelink? device (gld) msrs 6.1.1.1 gld capabilities msr (gliu_gld_msr_cap) 6.1.1.2 gld master configurat ion msr (gliu_gld_msr_config) msr address 51010000h ty p e r o reset value 00000000_000010xxh gliu_gld_msr_cap register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd dev_id rev_id gliu_gld_msr_cap bit descriptions bit name description 63:24 rsvd reserved. reads return 0. 23:8 dev_id device id. identifies module (0010h). 7:0 rev_id revision id. identifies module revision. see amd geode? cs5535 companion device specification update for value. msr address 51010001h ty p e r / w reset value 0000000_00000004h gliu_gld_msr_config register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd subp gld_msr_config bit descriptions bit name description 63:3 rsvd reserved. write as read. 2:0 subp subtractive port. for all negative decode requests. 000: port 0 (gliu) 100: port 4 (dd) 001: port 1 (glpci_sb) 101: port 5 (acc) 010: port 2 (usbc2) 110: port 6 (usbc1) 011: port 3 (atac) 111: port 7 (glcp) note: the reset value of this register should not be changed. amd geode? cs5535 companion device data book 205 geodelink? interface unit register descriptions 31506b 6.1.1.3 gld smi msr (gliu_gld_msr_smi) the flags are set by internal conditions. the internal conditions are enabled if the en bit is 0. reading the flag bit returns the value; writing 1 clears the flag; writ ing 0 has no effect. (see section 4.8.3 "msr address 2: smi control" on page 74 for further smi and asmi generation details.) msr address 51010002h ty p e r / w reset value 00000000_00000001h gliu_gld_msr_smi register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd statcnt2_asmi_flag statcnt1_asmi_flag statcnt0_asmi_flag ssmi_flag 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd statcnt2_asmi_en statcnt1_asmi_en statcnt0_asmi_en ssmi_en gliu_gld_msr_smi bit descriptions bit name description 63:36 rsvd reserved. write as read. 35 statcnt2_ asmi_flag statistic counter 2 asmi flag. if high, records that an asmi was generated due to a statistic counter 2 (msr 510100a8h) event. write 1 to clear; writing 0 has no effect. statcnt2_asmi_en (bit 3) must be low to generate asmi and set flag. 34 statcnt1_ asmi_flag statistic counter 1 asmi flag. if high, records that an asmi was generated due to a statistic counter 1 (msr 510100a4h) event. write 1 to clear; writing 0 has no effect. statcnt1_asmi_en (bit 2) must be low to generate asmi and set flag. 33 statcnt0_ asmi_flag statistic counter 0 smi flag. if high, records that an asmi was generated due to a sta- tistic counter 0 (msr 510100a0h) event. writ e 1 to clear; writing 0 has no effect. statcnt0_asmi_en (bit 1) must be low to generate asmi and set flag. 32 ssmi_flag ssmi flag. if high, records that an ssmi was generated due to a received event. event sources are: illegal request type to gliu (port 0), meaning anything other than msr read/write, debug request, and null. a self-referencing packet (i.e., a packet sent to the gliu that finds its destination port is the source port). the destination of the packet is to a port where the gliu slave for that port has been disabled. trap on a descriptor with device port set to 0. this is the typical operational use of this bit. the data returned with such a trap is the value 0. write 1 to clear; writing 0 has no effect. ssm i_en (bit 0) must be low to generate ssmi and set flag. 31:4 rsvd reserved. write as read. 206 amd geode? cs5535 companion device data book geodelink? interface unit register descriptions 31506b 6.1.1.4 gld error msr (gliu_gld_msr_error) the flags are set by internal conditions. the internal conditions are enabled if the en bit is 0. reading the flag bit returns the value; writing 1 clears the flag; writing 0 has no effect. (see section 4.8.4 "msr address 3: error control" on page 78 for further details.) 3 statcnt2_ asmi_en statistic counter 2 asmi enable. write 0 to enable statcnt2_asmi_flag (bit 35) and to allow a statistic counter 2 (msr 510100a8h) event to generate an asmi. 2 statcnt1_ asmi_en statistic counter 1 asmi enable. write 0 to enable statcnt1_asmi_flag (bit 34) and to allow a statistic counter 1 (msr 510100a4h) event to generate an asmi. 1 statcnt0_ asmi_en statistic counter 0 asmi enable. write 0 to enable statcnt0_asmi_flag (bit 33) and to allow a statistic counter 0 (msr 510100a0h) event to generate an asmi. 0 ssmi_en ssmi enable. write 0 to enable ssmi_flag (bit 32) and to allow a received ssmi event to generate an ssmi. (see bit 32 description for ssmi event sources.) msr address 51010003h ty p e r / w reset value 00000000_00000001h gliu_gld_msr_error register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd dacmp_err_flag rsvd rqcomp_err_flag rsvd statcnt2_err_flag statcnt1_err_flag statcnt0_err_flag ssmi_err_flag unexp_add_err_flag unexp_type_err_flag 313029282726252423222120191817161514131211109876543210 rsvd dacmp_err_en rsvd rqcomp_err_en rsvd statcnt2_err_en statcnt1_err_en statcnt0_err_en ssmi_err_en unexp_add_err_en unexp_type_err_en gliu_gld_msr_error bit descriptions bit name description 63:44 rsvd reserved. write as read. 43 dacomp_ err_flag data comparator error flag. if high, records that an err was generated due to a data comparator (da_comp_val_lo / da_com p_val_hi, msr 510100d0h / 510100d1h) event. write 1 to clear; writing 0 has no effect. dacomp_err_en (bit 11) must be low to generate err and set flag. 42:40 rsvd reserved. write as read. gliu_gld_msr_smi bit descriptions (continued) bit name description amd geode? cs5535 companion device data book 207 geodelink? interface unit register descriptions 31506b 39 rqcomp_ err_flag request comparator error flag. if high, records that an err was generated due to a request comparator 0 (rq_comp_val, msr 510100c0h) event. write 1 to clear; writ- ing 0 has no effect. rqcomp_err_en (bit 7) must be low to generate err and set flag. 38 rsvd reserved. write as read. 37 statcnt2_ err_flag statistic counter 2 error flag. if high, records that an err was generated due to a sta- tistic counter 2 (msr 510100a8h) event. writ e 1 to clear; writing 0 has no effect. statcnt2_err_en (bit 5) must be low to generate err and set flag. 36 statcnt1_ err_flag statistic counter 1 error flag. if high, records that an err was generated due to a sta- tistic counter 1 (msr 510100a4h) event. writ e 1 to clear; writing 0 has no effect. statcnt2_err_en (bit 4) must be low to generate err and set flag. 35 statcnt0_ err_flag statistic counter 0 error flag. if high, records that an err was generated due to a sta- tistic counter 0 (msr 510100a4h) event. writ e 1 to clear; writing 0 has no effect. statcnt0_err_en (bit 3) must be low to generate err and set flag. 34 ssmi_err_ flag ssmi error flag. if high, records that an err was generated due an unhandled ssmi (synchronous error). write 1 to clear; writing 0 has no effect. ssmi_err_en (bit 2) must be low to generate err and set flag. (note 1) 33 unexp_add_ err_flag unexpected address error flag. if high, records that an err was generated due an unexpected address (synchronous error). writ e 1 to clear; writing 0 has no effect. unexp_add_err_en (bit 1) must be low to generate err and set flag. (note 1) 32 unexp_type _err_flag unexpected type error flag. if high, records that an err was generated due an unex- pected type (synchronous error). write 1 to clear; writing 0 has no effect. unexp_type_err_en (bit 0) must be low to generate err and set flag. (note 1) 31:12 rsvd reserved. write as read. 11 dacomp_ err_en data comparator error enable. write 0 to enable dacomp_err_flag (bit 43) and to allow a data comparator (da_comp_val_lo / da_comp_val_hi, msr 510100d0h / 510100d1h) event to generate an err and set flag. 10:8 rsvd reserved. write as read. 7rqcomp_ err_en request comparator error enable. write 0 to enable rqcomp_err_flag (bit 39) and to allow a request comparator (rq_comp_val, msr 510100c0h) event to generate an err. 6 rsvd reserved. write as read. 5 statcnt2_ err_en statistic counter 2 error enable. write 0 to enable statcnt2_err_flag (bit 37) and to allow a statistic counter 2 (msr 510100a8h) event to generate an err. 4 statcnt1_ err_en statistic counter 1 error enable. write 0 to enable statcnt1_err_flag (bit 36) and to allow a statistic counter 1 (msr 510100a4h) event to generate an err. 3 statcnt0_ err_en statistic counter 0 error enable. write 0 to enable statcnt0_err_flag (bit 35) and to allow a statistic counter 0 (msr 510100a0h) event to generate an err. 2 ssmi_err_ en ssmi error enable. write 0 to enable ssmi_err_flag (bit 34) and to allow the unhan- dled ssmi (synchronous error) event to generate an err. 1 unexp_add_ err_en unexpected address error enable. write 0 to enable unexp_add_err_flag (bit 33) and to allow the unexpected address (synchronous error) event to generate an err. 0 unexp_type _err_en unexpected type error enable. write 0 to enable unexp_ type_err_flag (bit 32) and to allow the unexpected type (synchronous error) event to generate an err. note 1. these are synchronous errors, that is, they do not result in the assertion of the gl error signal but instead set the exception bit in the response packet. gliu_gld_msr_error bit descriptions (continued) bit name description 208 amd geode? cs5535 companion device data book geodelink? interface unit register descriptions 31506b 6.1.1.5 gld power manageme nt msr (gliu_gld_msr_pm) 6.1.1.6 gld diagnostic msr (gliu_gld_msr_diag) this register is reserved for internal use by amd and should not be written to. msr address 51010004h ty p e r / w reset value 00000000_00000000h gliu_gld_msr_pm register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd pmode1 pmode0 gliu_gld_msr_pm bit descriptions bit name description 63:4 rsvd reserved. write as read. 3:2 pmode1 power mode 1. statistics and time slice counters. 00: disable clock gating. clocks are always on. 01: enable active hardware clock gating. clock goes off whenever this module?s circuits are not busy. 10: reserved. 11: reserved. 1:0 pmode0 power mode 0. online gliu logic. 00: disable clock gating. clocks are always on. 01: enable active hardware clock gating. clock goes off whenever this module?s circuits are not busy. 10: reserved. 11: reserved. msr address 51010005h ty p e r / w reset value 00000000_00000000h amd geode? cs5535 companion device data book 209 geodelink? interface unit register descriptions 31506b 6.1.2 p2d descriptor msrs 6.1.2.1 p2d base mask descriptors (gliu_p2d_bm[x]) p2d base mask descriptor 0 (gliu_p2d_bm0) p2d base mask descriptor 1 (gliu_p2d_bm1) p2d base mask descriptor 2 (gliu_p2d_bm2) these registers set up the physical to device base mask descriptors for determining an address hit. msr address 51010020h ty p e r / w reset value 000000ff_fff00000h msr address 51010021h ty p e r / w reset value 000000ff_fff00000h msr address 51010022h ty p e r / w reset value 000000ff_fff00000h gliu_p2d_bm[x] register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 pdid1_bm pcmp_biz_bm rsvd pbase 313029282726252423222120191817161514131211109876543210 pbase_bm pmask_bm gliu_p2d_bm[x] bit descriptions bit name description 63:61 pdid_bm physical descriptor destination id. these bits define which port to route the request to if it is a hit based on the other settings in this register. 000: port 0 (gliu) 100: port 4 (dd) 001: port 1 (glpci_sb) 101: port 5 (acc) 010: port 2 (usbc2) 110: port 6 (usbc1) 011: port 3 (atac) 111: port 7 (glcp) 60 pcmp_biz_bm physical compare bizzaro flag. 0: consider only transactions whose bizzaro flag is low as a potentially valid address hit. a low bizzaro flag indicates a normal transaction cycle such as a memory or i/o. 1: consider only transactions whose bizzaro fl ag is high as a potentially valid address hit. a high bizzaro flag indicates a ?special? transaction, such as a pci shutdown or halt cycle 59:40 rsvd reserved. write as read. 39:20 pbase_bm physical memory address base. these bits form the matching value against which the masked value of the physical address bits [31: 12] are directly compared. if a match is found, then a hit is declared, depending on the setting of the bizzaro flag comparator. 19:0 pmask_bm physical memory address mask. these bits are used to mask physical address bits [31:12] for the purposes of this hit detection. 210 amd geode? cs5535 companion device data book geodelink? interface unit register descriptions 31506b 6.1.2.2 p2d base mask kel descriptors (gliu_p2d_bmk[x]) p2d base mask kel descriptor 0 (gliu_p2d_bmk0) p 2d base mask kel descriptor 1 (gliu_p2d_bmk1) this is a special version of a p2d_bm descriptor to sup port routing the usb keyboard emulation logic (kel) native regis- ters to the default port. the default port device on the geode cs5535 companion device contains the kel. msr address 51010023h ty p e r / w reset value 000000ff_fff00000h msr address 51010024h ty p e r / w reset value 000000ff_fff00000h gliu_p2d_bmk[x] register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 pdid1_bm k pcmp_biz_bmk rsvd pbase_bmk 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pbase_bmk pmask_bmk gliu_p2d_bmk[x] bit descriptions bit name description 63:61 pdid1_bmk physical descriptor destination id. descriptor destination id. these bits define which port to route the request to if it is a hi t based on the other sett ings in this register. 000: port 0 (gliu) 100: port 4 (dd) 001: port 1 (glpci_sb) 101: port 5 (acc) 010: port 2 (usbc2) 110: port 6 (usbc1) 011: port 3 (atac) 111: port 7 (glcp) 60 pcmp_biz_bmk physical compare bizzaro flag. if set, bit 8 of the address must be low for a hit on this descriptor. 59:40 rsvd reserved. write as read. 39:20 pbase_bmk physical memory address base. these bits form the matching value against which the masked value of the physical address bits [31:12] are directly compared. if a match is found, then a hit is declared, depending on the setting of the bizzaro flag compara- tor. 19:0 pmask_bmk physical memory address mask. these bits are used to mask physical address bits [31:12] for the purposes of this hit detection. amd geode? cs5535 companion device data book 211 geodelink? interface unit register descriptions 31506b 6.1.3 gliu specific msrs 6.1.3.1 coheren cy (gliu_coh) 6.1.3.2 port active enable (gliu_pae) msr address 51010080h ty p e r / w reset value 00000000_00000000h gliu_coh register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd cohp gliu_coh bit descriptions bit name description 63:3 rsvd reserved. write as read. 2:0 cohp coherent device port. the port that coherent snoops ar e routed to. if the coherent device is on the other side of a bridge, the cohp points to the bridge. 000: port 0 (gliu) 100: port 4 (dd) 001: port 1 (glpci_sb) 101: port 5 (acc) 010: port 2 (usbc2) 110: port 6 (usbc1) 011: port 3 (atac) 111: port 7 (glcp) msr address 51010081h ty p e r / w reset value 00000000_0000ffffh gliu_pae register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd pae0 pae7 pae6 pae5 pae4 pae3 pae2 pae1 gliu_pae bit descriptions bit name description 63:16 rsvd reserved. write as read. 15:14 pae0 port active enable for port 0 (gliu). 00: off - master transactions are disabled. 01: low - master transactions limited to one outstanding transaction. 10: reserved. 11: on - master transactions enabled with no limitations. 13:12 pae7 port active enable for port 7 (glcp). see bits [15:14] for decode. 11:10 pae6 port active enable for port 6 (usbc1). see bits [15:14] for decode. 9:8 pae5 port active enable for port 5 (acc). see bits [15:14] for decode. 7:6 pae4 port active enable for port 4 (dd). see bits [15:14] for decode. 212 amd geode? cs5535 companion device data book geodelink? interface unit register descriptions 31506b 6.1.3.3 arbitration (gliu_arb) 6.1.3.4 asynchronou s smi (gliu_asmi) asmi is a condensed version of the port asmi signals. the en bi ts ([15:8]) can be used to prevent a device from issuing an asmi. a write of 1 to the en bit disables the device?s asmi. th e flag bits ([7:0]) are status bits. if high, an asmi was gen- erated due to the associated device. (see section 4. 1.4 "asmi and error" on page 57 for further details.) 5:4 pae3 port active enable for port 3 (atac). see bits [15:14] for decode. 3:2 pae2 port active enable for port 2 (usbc2). see bits [15:14] for decode. 1:0 pae1 port active enable for port 1 (glpci_sb). msr address 51010082h ty p e r / w reset value 00000000_00000000h gliu_arb register 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd pipe_dis rsvd 313029282726252423222120191817161514131211109876543210 rsvd gliu_arb bit descriptions bit name description 63 rsvd reserved . write as read. 62 pipe_dis pipelined arbitration disabled. 0: pipelined arbitration enabled and the gliu is not limited to one outstanding transaction. 1: limit the entire gliu to one outstanding transaction. 61:0 rsvd reserved . write as read. msr address 51010083h ty p e r / w reset value 00000000_00000000h gliu_pae bit descriptions (continued) bit name description gliu_asmi register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd p7_asmi_en p6_asmi_en p5_asmi_en p4_asmi_en p3_asmi_en p2_asmi_en p1_asmi_en p0_asmi_en p7_asmi_flag p6_asmi_flag p5_asmi_flag p4_asmi_flag p3_asmi_flag p2_asmi_flag p1_asmi_flag p0_asmi_flag amd geode? cs5535 companion device data book 213 geodelink? interface unit register descriptions 31506b 6.1.3.5 asynchronou s error (gliu_aerr) err is a condensed version of the port (asynchronous) err sig nals. the en bits ([15:8]) can be used to prevent a device from issuing an err. a write of 1 to the en bit disables the de vice?s err. the flag bits ([7: 0]) are status bits. if high, an err was generated due to the associated device. (see sect ion 4.1.4 "asmi and error" on page 57 for further details.) gliu_asmi bit descriptions bit name description 63:16 rsvd reserved. 15 p7_asmi_en port 7 (glcp) asynchronous smi enable. 14 p6_asmi_en port 6 (usbc1) asynchronous smi enable. 13 p5_asmi_en port 5 (acc) asynchronous smi enable. 12 p4_asmi_en port 4 (dd) asynchronous smi enable. 11 p3_asmi_en port 3 (atac) asynchronous smi enable. 10 p2_asmi_en port 2 (usbc2) asynchronous smi enable. 9 p1_asmi_en port 1 (glpci_sb) asynchronous smi enable. 8 p0_asmi_en port 0 (gliu) asynchronous smi enable. 7 p7_asmi_flag (ro) port 7 (glcp) asynchronous smi flag (read only). 6 p6_asmi_flag (ro) port 6 (usbc1) asynchronous smi flag (read only). 5 p5_asmi_flag (ro) port 5 (acc) asynchronous smi flag (read only). 4 p4_asmi_flag (ro) port 4 (dd) asynchronous smi flag (read only). 3 p3_asmi_flag (ro) port 3 (atac) asynchronous smi flag (read only). 2 p2_asmi_flag (ro) port 2 (usbc2) asynchronous smi flag (read only). 1 p1_asmi_flag (ro) port 1 (glpci_sb) asynchronous smi flag (read only). 0 p0_asmi_flag (ro) port 0 (gliu) asynchronous smi flag (read only). msr address 51010084h ty p e r / w reset value 00000000_00000000h gliu_aerr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd p7_aerr_en p6_aerr_en p5_aerr_en p4_aerr_en p3_aerr_en p2_aerr_en p1_aerr_en p0_aerr_en p7_aerr_flag p6_aerr_flag p5_aerr_flag p4_aerr_flag p3_aerr_flag p2_aerr_flag p1_aerr_flag p0_aerr_flag 214 amd geode? cs5535 companion device data book geodelink? interface unit register descriptions 31506b 6.1.3.6 debug (gliu_debug) gliu_aerr bit descriptions bit name description 63:16 rsvd reserved. 15 p7_aerr_en port 7 (glcp) asynchronous error enable. 14 p6_aerr_en port 6 (usbc1) asynchronous error enable. 13 p5_aerr_en port 5 (acc) asynchronous error enable. 12 p4_aerr_en port 4 (dd) asynchronous error enable. 11 p3_aerr_en port 3 (atac) asynchronous error enable. 10 p2_aerr_en port 2 (usbc2) asynchronous error enable. 9 p1_aerr_en port 1 (glpci_sb) asynchronous error enable. 8 p0_aerr_en port 0 (gliu) asynchronous error enable. 7 p7_aerr_flag (ro) port 7 (glcp) asynchronous error flag (read only). 6 p6_aerr_flag (ro) port 6 (usbc1) asynchronous error flag (read only). 5 p5_aerr_flag (ro) port 5 (acc) asynchronous error flag (read only). 4 p4_aerr_flag (ro) port 4 (dd) asynchronous error flag (read only). 3 p3_aerr_flag (ro) port 3 (atac) asynchronous error flag (read only). 2 p2_aerr_flag (ro) port 2 (usbc2) asynchronous error flag (read only). 1 p1_aerr_flag (ro) port 1 (glpci_sb) asynchronous error flag (read only). 0 p0_aerr_flag (ro) port 0 (gliu) asynchronous error flag (read only). msr address 51010085h ty p e r / w reset value 00000000_00000004h gliu_debug register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd gliu_debug bit descriptions bit name description 63:0 rsvd reserved. write as read. amd geode? cs5535 companion device data book 215 geodelink? interface unit register descriptions 31506b 6.1.3.7 physical capabi lities (gliu_phy_cap) this register provides the resources ava ilable in the geode cs5535 companion device. msr address 51010086h ty p e r o reset value 327920a0_80000003h gliu_phy_cap register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd nstat_cnt ndbg_da_cmp ndbg_rq_cmp nports ncoh niod_sc niod_bm np2d_bmk 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 np2d_bmk np2d_sc np2d_ro np2d_r np2d_bmo np2d_bm gliu_phy_cap bit descriptions bit name description 63 rsvd reserved. returns 0. 62:60 nstat_cnt number of statistic counters. provides the number of available statistic counters. 59:57 ndbg_da_cmp number of data comparators. provides the number of available data comparators . 56:54 ndbg_rq_cmp number of request comparators. provides the number of available request comparators. 53:51 nports number of ports on the gliu. provides the number of available ports on the gliu. 50:48 ncoh number of coherent devices. provides the number of available coherent devices. 47:42 niod_sc number of iod_sc descriptors. provides the number of available i od_sc descriptors. 41:36 niod_bm number of iod_bm descriptors. provides the number of available iod_bm descriptors. 35:30 np2d_bmk number of p2d_bmk descriptors. provides the number of available p2d_bmk descriptors. 29:24 np2d_sc number of p2d_sc descriptors. provides the number of available p2d_sc descriptors 23:18 np2d_ro number of p2d_ro descriptors. provides the number of available p2d_ro descriptors. 17:12 np2d_r number of p2d_r descriptors. provides the number of available p2d_r descriptors. 11:6 np2d_bmo number of p2d_bmo descriptors. provides the number of available p2d_bmo descriptors. 5:0 np2d_bm number of p2d_bm descriptors. provides the number of available p2d_bm descriptors. 216 amd geode? cs5535 companion device data book geodelink? interface unit register descriptions 31506b 6.1.3.8 n outstanding response (gliu_nout_resp) . 6.1.3.9 number of outstanding write data (gli u_nout_wdata) 6.1.3.10 who am i (gliu_whoami) msr address 51010087h ty p e r o reset value 00000000_00000000h gliu_nout_resp register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd gliu_nout_resp bit descriptions bit name description 63:0 rsvd reserved. returns 0. msr address 51010088h ty p e r o reset value 00000000_00000000h gliu_nout_wdata register map (ro) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd gliu_nout_wdata bit descriptions bit name description 63:0 rsvd reserved. returns 0. msr address 5101008bh ty p e r o reset value configuration dependent gliu_whoami register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd gliu_whoami bit descriptions bit name description 63:0 rsvd reserved. returns 0. amd geode? cs5535 companion device data book 217 geodelink? interface unit register descriptions 31506b 6.1.3.11 slave disable (gliu_slv_dis) msr address 5101008ch ty p e r / w reset value 00000000_00000000h gliu_slv_dis register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd gliu_slv_dis bit descriptions bit name description 63:0 rsvd reserved. write as read. 218 amd geode? cs5535 companion device data book geodelink? interface unit register descriptions 31506b 6.1.3.12 descriptor statistic co unters (gliu_statistic_cnt[x]) descriptor statistic counter 0 (gliu_statistic_cnt0) descriptor statistic counter 1 (gliu_statistic_cnt1) descriptor statistic counter 2 (gliu_statistic_cnt2) these registers work in conjunction with the gliu_stati stic_mask[x] and the gliu_statistic_action[x] registers. the counters count ?hits? on the p2d and iod de scriptors. the counter behaves as setup in the gliu_statistic_action[x] register. msr address 510100a0h ty p e w o reset value 00000000_00000000h msr address 510100a4h ty p e w o reset value 00000000_00000000h msr address 510100a8h ty p e w o reset value 00000000_00000000h gliu_statistic_cnt[x] register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 load_val 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cnt gliu_statistic_cnt[x] bit descriptions bit name description 63:32 load_val counter load value. a value loaded here will be used as the initial statistics counter value when a load action occurs or is commanded. 31:0 cnt counter value. these bits provide the current counter value when read. amd geode? cs5535 companion device data book 219 geodelink? interface unit register descriptions 31506b 6.1.3.13 descriptor statistic mask (gliu_statistic_mask[x]) descriptor statistic mask 0 (gliu_statistic_mask0) descriptor statistic mask 1 (gliu_statistic_mask1) descriptor statistic mask 2 (gliu_statistic_mask2) msr address 510100a1h ty p e r / w reset value 00000000_00000000h msr address 510100a5h ty p e r / w reset value 00000000_00000000h msr address 510100a9h ty p e r / w reset value 00000000_00000000h gliu_statistic_mask[x] register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 iod_mask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p2d_mask gliu_statistic_mask[x] bit descriptions bit name description 63:32 iod_mask mask for hits to each iod. hits are determined after the request is arbitrated. a hit is determined by the following logical equation: hit = |(iod_mask[n-1:0] & rq _desc_hit[n-1:0] && is_io) | |(p2d_mask[n-1:0] & rq_desc_hit[n-1:0] && is_mem) 31:0 p2d_mask mask for hits to each p2d. a hit is determined by the following logical equation: hit = |(iod_mask[n-1:0] & rq_desc_hit[n-1:0] && is_io) | |(p2d_mask[n-1:0] & rq_desc_hit[n-1:0] && is_mem) 220 amd geode? cs5535 companion device data book geodelink? interface unit register descriptions 31506b 6.1.3.14 descriptor statistic ac tion (gliu_statistic_action[x]) descriptor statistic action 0 (gliu_statistic_action0) descriptor statistic action 1 (gliu_statistic_action1) descriptor statistic action 2 (gliu_statistic_action2) msr address 510100a2h ty p e r / w reset value 00000000_00000000h msr address 510100a6h ty p e r / w reset value 00000000_00000000h msr address 510100aah ty p e r / w reset value 00000000_00000000h gliu_statistic_action[x] register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd prediv wrap zero_err zero_smi always_dec hit_err hit_smi hit_dec hit_lden gliu_statistic_action[ x] bit descriptions bit name description 63:24 rsvd reserved. write as read. 23:8 prediv pre-divider used for always_dec. the pre-divider is free running and extends the depth of the counter. 7wrap decrement counter beyond zero and wrap. 0: disable wrap; counter stops when it reaches zero. 1: enable wrap; counter decrements through 0 to all ones. 6 zero_err asset aerr on cnt = 0. assert aerr (internal gliu_p_serr) when statistic_cnt[x] = 0. 0: disable. 1: enable. 5 zero_smi assert asmi on cnt = 0. assert asmi (internal gliu_p_asmi) when statistic_cnt[x] = 0. 0: disable. 1: enable. 4 always_dec always decrement counter. if enabled, the counter will decrement on every memory clock, subject to the prescaler value prediv (bits [23:8]). decrementing will continue unless loading is occurring due to another action, or if the counter reaches zero and wrap is disabled (bit[7]). 0: disable. 1: enable. amd geode? cs5535 companion device data book 221 geodelink? interface unit register descriptions 31506b 6.1.3.15 request compare value (gliu_rq_comp_val) the rq compare value and the rq compare mask enable traps on specific transactions. a hit to the rq compare is determined by hit = (r q_in & rq_comp_mask) == rq_comp_val). a hit can trigger the rq _comp error sources when they are enabled. the value is compared only after the packet is arbitrated. 3hit_err assert aerr on descriptor hit. this bit causes an asynchronous error to be generated when a matching descriptor hit occurs, or not. the descriptor hits are anded with the masks and then all ored together. 0: disable. 1: enable. 2hit_smi assert asmi on descriptor hit. this bit causes an asmi to be generated when a matching descriptor hit occurs, or not. th e descriptor hits are anded with the masks and then all ored together. 0: disable. 1: enable. 1hit_dec decrement counter on descriptor hit. this bit causes the associated counter to dec- rement when a matching descriptor hit occurs, or not.the descriptor hits are anded with the masks and then al l ored together. 0: disable. 1: enable. 0hit_lden load counter on descriptor hit. this bit causes the associated counter to reload its load_val when a matching descriptor hit occurs, or not.the descriptor hits are anded with the masks and then all ored together. 0: disable. 1: enable. msr address 510100c0h ty p e r / w reset value 001fffff_ffffffffh gliu_rq_comp_val register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd rq_compval 313029282726252423222120191817161514131211109876543210 rq_compval gliu_rq_comp_val bit descriptions bit name description 63:53 rsvd reserved. write as read. 52:0 rq_compval request packet value. this is the value compared against the logical bit-wise and of the incoming request packet and the rq_comp_mask in order to determine a hit. gliu_statistic_action[x] bi t descriptions (continued) bit name description 222 amd geode? cs5535 companion device data book geodelink? interface unit register descriptions 31506b 6.1.3.16 request compare mask (gliu_rq_comp_mask) the rq compare value and the rq compare mask enable traps on specific transactions. a hit to the rq compare is determined by hit = (r q_in & rq_comp_mask) == rq_comp_val). a hit can trigger the rq _comp error sources when they are enabled. the value is compared only after the packet is arbitrated. 6.1.3.17 data compare value low (gliu_da_comp_val_lo) the da compare value and the da compare mask enable traps on specific transactions. a hit to the da compare is determined by hit = (da_in & da_comp_mask) == da_comp_ val). a hit can trigger the da_cmp error sources when they are enabled. the value is compared only after the packet is arbitrated. msr address 510100c1h ty p e r / w reset value 00000000_00000000h gliu_rq_comp_mas k register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd rq_compmask 313029282726252423222120191817161514131211109876543210 rq_compmask gliu_rq_comp_mask bit descriptions bit name description 63:53 rsvd reserved. write as read. 52:0 rq_compmask request packet mask. this field is bit-wise logically anded with the incoming request packet before it is compared to the rq_compval. msr address 510100d0h ty p e r / w reset value 00001fff_ffffffffh gliu_da_comp_val_lo register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd dalo_compval 313029282726252423222120191817161514131211109876543210 dalo_compval gliu_da_comp_val_lo bit descriptions bit name description 63:45 rsvd reserved. write as read. 44:0 dalo_compval data packet compare value [44:0]. this field forms the lower portion of the data value that is compared to the logical bit-wise and of the incoming data value and the data value compare mask in order to determine a hit. the ?hi? and ?lo? portions of the incoming data, the compare value, and th e compare mask, are assembled into com- plete bit patterns before these operations occur. amd geode? cs5535 companion device data book 223 geodelink? interface unit register descriptions 31506b 6.1.3.18 data compare value high (gliu_da_comp_val_hi) the da compare value and the da compare mask enable traps on specific transactions. a hit to the da compare is determined by hit = (da_in & da_comp_mask) == da_comp_ val). a hit can trigger the da_cmp error sources when they are enabled. the value is compared only after the packet is arbitrated. 6.1.3.19 data compare mask low (gliu_da_comp_mask_lo) the da compare value and the da compare mask enable traps on specific transactions. a hit to the da compare is determined by hit = (da_in & da_comp_mask) == da_comp_val). a hit can trigger the da_comp error sources when they are enabled. the value is compared only after the packet is arbitrated. msr address 510100d1h ty p e r / w reset value 0000000f_ffffffffh gliu_da_comp_val_hi register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd dahi_ compval 313029282726252423222120191817161514131211109876543210 dahi_compval gliu_da_comp_val_hi bit descriptions bit name description 63:36 rsvd reserved. write as read. 35:0 dahi_ compval da packet compare value [80:45]. this field forms the upper portion of the data value that is compared to the logical bit-wise and of the incoming data value and the data value compare mask in order to determine a hit. the ?hi? and ?lo? portions of the incoming data, the compare value, and th e compare mask, are assembled into com- plete bit patterns before these operations occur. msr address 510100d2h ty p e r / w reset value 00000000_00000000h gliu_da_comp_mask_lo register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd dalo_compmask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dalo_compmask gliu_da_comp_mask_lo bit descriptions bit name description 63:45 rsvd reserved. write as read. 44:0 dalo_compmask data packet compare value [44:0]. this field is forms the lower portion of the data compmask value, that is then bit-wise logically anded with the incoming data value before it is compared to the da_compval. the ?hi? and ?lo? portions of the incom- ing data, the compare value, and the compare mask, are assembled into complete bit patterns before these operations occur. 224 amd geode? cs5535 companion device data book geodelink? interface unit register descriptions 31506b 6.1.3.20 data compare mask high (gliu_da_comp_mask_hi) msr address 510100d3h ty p e r / w reset value 00000000_00000000h gliu_da_comp_mask_hi register 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd dahi_ compmask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dahi_compmask gliu_da_comp_mask_hi bit descriptions bit name description 63:36 rsvd reserved. write as read. 35:0 dahi_compmask da packet compare mask [80:45]. this field is forms the upper portion of the data compmask value that is then bit-wise logica lly anded with the incoming data value before it is compared to the da_comp_val.th e ?hi? and ?lo? portions of the incom- ing data (the compare value and compare mask) are assembled into complete bit pat- terns before these operations occur. amd geode? cs5535 companion device data book 225 geodelink? interface unit register descriptions 31506b 6.1.4 iod descriptor msrs 6.1.4.1 iod base mask desc riptors (gliu_iod_bm[x]) iod base mask 0 (gliu_iod_bm0) iod base mask 1 (gliu_iod_bm1) iod base mask 2 (gliu_iod_bm2) iod base mask 3 (gliu_iod_bm3) iod base mask 4 (gliu_iod_bm4) iod base mask 5 (gliu_iod_bm5) iod base mask 6 (gliu_iod_bm6) iod base mask 7 (gliu_iod_bm7) iod base mask 8 (gliu_iod_bm8) iod base mask 9 (gliu_iod_bm9) msr address 510100e0h ty p e r / w reset value 60000000_1f0ffff0h msr address 510100e1h ty p e r / w reset value 000000ff_fff00000h msr address 510100e2h ty p e r / w reset value 000000ff_fff00000h msr address 510100e3h ty p e r / w reset value 000000ff_fff00000h msr address 510100e4h ty p e r / w reset value 000000ff_fff00000h msr address 510100e5h ty p e r / w reset value 000000ff_fff00000h msr address 510100e6h ty p e r / w reset value 000000ff_fff00000h msr address 510100e7h ty p e r / w reset value 000000ff_fff00000h msr address 510100e8h ty p e r / w reset value 000000ff_fff00000h msr address 510100e9h ty p e r / w reset value 000000ff_fff00000h gliu_iod_bm[x] register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 idid_bm icmp_biz_bm rsvd ibase 313029282726252423222120191817161514131211109876543210 ibase_bm imask_bm gliu_iod_bm[x] bit descriptions bit name description 63:61 idid_bm i/o descriptor destination id. these bits define which port to route the request to if it is a hit based on the other settings in this register. 000: port 0 (gliu) 100: port 4 (dd) 001: port 1 (glpci_sb) 101: port 5 (acc) 010: port 2 (usbc2) 110: port 6 (usbc1) 011: port 3 (atac) 111: port 7 (glcp) 60 icmp_biz_bm compare bizzaro flag. 0: consider only transactions whose bizzaro flag is low as a potentially valid address hit. a low bizzaro flag indicates a normal transaction cycle such as a memory or i/o. 1: consider only transactions whose bizzaro fl ag is high as a potentially valid address hit. a high bizzaro flag indicates a ?special? transaction, such as a pci shutdown or halt cycle. 226 amd geode? cs5535 companion device data book geodelink? interface unit register descriptions 31506b 6.1.4.2 iod swiss cheese d escriptors (gliu_iod_sc[x]) iod swiss cheese 0 (gliu_iod_sc0) iod swiss cheese 1 (gliu_iod_sc1) iod swiss cheese 2 (gliu_iod_sc2) iod swiss cheese 3 (gliu_iod_sc3) iod swiss cheese 4 (gliu_iod_sc4) iod swiss cheese 5 (gliu_iod_sc5) iod swiss cheese 6 (gliu_iod_sc6) iod swiss cheese 7 (gliu_iod_sc7) each of these eight descriptors checks that the physical address supplied by t he device?s request on the address bits is equal to the ibase_sc field of descriptor register bits and that th e enable write or read conditions given by the descriptor register fields wen and ren respectively matches the request type and enable fields given on the physical address bits of the device?s request. if the above matches, then the descripto r has a hit condition and routes the received address to the programmed destination id, idid1_sc field of the descriptor register bits. 59:40 rsvd reserved. write as read. 39:20 ibase_bm physical i/o address base. these bits form the matching value against which the masked value of the physical address, bits [31:12] are directly compared. if a match is found, then a hit is declared, depending on the setting of the bizzaro flag comparator. 19:0 imask_bm physical i/o address mask. these bits are used to mask address bits [31:12] for the purposes of this hit detection. gliu_iod_bm[x] bit descriptions (continued) bit name description msr address 510100eah ty p e r / w reset value 60000000_403003f0h msr address 510100ebh ty p e r / w reset value 00000000_00000000h msr address 510100ech ty p e r / w reset value 00000000_00000000h msr address 510100edh ty p e r / w reset value 00000000_00000000h msr address 510100eeh ty p e r / w reset value 00000000_00000000h msr address 510100efh ty p e r / w reset value 00000000_00000000h msr address 510100f0h ty p e r / w reset value 00000000_00000000h msr address 510100f1h ty p e r / w reset value 00000000_00000000h gliu_iod_sc[x] register 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 idid_sc icmp_biz_sc rsvd 313029282726252423222120191817161514131211109876543210 en_sc rsvd wen_sc ren_sc ibase_sc rsvd amd geode? cs5535 companion device data book 227 geodelink? interface unit register descriptions 31506b gliu_iod_sc bit descriptions bit name description 63:61 idid_sc i/o descriptor destination id. encoded port number of the destination of addresses which produce a hit based on the other fields in this descriptor. 000: port 0 (gliu) 100: port 4 (dd) 001: port 1 (glpci_sb) 101: port 5 (acc) 010: port 2 (usbc2) 110: port 6 (usbc1) 011: port 3 (atac) 111: port 7 (glcp) 60 icmp_biz_sc compare bizzaro flag. used to check that the bizzaro flag of the request is equal to the picmp_biz_sc bit (this bit). if a matc h does not occur, then the incoming request cannot generate a hit. the bizzar o flag, if set in the incoming request, signifies a ?spe- cial? cycle such as a pc i shutdown or halt. 59:32 rsvd reserved. write as read. 31:24 en_sc enable for hits to idid_sc else subp. bit 0, if set, hit on i/o address base plus 0. bit 1, if set, hit on i/o address base plus 1. : bit 7, if set, hit on i/o address base plus 7. 21 wen_sc descriptor hits idid_sc on write request types else subp. if set, causes the incoming request to be routed to the port specified in idid_sc if the incoming request is a write type. 20 ren_sc descriptors hit idid_sc on read request types else subp. if set, causes the incoming request to be routed to the port specified in idid_sc if the incoming request is a read type. 19:0 ibase_sc i/o address base. this field forms the basis of comparison with the incoming checks that the physical address supplied by the de vice?s request on address bits [31:18] are equal to the pbase field of descriptor register bits [13:0] 2:0 rsvd reserved. write as read. 228 amd geode? cs5535 companion device data book geodelink? pci south bridge register descriptions 31506b 6.2 geodelink? pci south brid ge register descriptions the geodelink? pci south bridge (glpci_sb) register set consists of: standard geodelink device (gld) msrs glpci_sb specific msrs pci configuration registers the msrs (both standard and glpci_sb specific) are accessed via the rdmsr and wrmsr processor instruc- tions. the msr address is derived from the perspective of the cpu core. see section 4.2 "msr addressing" on page 59 for more details on msr addressing. additionally, all glpci_sb specific msrs can be accessed through both the pc i and gliu interfaces. see section 6.2.3 "pci configuration registers" on page 240 for details. the pci configuration registers can only be accessed through the pci interface and include: the first 16 bytes of standard pci configuration regis- ters. msr access registers: ?pmctrl ? pmaddr ?pmdata0 ?pmdata1 tables 6-5 through 6-7 are register summary tables that include reset values and page references where the bit descriptions are provided. table 6-5. standard geodelink? device msrs summary msr address type registe r reset value reference 51000000h ro gld capabilities msr (glpci_gld_msr_cap) 00000000_002051xxh page 230 51000001h r/w gld master configuration msr (glpci_gld_msr_config) 00000000_00000000h page 230 51000002h r/w gld smi msr (glpci_gld_msr_smi) 00000000_00000000h page 231 51000003h r/w gld error msr (glpci_g ld_msr_error) 00000000_00000000h page 232 51000004h r/w gld power management msr (glpci_gld_msr_pm) 00000000_00000000h page 233 51000005h r/w gld diagnostic msr (glpci_gld_msr_diag) 00000000_00000000h page 234 table 6-6. glpci_sb specific msrs summary msr address type registe r reset value reference 51000010h r/w global control (glpci_ctrl) 44000030_00000003h page 234 51000020h r/w region 0 configuration (glpci_r0) 00000000_00000000h page 238 51000021h r/w region 1 configuration (glpci_r1) 00000000_00000000h page 238 51000022h r/w region 2 configuration (glpci_r2) 00000000_00000000h page 238 51000023h r/w region 3 configuration (glpci_r3) 00000000_00000000h page 238 51000024h r/w region 4 configuration (glpci_r4) 00000000_00000000h page 238 51000025h r/w region 5 configuration (glpci_r5) 00000000_00000000h page 238 51000026h r/w region 6 configuration (glpci_r6) 00000000_00000000h page 238 51000027h r/w region 7 configuration (glpci_r7) 00000000_00000000h page 238 51000028h r/w region 8 configuration (glpci_r8) 00000000_00000000h page 238 51000029h r/w region 9 configuration (glpci_r9) 00000000_00000000h page 238 5100002ah r/w region 10 configuratio n (glpci_r10) 00000000_00000000h page 238 5100002bh r/w region 11 configuratio n (glpci_r11) 00000000_00000000h page 238 5100002ch r/w region 12 configuratio n (glpci_r12) 00000000_00000000h page 238 amd geode? cs5535 companion device data book 229 geodelink? pci south bridge register descriptions 31506b 5100002dh r/w region 13 configuratio n (glpci_r13) 00000000_00000000h page 238 5100002eh r/w region 14 configuratio n (glpci_r14) 00000000_00000000h page 238 5100002fh r/w region 15 configuration (glpci_r15) 00000000_00000000h page 238 51000030h ro pci configuration space header byte 0-3 (glpci_pcih ead_byte0-3) 00000000_002a100bh page 239 51000031h ro pci configuration space header byte 4-7 (glpci_pcih ead_byte4-7) 00000000_00000000h page 239 51000032h ro pci configuration space header byte 8-b (glpci_pcih ead_byte8-b) 00000000_00000000h page 239 51000033h ro pci configuration space header byte c-f (glpci_pcih ead_bytec-f) 00000000_00000000h page 240 table 6-7. pci configuration registers index type width (bits) name reset value reference 00h ro 32 (note 1) note 1. read address bits [1:0] are ignored and taken as 00. pci configuration space header byte 0-3 (glpci_pci_head_byte0-3) 002a100bh page 240 04h ro 32 (note 1) pci configuration space header byte 4-7 (glpci_pci_head_byte4-7) 00000000h page 241 08h ro 32 (note 1) pci configuration space header byte 8-b (glpci_pci_head_byte8-b) ff0000xxh page 241 0ch ro 32 (note 1) pci configuration space header byte c-f (glpci_pci_head_bytec-f) 00000000h page 242 f0h r/w 32 pci msr control (glpci_pmctrl) 00000001h page 242 f4h r/w 32 pci msr address (glpci_pmaddr) 00000000h page 243 f8h r/w 32 pci msr data 0 (glpci_pmdata0) 00000000h page 243 fch r/w 32 pci msr data 1 (glpci_pmdata1) 00000000h page 244 table 6-6. glpci_sb specific msrs summary msr address type registe r reset value reference 230 amd geode? cs5535 companion device data book geodelink? pci south bridge register descriptions 31506b 6.2.1 standard geodelink? device (gld) msrs 6.2.1.1 gld capabilities msr (glpci_gld_msr_cap) 6.2.1.2 gld master configurat ion msr (glpci_gld_msr_config) msr address 51000000h ty p e r o reset value 00000000_002051xxh glpci_gld_msr_cap register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd dev_id rev_id glpci_gld_msr_cap bit descriptions bit name description 63:24 rsvd reserved. reads as 0. 23:8 dev_id device id. identifies module (2051h). 7:0 rev_id revision id. identifies module revision. see amd geode? cs5535 companion device specification update document for value. msr address 51000001h ty p e r / w reset value 00000000_00000000h glcpi_gld_msr_config register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd pri rsvd pid glpci_gld_msr_config bit descriptions bit name description 63:7 rsvd (ro) reserved (read only). returns 0. 6:4 pri priority level. always write 0. 3 rsvd (ro) reserved (read only). returns 0. 2:0 pid priority id. always write 0. amd geode? cs5535 companion device data book 231 geodelink? pci south bridge register descriptions 31506b 6.2.1.3 gld smi msr (glpci_gld_msr_smi) the flags are set by internal conditions. the internal conditions are enabled if the en bit is 1. reading the flag bit returns the value; writing 1 clears the flag; writ ing 0 has no effect. (see section 4.8.3 "msr address 2: smi control" on page 74 for further smi/asmi generation details.) msr address 51000002h ty p e r / w reset value 00000000_00000000h glpci_gld_msr_smi register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd tas_asmi_flag par_asmi_flag syse_asmi_flag excep_asmi_flag ssmi_asmi_flag tar_asmi_flag mar_asmi_flag rsvd tas_asmi_en par_asmi_en syse_asmi_en excep_asmi_en ssmi_asmi_en ta r _ a s m i _ e n mar_asmi_en glpci_gld_msr_smi bit descriptions bit name description 63:23 rsvd (ro) reserved (read only). returns 0. 22 tas_asmi_ flag target abort signaled asmi flag. if high, records that an asmi was generated due the signaling of a target abort on the pci bus. write 1 to clear; writing 0 has no effect. ta_asmi_en (bit 6) must be high to generate asmi and set flag. 21 par_asmi_ flag parity error asmi flag. if high, records that an asmi was generated due to the detec- tion of a pci bus parity error. write 1 to clear; writing 0 has no effect. par_asmi_en (bit 5) must be high to generate asmi and set flag. 20 syse_asmi_ flag system error asmi flag. if high, records that an asmi was generated due to the detec- tion of a pci bus system error. write 1 to clear; writing 0 has no effect. syse_asmi_en (bit 4) must be high to generate asmi and set flag. 19 excep_asmi_ flag exception bit flag. if high, records that an asmi was generated due to the excep bit being set in the received gliu read or write response packet. write 1 to clear; writing 0 has no effect. excep_asmi_en (bit 3) must be set to enable this flag. 18 ssmi_asmi_ flag ssmi asmi flag. if high, records that an asmi was generated due to the ssmi bit being set in the received gliu read or write response packet. write 1 to clear; writing 0 has no effect. ssmi_asmi_en (bit 2) must be set to enable this flag. 17 tar_asmi_ flag target abort received asmi flag. if high, records that an asmi was generated due to the reception of a target abort on the pci bu s. write 1 to clear; writing 0 has no effect. tar_asmi_en (bit 1) must be high to generate asmi and set flag. 16 mar_asmi_ flag master abort received asmi flag. if high, records that an asmi was generated due to the reception of a master abort on the pci bus. write 1 to clear; writing 0 has no effect. mar_asmi_en (bit 0) be high to generate asmi and set flag. 15:7 rsvd (ro) reserved (read only). returns 0. 6 tas_asmi_en target abort signaled asmi enable. write 1 to enable tas_asmi_flag (bit 22) and to allow the event to generate an asmi. 5 par_asmi_en parity error asmi enable. write 1 to enable par_asmi_flag (bit 21) and to allow the event to generate an asmi. 4 syse_asmi_ en system error smi enable. write 1 to enable syse_asmi_fl ag (bit 20) and to allow the event to generate an asmi. 232 amd geode? cs5535 companion device data book geodelink? pci south bridge register descriptions 31506b 6.2.1.4 gld error msr (glpci_gld_msr_error) the flags are set by internal conditions. the internal conditions are enabled if the en bit is 1. reading the flag bit returns the value; writing 1 clears the flag; writing 0 has no effect. (see section 4.8.4 "msr address 3: error control" on page 78 for further details.) 3 excep_asmi_ en exception bit enable. write 1 to enable excep_asmi_flag (bit 19) and to allow the event. 2 ssmi_en ssmi enable. write 1 to enable ssmi_asmi_flag bit (bit 18) and to allow the event. 1 tar_asmi_en target abort received asmi enable. write 1 to enable tar_asmi_flag (bit 17) and to allow the event to generate an asmi. 0 mar_asmi_en master abort received asmi enable. write 1 to enable mar_asmi_flag (bit 16) and to allow the event to generate an asmi. msr address 51000003h ty p e r / w reset value 00000000_00000000h glpci_gld_msr_error register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd tas_err_flag pare_err_flag syse_err_flag excep_err_flag rsvd ta r _ e r r _ f l ag mar_err_flag rsvd tas_err_en pare_err_en syse_err_en excep_err_en rsvd tar_err_en mar_err_en glpci_gld_msr_error bit descriptions bit name description 63:23 rsvd reserved (read only). returns 0. 22 tas_err_ flag target abort signaled error flag. if high, records that an err was generated due to signaling of a target abort on the pci bus. write 1 to clear; writing 0 has no effect. tas_err_en (bit 6) must be set to enable this event and set flag. 21 pare_err_ flag parity error flag. if high, records that an err was generated due to the detection of a pci bus parity error. write 1 to clear; writing 0 has no effect. pare_err_en (bit 5) must be set to enable this event and set flag. 20 syse_err_ flag system error flag. if high, records that an err was generated due to the detection of a pci bus system error. write 1 to clear; wr iting 0 has no effect. syse_err_en (bit 4) must be set to enable this event and set flag. 19 excep_err_ flag exception bit error flag. if high, records that the excp bit in the received gliu read or write response packet is set. write 1 to clear. excep_err_en (bit 3) must be set to enable this event and set flag. 18 rsvd reserved (read only). returns 0. 17 tar_err_ flag target abort received error flag. if high, records that an err was generated due to the reception of a target abort on the pci bu s. write 1 to clear; writing 0 has no effect. tar_err_en (bit 1) must be set to enable this event and set flag. glpci_gld_msr_smi bit de scriptions (continued) bit name description amd geode? cs5535 companion device data book 233 geodelink? pci south bridge register descriptions 31506b 6.2.1.5 gld power manageme nt msr (glpci_gld_msr_pm) 16 mar_err_ flag master abort received error flag. if high, records that an err was generated due to the reception of a master abort on the pci bus. write 1 to clear; writing 0 has no effect. mar_err_en (bit 0) must be set to enable this event and set flag. 15:7 rsvd reserved (read only). returns 0. 6 tas_err_en target abort signal ed error enable. write 1 to enable tas_err_flag (bit 22) and to allow the event to generate an err. 5 pare_err_en parity error enable. write 1 to enable par_err_flag (bit 21) and to allow the event to generate an err. 4 syse_err_en system error enable. write 1 to enable syse_err_flag (bit 20) and to allow the event to generate an err. 3 excep_err_ en exception bit error enable. write 1 to enable excep_err_flag (bit 19) and to allow the event to generate an err. 2 rsvd reserved (read only). returns 0. 1 tar_err_en target abort received error enable. write 1 to enable tar_err_flag (bit 17) and to allow the event to generate an err. 0 mar_err_en master abort received enable. write 1 to enable mar_err_flag (bit 16) and to allow the event to generate an err. msr address 51000004h ty p e r / w reset value 00000000_00000000h clpci_gld_msr_pm register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd io modea rsvd 313029282726252423222120191817161514131211109876543210 rsvd p mode2 p mode1 p mode0 glpci_gld_msr_pm bit descriptions bit name description 63:50 rsvd (ro) reserved (read only). returns 0. 49:48 iomodea i/o mode a control. these bits determine how the associated pci inputs and outputs will behave when the pmc asserts two internal signals that are controlled by pms i/o offset 20h and 0ch. the list of affected signals is given in table 4-11 "sleep driven pci signals" on page 79. 00: no gating of i/o cells during a sleep sequence (default). 01: during a power management sleep sequence, force inputs to their non-asserted state when pm_in_slpctl is enabled. 10: during a power management sleep sequence, force inputs to their non-asserted state when pm_in_slpctl is enabled, and park (force) outputs low when pm_out_slpctl is enabled. 11: immediately and unconditionally, force inpu ts to their not asserted state, and park (force) outputs low. glpci_gld_msr_error bit de scriptions (continued) bit name description 234 amd geode? cs5535 companion device data book geodelink? pci south bridge register descriptions 31506b 6.2.1.6 gld diagnostic msr (glpci_gld_msr_diag) this register is reserved for internal use by amd and should not be written to. 6.2.2 glpci_sb specific msrs 6.2.2.1 global control (glpci_ctrl) 47:35 rsvd (ro) reserved (read only). returns 0. 34:32 rsvd reserved. write as read. 31:6 rsvd (ro) reserved (read only). returns 0. 5:4 pmode2 power mode 2. power mode for pci-fast clock domain. 00: disable clock gating. clocks are always on. 01: enable active hardware clock gating. clock goes off whenever this module?s circuits are not busy. 10: reserved. 11: reserved. 3:2 pmode1 power mode 1. power mode for pci clock domain. 00: disable clock gating. clocks are always on. 01: enable active hardware clock gating. clock goes off whenever this module?s circuits are not busy. 10: reserved. 11: reserved. 1:0 pmode0 power mode 0. power mode for gliu clock domain. 00: disable clock gating. clocks are always on. 01: enable active hardware clock gating. clock goes off whenever this module?s circuits are not busy. 10: reserved. 11: reserved. msr address 51000005h ty p e r / w reset value 00000000_00000000h glpci_gld_msr_pm bit descriptions (continued) bit name description msr address 51000010h ty p e r / w reset value 44000030_00000003h glpci_ctrl register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 fth rth rsvd rtl rsvd slto ilto lat 000 313029282726252423222120191817161514131211109876543210 rsvd sus rsvd fpide ppide lrh rdhp pside rpide legact sdoff hcd ioed rsvd cism od ie me amd geode? cs5535 companion device data book 235 geodelink? pci south bridge register descriptions 31506b glpci_ctrl bit descriptions bit name ib/ob description 63:60 fth ib in-bound flush threshold. controls the timing for requesting new read data while concurrently flushing previously prefetched, stale read data. while flushing stale data, if the number of prefetched 64-bit words reac hes this level, then a new read request is made. 59:56 rth ib in-bound read threshold. controls the timing for prefetching read data. if the number of prefetched 32-bit words is decremented and reaches th is threshold, a subsequent gliu request is generated to fetch the next cache-line of read data. 55:52 rsvd (ro) --- reserved (read only). returns 0. 51:49 rtl ob retry transaction limit. limits the number of out-bound retries. if a target signals retry indefinitely the pci interface may be configured to abort the failing out-bound request. 000: no limit. 100: 64 retries. 001: 8 retries. 101: 128 retries. 010: 16 retries. 110: 256 retries. 011: 32 retries. 111: 512 retries. 48:43 rsvd (ro) --- reserved (read only). returns 0. 42 slto ib subsequent latency time-out select. specifies the subsequen t target latency time- out limit. if, within a burst, the glpci_sb mo dule does not respond with the configured number of clock edges the pci interface terminates the pci bus cycle. 0: 8 pci clock edges. 1: 4 pci clock edges. 41:40 ilto ib initial latency time-out select. specifies the initial target latency time-out limit for the pci interface. if the glpci_sb module does not respond with the first data phase within the configured number of clock edges the pc i interface terminates the pci bus cycle. 00: 32 pci clock edges. 10: 8 pci clock edges. 01: 16 pci clock edges. 11: 4 pci clock edges. 39:35 lat ib/ob pci usage timer. usage time-out value for limiting bus tenure. 34:32 0 (ro) ib/ob constant 0 (read only). the three least significant bits of the pci latency timer field are fixed as zeros. these bits are not used as part of the pci latency timer comparison. 31:24 rsvd (ro) --- reserved (read only). returns 0. 23:21 sus ib/ob busy sustain. controls the sustain time for keeping the clocks running after the internal busy signals indicate that the clocks may be gated. 000: no sustain. 100: 32 clock cycles. 001: 4 clock cycles. 101: 64 clock cycles. 010: 8 clock cycles. 110: 128 clock cycles. 011: 16 clock cycles. 111: 256 clock cycles. 20 rsvd (ro) --- reserved (read only). returns 0. 236 amd geode? cs5535 companion device data book geodelink? pci south bridge register descriptions 31506b 19:18 fpide ib prefetch primary ide. if these bits are set, i/o reads to address 1f0h conform to a prefetching behavior. under this mode, the glpci_sb issues gliu read request packets for this specific address before receiving a request on the pci bus for it. when ide prefetch is enabled, all pci accesses to 1f0h must be dwords; that is, 4 bytes. this setting can only be changed between pio operations. 00: off. (default) 01: at ?beginning? initialize pipeline with two read requests. 10: at ?beginning? initialize pipeline with three read requests. 11: reserved. the prefetch only applies if the current command is "read". the current command is assumed from the last writ e to ide command register at 1f7h. the following com- mands are considered "reads": read sectors - 20h read multiple - c4h read buffer - e4h prefetch does not cross sector boundaries; t hat is, 512-byte boundaries. any prefetched data is discarded and the ?boundary? set to 0 on any write to 1f7h. 17 ppide ib post primary ide. defaults to 0. if this bit is set, i/ o writes to address 1f0h are posted; that is, the ?send response? flag is not set in the gliu write request packet. effectively, an i/o write to this specific address is post ed just like memory writes are posted. when ide posting is enabled, single and double word writes may be mixed without restric- tion. 16 lrh ib legacy i/o retry/hold. 0: legacy i/o retry. 1: legacy i/o hold. regardless of the above settings an i/o read or write to 1f0h always causes a retry if data can not be immediately transferred. 15 rdhp ib reject dma high page. controls the decoding of i/o range associated with the dma high page registers (480h-48fh). 0: considered part of legacy i/o. 1: subtractive decode. 14 rside ib reject secondary ide. controls the decoding of i/o range associated with secondary ide address of 170h-177h and 376h. 0: considered part of legacy i/o. 1: subtractive decode. 13 rpide ib reject primary ide. controls the decoding of i/o range associated with primary ide address of 1f0h-1f7h and 3f6h. 0: considered part of legacy i/o. 1: subtractive decode. 12:11 legact ib legacy i/o space active decode. 00: subtractive decode (claim on fourth clock). 01: slow decode (claim on third clock). 10: medium decode (claim on second clock). 11: reserved (implemented as medium decode and returned 10 when read). 10 sdoff ob non legacy subtractive decode off. 0: subtractive decode enabled. 1: subtractive decode disabled. glpci_ctrl bit descriptions (continued) bit name ib/ob description amd geode? cs5535 companion device data book 237 geodelink? pci south bridge register descriptions 31506b 9 hcd ib hold for cis transfer disable. 0: hold for cis transfer enabled. 1: hold for cis transfer disabled. 8ioed ib i/o addressing error checking disable. 0: i/o addressing error checking enabled. 1: i/o addressing error checking disabled. 7:5 rsvd (ro) --- reserved (read only). returns 0. 4:3 cism ib/ob cis mode. 00: mode a (default). not used in normal operation. 01: mode b. not used in normal operation. 10: mode c. used in normal operation. 11: reserved. see section 5.2.14 "cpu interface serial (cis)" on page 87 for details regarding opera- tion modes. 2od ob out-bound request disable. 0: out-bound request enabled. 1: out-bound request disabled. when an out-bound request is disabled, all outstanding out-bound requests are ser- viced before a read response packet with ssmi bit and all data bits cleared and excep bit set is returned. 1ie ib i/o enable. enable handling of in-bound i/o transactions from pci. when set to 1 the pci interface accepts all in-bound i/o transactions from pci. this mode is only intended for design verification purposes. when cleared to 0 no in-bound i/o transactions are accepted. 0me ib memory enable. enable handling of in-bound memo ry access transaction from pci. when cleared to 0, the pci interface does not accept any in-bound memory transactions from the pci bus. glpci_ctrl bit descriptions (continued) bit name ib/ob description 238 amd geode? cs5535 companion device data book geodelink? pci south bridge register descriptions 31506b 6.2.2.2 region 0-15 configuration msrs (glpci_r[x]) region 0 configuration (glpci_r0) region 1 configuration (glpci_r1) region 2 configuration (glpci_r2) region 3 configuration (glpci_r3) region 4 configuration (glpci_r4) region 5 configuration (glpci_r5) region 6 configuration (glpci_r6) region 7 configuration (glpci_r7) region 8 configuration (glpci_r8) region 9 configuration (glpci_r9) region 10 configuration (glpci_r10) region 11 configuration (glpci_r11) region 12 configuration (glpci_r12) region 13 configuration (glpci_r13) region 14 configuration (glpci_r14) region 15 configuration (glpci_r15) msr address 51000020h ty p e r / w reset value 00000000_00000000h msr address 51000021h ty p e r / w reset value 00000000_00000000h msr address 51000022h ty p e r / w reset value 00000000_00000000h msr address 51000023h ty p e r / w reset value 00000000_00000000h msr address 51000024h ty p e r / w reset value 00000000_00000000h msr address 51000025h ty p e r / w reset value 00000000_00000000h msr address 51000026h ty p e r / w reset value 00000000_00000000h msr address 51000027h ty p e r / w reset value 00000000_00000000h msr address 51000028h ty p e r / w reset value 00000000_00000000h msr address 51000029h ty p e r / w reset value 00000000_00000000h msr address 5100002ah ty p e r / w reset value 00000000_00000000h msr address 5100002bh ty p e r / w reset value 00000000_00000000h msr address 5100002ch ty p e r / w reset value 00000000_00000000h msr address 5100002dh ty p e r / w reset value 00000000_00000000h msr address 5100002eh ty p e r / w reset value 00000000_00000000h msr address 5100002fh ty p e r / w reset value 00000000_00000000h glpci_r[x] register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 top rsvd space 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 base rsvd pf rsvd rh en amd geode? cs5535 companion device data book 239 geodelink? pci south bridge register descriptions 31506b 6.2.2.3 pci configuration space header byte 0-3 (glpci_pcihead_byte0-3) reads back the value of pci configuration space header by te 0-3 (glpci_pci_head_byte0 -3). see section 6.2.3.1 on page 240 for register map and bit definitions. 6.2.2.4 pci configuration space header byte 4-7 (glpci_pcihead_byte4-7) reads back the value of pci configuration space header by te 4-7 (glpci_pci_head_byte4 -7). see section 6.2.3.2 on page 241 for register map and bit definitions. 6.2.2.5 pci configuratio n space header byte 8- b (glpci_pcihead_byte8-b) reads back the value of pci configuration space header byte 8-b (glpci_pci_head_byt e8-b). see section 6.2.3.3 on page 241 for register map and bit definitions. glpci_regconf[x] bit descriptions bit name description 63:44 top top of region. for memory use [63:44] as top of address bits [31:12]. for i/o use [63:46] as top of address bits [19:2]. (note 1) note 1. for memory, 4 kb granularity, inclus ive: [63:44] <= addr ess[31:12] <= [31:12]. for i/o, 4b granularity, inclusive: [63:46] <= address[19:2] <= [31:14]. 43:33 rsvd (ro) reserved (read only): returns 0. 32 space region space indicator. 0: memory space. 1: i/o space. 31:12 base base of region. for memory use [31:12] as base of address bits [31:12]. for i/o use [31:14] as base of address bits [19:2]. (note 1) 11:4 rsvd (ro) reserved (read only). returns 0. 3pf prefetchable. if region is memory and this bit is se t, it indicates a prefetechable memory region. reads to this region have no side-effects. if region is i/o and this bit is set, post all i/o writes to this region. 2 rsvd (ro) reserved (read only). returns 0. 1rh retry/hold. defines whether glpci_sb pci slave generates a retry condition or holds the pci bus until cycle completion. note that even if hold is selected, the cycle will be ter- minated if initial latency time-out is reached. 0: retry. 1: hold. 0en region enable. set to 1 to enable access to this region. msr address 51000030h ty p e r o reset value 00000000_002a100bh msr address 51000031h ty p e r o reset value 00000000_00000000h msr address 51000032h ty p e r o reset value 00000000_00000000h 240 amd geode? cs5535 companion device data book geodelink? pci south bridge register descriptions 31506b 6.2.2.6 pci configuration space header byte c-f (glpci_pcihead_bytec-f) reads back the value of pci configuration space header byte c-f (glpci_pci_head_byt ec-f). see section 6.2.3.4 on page 242 for register map and bit definitions. 6.2.3 pci configuration registers the first 16 bytes of the pci configuration register space consist of standard pci header registers. an additional 32 bytes are used to implement a mailbox for giving access from the pci bus to the internal msrs of the geode cs5535 companion device. msr access mailbox upon reset, msr access is enabled. that is, the pmc- trl.en bit is set. a pci configuration (config) write to reg- ister f0h clearing the en bit is required to disable msr access. an msr read is accomplished by: a pci configuration write to register f4h (pmaddr) with the appropriate address value. if the appropriate address value was previously written to register f4h, then this step is unnecessary. a pci configuration read of register f8h (pmdata0). this starts the gliu msr read. the pci bus is held (i.e., no retry unless time-out) until the transaction completes. a pci configuration read of register fch (pmdata1). the pci bus is held (i.e., no retry unless time-out) until the transaction completes. an msr write is accomplished by: a pci configuration write to register f4h (pmaddr) with the appropriate address value. if the appropriate address value was previously written to register f4h, then this step is unnecessary. a pci configuration write to register f8h (pmdata0). a pci configuration write to register fch (pmdata1). this starts the gliu msr write. the pci bus is held (i.e., no retry unless time-out) until the transaction completes. any pci transaction interrupting an msr read/write trans- action is retried until the msr transaction is complete. the external msr write request always has the send_response bit set. the returned msr read or write response packet is checked for the ssmi and excep bits. 6.2.3.1 pci configuration space header byte 0-3 (glpci_pci_head_byte0-3) msr address 51000033h ty p e r o reset value 00000000_00000000h pci index 00h ty p e r o reset value 002a100bh glpci_pci_head_byte0-3 register map 313029282726252423222120191817161514131211109876543210 dev_id ven_id glpci_pci_head_byte 0-3 bit descriptions bit name description 31:16 dev_id device identification register (read only). identifies geode cs5535 companion as the device. reads as 002ah. 15:0 ven_id vendor identification register (read only). identifies amd as the vendor. reads as 100bh. amd geode? cs5535 companion device data book 241 geodelink? pci south bridge register descriptions 31506b 6.2.3.2 pci configuration space header byte 4-7 (glpci_pci_head_byte4-7) 6.2.3.3 pci configuration space header byte 8-b (glpci_pci_head_byte8-b) pci index 04h ty p e r o reset value 00000000h glpci_pci_head_byte4-7 register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pci_sts pci_cmd glpci_pci_head_byte 4-7 bit descriptions bit name description 31:16 pci_sts pci status register (read only). not implemented. 15:0 pci_cmd pci command register (read only). not implemented. pci index 08h ty p e r o reset value ff0000xxh glpci_pci_head_byte 8-b register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pci_class dev_rev_id glpci_pci_head_byte8-b bit descriptions bit name description 31:16 pci_class pci class code (read only). 15:0 dev_rev_id device revision id (read only). identifies the major and minor silicon revision of the geode cs5535 companion device. can also be read at msr 51700017h[7:0]. see sec- tion 6.20.2.13 "chip revision id (glcp_chip_rev_id)" on page 543. 242 amd geode? cs5535 companion device data book geodelink? pci south bridge register descriptions 31506b 6.2.3.4 pci configuration space header byte c-f (glpci_pci_head_bytec-f) 6.2.3.5 pci msr cont rol (glpci_pmctrl) pci index 0ch ty p e r o reset value 00000000h glpci_pci_head_bytec-f register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pci_bist pci_header pci_ltncy_tmr pci_cache glpci_pci_head_bytec-f bit descriptions bit name description 31:24 pci_bist pci bist register (read only). not implemented. 23:16 pci_header pci header type byte (read only). this register defines t he format of this header. this header is of type format 0, that is, this byte contains all zeroes. 16:8 pci_ltncy_tmr pci latency timer register (read only). not implemented. writing these bits have no effect. 7:0 pci_cache pci cache line size register (read only). not implemented. writing these bits have no effect. pci index f0h ty p e r / w reset value 00000001h glpci_pmctrl register map 313029282726252423222120191817161514131211109876543210 rsvd msr_en glpci_pmctrl bit descriptions bit name description 31:1 rsvd (ro) reserved (read only). returns 0. 0msr_en msr enable. set to 1 to enable access to model specific registers (msrs). amd geode? cs5535 companion device data book 243 geodelink? pci south bridge register descriptions 31506b 6.2.3.6 pci msr ad dress (glpci_pmaddr) 6.2.3.7 pci msr data 0 (glpci_pmdata0) pci index f4h ty p e r / w reset value 00000000h glpci_pmaddr register map 313029282726252423222120191817161514131211109876543210 address glpci_pmaddr bit descriptions bit name description 31:0 address msr address. address field to use in gliu msr accessing. addresses with the most significant 18 bits set to zero address the model specific registers of the glpci_sb mod- ule itself. if any of the 18 most significant bits are set to one, the glpci_sb forwards the msr access to the gliu without performing any address translation. pci index f8h ty p e r / w reset value 00000000h glpci_pmdata0 register map 313029282726252423222120191817161514131211109876543210 data0 glpci_pmdata0 bit descriptions bit name description 31:0 data0 msr data 0. least significant 32-bits of msr data . data0 and data1 r/w are atomic in nature (i.e., if data0 access is made in gl pci_sb then it must followed by data1 access). until the data1 access, the glpci_sb retries all other transactions on the pci bus for 2 15 cycles. after the timeout expires, atom ic nature of data0 and data1 expires and other transactions are accepted. 244 amd geode? cs5535 companion device data book geodelink? pci south bridge register descriptions 31506b 6.2.3.8 pci msr data 1 (glpci_pmdata1) pci index fch ty p e r / w reset value 00000000h glpci_pmdata1 register map 313029282726252423222120191817161514131211109876543210 data1 glpci_pmdata1 bit descriptions bit name description 31:0 data1 msr data 1. most significant 32-bit s of msr data. data0 and data1 r/w are atomic in nature (i.e., if data0 access is made in gl pci_sb then it must followed by data1 access). until the data1 access, glpci_sb wi ll retry all other transactions on pci bus for 2 15 cycles. after this timeout, atomic nat ure for data0 and data1 expires and other transactions are accepted. amd geode? cs5535 companion device data book 245 ac97 audio codec controller register descriptions 31506b 6.3 ac97 audio codec controll er register descriptions the control registers for the ac97 audio codec controller (acc) are divided into two register sets: standard geodelink? device (gld) msrs acc native registers the msrs are accessed via the rdmsr and wrmsr pro- cessor instructions. the msr address is derived from the perspective of the cpu core. see section 4.2 "msr addressing" on page 59 for more details. the acc native registers beg in at acc offset 00h. the system automatically maps the acc registers to a location in memory space or i/o space, but this is hidden from the module?s point of view. at the audio block level, it does not matter if these registers are in memory or i/o space but at the system level, there are si gnificant operational differ- ences (see section "eliminating race conditions") hereaf- ter the acc address are called out as i/o offsets, since i/o mapping is recommended. for native register access, only the lower seven bits of the address are decoded, so the register space is aliased. accesses beyond 7fh alias below 7fh. accesses to addresses that are not implem ented or reserved are ?don?t cares? (i.e. writes do nothing, reads return 0s). tables 6-8 and 6-9 are acc register summary tables that include reset values and page references where the bit descriptions are provided. eliminating race conditions all i/o writes are sequence lo cked, that is, completion of the write at the target is co nfirmed before the executing processor proceeds to the ne xt instruction. all memory writes are posted, that is, the executing processor pro- ceeds to the next instruction immediately after the write whether or not the write has completed. write posting can lead to out of order execut ion. reading the register to which a write has been posted, forces any pending posted write to execute if it has not already done so. consider this example. assume an audio master is per- forming an access to system memory and register access is temporarily blocked. if the processor was servicing an interrupt, a write to clear the interrupt would post to a mem- ory mapped register but not execute immediately, that is, the interrupt would not immediat ely clear. if the processor then enabled the programmable interrupt controller (pic) for new interrupts, then the ?not immediately cleared? inter- rupt would cause a false new interrupt, a form of a race condition. this type of race condition can be eliminated by placing the audio registers in i/o space, or, by performing a register read to any register having a pending posted write that is capable of creating a race condition. table 6-8. standard geodelink? device msrs summary msr address type register name reset value reference 51500000h ro gld capabilities msr (acc_gld_msr_cap) 00000000_002330xxh page 248 51500001h r/w gld master configuration msr (acc_gld_msr_config) 00000000_0000f000h page 248 51500002h r/w gld smi msr (acc_gld_msr_smi) 00000000_00000000h page 249 51500003h r/w gld error msr (acc_gld_msr_error) 00000000_00000000h page 250 51500004h r/w gld power management msr (acc_gld_msr_pm) 00000000_00000000h page 251 51500005h r/w gld diagnostic msr (acc_gld_msr_diag) 00000000_00000000h page 251 246 amd geode? cs5535 companion device data book ac97 audio codec controller register descriptions 31506b table 6-9. acc native registers summary acc i/o offset type width (bits) name reset value reference 00h r/w 32 codec gpio status register (acc_gpio_status) 00000000h page 252 04h r/w 32 codec gpio control register (acc_gpio_cntl) 00000000h page 253 08h r/w 32 codec status register (acc_codec_status) 00000000h page 253 0ch r/w 32 codec control register (acc_codec_cntl) 00000000h page 254 10h-11h --- --- not used --- --- 12h ro 16 second level audio irq status regis- ter (acc_irq_status) 00000000h page 256 14h r/w 32 bus master engine control register (acc_engine_cntl) 00000000h page 257 18h-1fh --- --- not used --- --- 20h r/w 8 bus master 0 command (acc_bm0_cmd) 00h page 258 21h rc 8 bus master 0 irq status (acc_bm0_status) 00h page 259 22h-23h --- --- not used --- --- 24h r/w 32 bus master 0 prd table address (acc_bm0_prd) 00000000h page 260 28h r/w 8 bus master 1 command (acc_bm1_cmd) 08h page 258 29h rc 8 bus master 1 irq status (acc_bm1_status) 00h page 259 2ah-2bh --- --- not used --- --- 2ch r/w 32 bus master 1 prd table address (acc_bm1_prd) 00000000h page 260 30h r/w 8 bus master 2 command (acc_bm2_cmd) 00h page 258 31h rc 8 bus master 2 irq status (acc_bm2_status) 00h page 259 32h-33h --- --- not used --- --- 34h r/w 32 bus master 2 prd table address (acc_bm2_prd) 00000000h page 260 38h r/w 8 bus master 3 command (acc_bm3_cmd) 08h page 258 39h rc 8 bus master 3 irq status (acc_bm3_status) 00h page 259 3ah-3bh --- --- not used --- --- 3ch r/w 32 bus master 3 prd table address (acc_bm3_prd) 00000000h page 260 40h r/w 8 bus master 4 command (acc_bm4_cmd) 00h page 258 amd geode? cs5535 companion device data book 247 ac97 audio codec controller register descriptions 31506b 41h rc 8 bus master 4 irq status (acc_bm4_status) 00h page 259 42h-43h --- --- not used --- --- 44h r/w 32 bus master 4 prd table address (acc_bm4_prd) 00000000h page 260 48h r/w 8 bus master 5 command (acc_bm5_cmd) 08h page 258 49h rc 8 bus master 5 irq status (acc_bm5_status) 00h page 259 4ah-4bh --- --- not used --- --- 4ch r/w 32 bus master 5 prd table address (acc_bm5_prd) 00000000h page 260 50h r/w 8 bus master 6 command (acc_bm6_cmd) 00h page 258 51h rc 8 bus master 6 irq status (acc_bm6_status) 00h page 259 52h-53h --- --- not used --- --- 54h r/w 32 bus master 6 prd table address (acc_bm6_prd) 00000000h page 260 58h r/w 8 bus master 7 command (acc_bm7_cmd) 00h page 258 59h rc 8 bus master 7 irq status (acc_bm7_status) 00h page 259 5ah-5bh --- --- not used --- --- 5ch r/w 32 bus master 7 prd table address (acc_bm7_prd) 00000000h page 260 60h ro 32 bus master 0 dma pointer (acc_bm0_pntr) 00000000h page 261 64h ro 32 bus master 1 dma pointer (acc_bm1_pntr) 00000000h page 261 68h ro 32 bus master 2 dma pointer (acc_bm2_pntr) 00000000h page 261 6ch ro 32 bus master 3 dma pointer (acc_bm3_pntr) 00000000h page 261 70h ro 32 bus master 4 dma pointer (acc_bm4_pntr) 00000000h page 261 74h ro 32 bus master 5 dma pointer (acc_bm5_pntr) 00000000h page 261 78h ro 32 bus master 6 dma pointer (acc_bm6_pntr) 00000000h page 261 7ch ro 32 bus master 7 dma pointer (acc_bm7_pntr) 00000000h page 261 table 6-9. acc native registers summary acc i/o offset type width (bits) name reset value reference 248 amd geode? cs5535 companion device data book ac97 audio codec controller register descriptions 31506b 6.3.1 standard geodelink? device (gld) msrs 6.3.1.1 gld capabiliti es msr (acc_gld_msr_cap) 6.3.1.2 gld master configurat ion msr (acc_gld_msr_config) msr address 51500000h ty p e r o reset value 00000000_002330xxh acc_gld_msr_cap register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd dev_id rev_id acc_gld_msr_cap bit descriptions bit name description 63:24 rsvd reserved. reads return 0. 23:8 dev_id device id. identifies module (2330h). 7:0 rev_id revision id. identifies module revision. see amd geode? cs5535 companion device specification update document for value. msr address 51500001h ty p e r / w reset value 00000000_0000f000h acc_gld_msr_config register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd prefetch_sel prefetch discard non_coh_wr non_coh_rd rsvd pri rsvd pid acc_gld_msr_config bit descriptions bit name description 63:20 rsvd reserved. reads return 0. 19 prefetch_sel select flexible prefetch policy. 0: fixed read prefetch policy is selected. (default) 1: the acc establishes prefetch policy. 18:16 fix_prefetch fixed read prefetch policy. 000: none. each read takes a complete trip to memory. 001: initial read 08 bytes. read next 8 only when requested. 010: initial read 16 bytes. read next 16 only when requested. 011: initial read 32 bytes. read next 32 only when requested. 100: initial read 32 bytes. read next 32 when 16 bytes left. 101, 110, and 111: reserved. amd geode? cs5535 companion device data book 249 ac97 audio codec controller register descriptions 31506b 6.3.1.3 gld smi msr (acc_gld_msr_smi) the flags are set by internal conditions. the internal conditions are enabled if the en bit is 1. reading the flag bit returns the value; writing 1 clears the flag; writ ing 0 has no effect. (see section 4.8.3 "msr address 2: smi control" on page 74 for further smi/asmi generation details.) 15:14 discard read prefetch discard policy. 00: reserved. 01: discard all data not taken under current local bus grant. 10: discard all data on an y local bus transaction. 11: discard all data on any local bus write transaction. always use this value. 13 non_coh_wr non-coherent write. 0: write requests are coherent. 1: write requests are non-cohe rent. always use this value. 12 non_coh_rd non-coherent read. 0: read requests are coherent. 1: read requests are non-coherent. always use this value. 11:7 rsvd reserved. reads as 0. 6:4 pri priority level. always write 0. 3 rsvd (ro) reserved (read only). returns 0. 2:0 pid priority id. always write 0. msr address 51500002h ty p e r / w reset value 00000000_00000000h acc_gld_msr_smi register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd irq_ssmi_flag 313029282726252423222120191817161514131211109876543210 rsvd irq_ssmi_en acc_gld_msr_config bit descriptions (continued) bit name description 250 amd geode? cs5535 companion device data book ac97 audio codec controller register descriptions 31506b 6.3.1.4 gld error msr (acc_gld_msr_error) the flags are set by internal conditions. the internal conditions are enabled if the en bit is 1. reading the flag bit returns the value; writing 1 clears the flag; writ ing 0 has no effect. (see section 4.8.3 "msr address 2: smi control" on page 74 for further details.) acc_gld_msr_smi bit descriptions bit name description 63:33 rsvd reserved. reads return 0. 32 irq_ssmi_flag irq ssmi flag. if high, records that an ssmi was generated because the acc inter- rupt signal transitioned from 0 to 1. this bit is unaffected when the interrupt transitions from 1 to 0. write 1 to clear; writing 0 ha s no effect. irq_ssmi_en (bit 1) must be set to enable this event and set flag. 31:1 rsvd reserved. reads return 0. 0 irq_ssmi_en irq ssmi enable. write 1 to enable irq_ssmi_flag (bit 32) and to allow the event to generate an ssmi. msr address 51500003h ty p e r / w reset value 00000000_00000000h acc_gld_msr_error register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd unexp_type_err_flag 313029282726252423222120191817161514131211109876543210 rsvd unexp_type_err_en amd geode? cs5535 companion device data book 251 ac97 audio codec controller register descriptions 31506b 6.3.1.5 gld power management msr (acc_gld_msr_pm) 6.3.1.6 gld diagnostic msr (acc_gld_msr_diag) this register is reserved for internal use by amd and should not be written to. acc_gld_msr_error bit descriptions bit name description 63:33 rsvd reserved. reads return 0. 32 unexp_type_ err_flag unexpected type error flag. if high, records that an err was generated due to either an unexpected type event or a master response packet with the excep bit set has been received. write 1 to clear; wr iting 0 has no effe ct. unexp_type_err_en (bit 1) must be set to enable this event and set flag. 31:1 rsvd reserved. reads return 0. 0 unexp_type_ err_en unexpected type error enable. write 1 to enable un exp_type_err_flag (bit 32) and to allow the event to generate an err. msr address 51500004h ty p e r / w reset value 00000000_00000000h acc_gld_msr_pm register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd p mode1 p mode0 acc_gld_msr_pm bit descriptions bit name description 63:62 rsvd reserved. reads return value written. 61:32 rsvd reserved. reads return 0. 31:4 rsvd reserved. reads return 0. 3:2 pmode1 power mode 1. power mode for lbus clock. 00: disable clock gating. clocks are always on. 01: enable active hardware clock gating. clock goes off whenever the lbus circuits are not busy. 10: reserved. 11: reserved. 1:0 pmode0 power mode 0. power mode for gliu clock 00: disable clock gating. clocks are always on. 01: enable active hardware clock gating. clock goes off whenever the gliu circuits are not busy. 10: reserved. 11: reserved. msr address 51500005h ty p e r / w reset value 00000000_00000000h 252 amd geode? cs5535 companion device data book ac97 audio codec controller register descriptions 31506b 6.3.2 acc native registers 6.3.2.1 codec gpio status register (acc_gpio_status) acc i/o offset 00h ty p e r / w reset value 00000000h acc_gpio_status register map 313029282726252423222120191817161514131211109876543210 gpio_en int_en wu_int_en rsvd int_flag wu_int_flag pin_sts acc_gpio_status bit descriptions bit name description 31 gpio_en gpio enable. this bit determines if the codec gpio pin data is sent out in slot 12 of the serial output stream. 0: send 0s and tag slot 12 as invalid. 1: send gpio pin data and tag slot valid. 30 int_en codec gpio interrupt enable. allow a codec gpio interr upt to set the codec gpio interrupt flag and generate an irq. 0: disable. 1: enable. a gpio interrupt is defined by se rial data in slot 12, bit 0 29 wu_int_en codec gpio wakeup interrupt enable. allow a codec gpio wakeup interrupt to set the codec gpio wakeup interrupt flag and generate an irq. 0: disable. 1: enable. a codec gpio wakeup interrupt is defined as a 0-to-1 transition of ac_s_in or ac_s_in2 while the codec is powered down. th is bit can only be set after the codec(s) are powered down (see audio driver power-up/down programming model on page 98). 28:22 rsvd reserved. reads return 0. 21 int_flag codec gpio interrupt flag (read to clear). if the gpio interrupt is enabled (bit 30 = 1) then this flag is set upon a codec gpio inte rrupt event (serial data in slot 12, bit 0 = 1), and an irq is generated. 20 wu_int_flag codec gpio wakeup interrup t flag (read to clear). if the gpio wakeup interrupt is enabled (bit 29 = 1), then this flag is set when a gpio wakeup interrupt occurs, and an irq is generated. 19:0 pin_sts codec gpio pin status (read only). this is the gpio pin stat us that is received from the codec in slot 12 of the serial input stream . this is updated every time slot 12 of the input stream is tagged valid. note: all 20 bits of input slot 12 are visible in this register, including reserved bits within slot 12. amd geode? cs5535 companion device data book 253 ac97 audio codec controller register descriptions 31506b 6.3.2.2 codec gpio control register (acc_gpio_cntl) 6.3.2.3 codec status register (acc_codec_status) acc i/o offset 04h ty p e r / w reset value 00000000h acc_gpio_cntl register map 313029282726252423222120191817161514131211109876543210 rsvd pin_data acc_gpio_cntl bit descriptions bit name description 31:20 rsvd reserved. reads return 0. 19:0 pin_data codec gpio pin data. this is the gpio pin data that is sent to the codec in slot 12 of the serial output stream. note: all 20 bits of the output slot 12 ar e controllable through this register, even though some are reserved per the ac97 spec and should be set to zero. acc i/o offset 08h ty p e r / w reset value 00000000h acc_codec_status register map 313029282726252423222120191817161514131211109876543210 sts_add prm_rdy_sts sec_rdy_sts sdatain2_en bm5_sel bm4_sel rsvd sts_new rsvd sts_data acc_codec_status bit descriptions bit name description 31:24 sts_add codec status address (read only). address of the register for which status is being returned. this address comes from slot 1 bits [19:12] of the serial input stream. note: bit 19 of slot 1 is reserved, but still observable by software. 23 prm_rdy_sts primary codec ready (read only). indicates the ready stat us of the primary codec (slot 0, bit 15). software should not access the codec or enable any bus masters until this bit is set. this bit is cleared when the ac link shutdown bit is set in the codec control register (acc i/o offset 0ch[18]). 22 sec_rdy_sts secondary codec ready (read only). indicates the ready st atus of the secondary codec (slot 0, bit 15). software should not access the codec or enable any bus masters until this bit is set. this bit is cleared when the ac link shutdown bit is set in the codec control register (acc i/o offset 0ch[18]). 254 amd geode? cs5535 companion device data book ac97 audio codec controller register descriptions 31506b 6.3.2.4 codec control re gister (acc_codec_cntl) since this register could potentially be accessed by both an a udio driver and a modem driver running at the same time, it is expected that all writes occur as atomic read-modify-write accesses. 21 sdatain2_en enable second serial data input (ac_s_in2). 0: disable. 1: enable. for the second serial input to function, this bit must be set. this is functionally anded with the ac_s_in2 port of the acc. often, it may be necessary to configure a corre- sponding i/o pin as an input on the chip containing the acc. 20 bm5_sel audio bus master 5 ac97 slot select. selects the serial input slot for audio bus mas- ter 5 to receive data. 0: slot 6. 1: slot 11. 19 bm4_sel audio bus master 4 ac97 slot select. selects slot for audio bus master 4 to transmit data. 0: slot 6. 1: slot 11. 18 rsvd reserved. reads return 0 17 sts_new codec status new (read to clear). indicates if the status data in bits [15:0] is new: 0: not new. 1: new. this bit is set by hardware after receiving valid codec status data in slot 2 of the input stream. upon issuing a read to the codec regist ers, software should wait for this flag to indicate that the corresponding data has been returned. 16 rsvd reserved . reads return 0. 15:0 sts_data codec status data (read only). this is the codec status data that is received from the codec in slot 2, bits [19: 4] of the serial input stream. this is used for reading the contents of registers inside the ac97 codec. acc i/o offset 0ch ty p e r / w reset value 00000000h acc_codec_cntl register map 313029282726252423222120191817161514131211109876543210 rw_cmd cmd_add comm _sel pd_prim pd_sec rsvd lnk_shtdwn lnk_wrmrst cmd_new cmd_data acc_codec_status bit descriptions (continued) bit name description amd geode? cs5535 companion device data book 255 ac97 audio codec controller register descriptions 31506b acc_codec_cntl bit descriptions bit name description 31 rw_cmd codec read/write command. this bit specifies a read or write operation targeting the ac97 codec?s registers. 0: write. 1: read. this bit determines whether slot 1, bit 19 of the serial output stream will be high or low. 30:24 cmd_add codec command address. address of the codec control register for which the com- mand is being sent. this address goes in slot 1, bits [18:12] of th e serial output stream. this is used for specifying the address of a register in the ac97 codec (for reading or writing). 23:22 comm_sel audio codec communication. selects which codec to communicate with (for register reads/writes): 00: codec 1 (primary) 01: codec 2 (secondary) 10: codec 3 11: codec 4 these bits determine output slot 0, bits [1:0]. when these bits are non-zero, bits [14:13] of output slot 0 must be set to zeros rega rdless of the validity of slot 1 and slot 2. 21 pd_prim power-down semaphore for primary codec. this bit is used by software in conjunc- tion with bit 20 to coordinate the power-down of the two codecs. this bit is intended to be set by the audio driver to indicate to the modem driver that the audio codec has been prepared for power-down. internally it does not control anything, and is simply a memory bit. 20 pd_sec power-down semaphore for secondary codec. this bit is used by software in con- junction with bit 21 to coordinate the power-dow n of the two codecs. this bit is intended to be set by the modem driver to indicate to the audio driver that the modem codec has been prepared for power-down. internally it does not control anything, and is simply a memory bit. 19 rsvd reserved. reads return 0. 18 lnk_shtdwn ac link shutdown. informs the controller that the ac link is being shutdown. this bit should be set at the same time that the codec power-down command is issued to the codec. setting this bit also clears both codec read y bits in the codec status register (acc i/o offset 08h[23:22]). issuing a warm reset via bit 17 clears this bit. if the codec has been powered off and back on, a warm reset is unnecessary, this bit should be cleared manually. 17 lnk_wrm_rst ac link warm reset. setting this bit initiates the ac link/codec warm reset process. it is automatically cleared by hardware once the serial bit clock resumes. this should only be set when the codec(s) are powered down. once set, software should then wait for ?codec ready? before accessing the codec. 256 amd geode? cs5535 companion device data book ac97 audio codec controller register descriptions 31506b 6.3.2.5 second level audio irq status register (acc_irq_status) 16 cmd_new codec command new. indicates if the codec command in bits [31:22] (and [15:0] for writes) is new. 0: not new. 1: new. this bit is to be set by software when a new command is loaded. it is cleared by hard- ware when the command is sent to the codec. software must wait for this bit to clear before loading another command. this bit can not be cleared by software. w hen the codec_cntl register is written by software with bit 16 cleared, then bits [31:22] and [15:0] are unaffe cted. thus, bit 16 is an "enable" allowing bits [31:22] and [15:0] to be changed. 15:0 cmd_data codec command data. this is the command data being s ent to the codec in slot 2, bits [19:12] of the serial output stream. this is used for writing data into one of the reg- isters in the ac97 codec. the contents ar e only sent to the codec for write commands (bit [31] = 0). for reads slot 2, bits[19:12] are stuffed with 0s. acc i/o offset 12h ty p e r o reset value 00000000h acc_irq_status register map 1514131211109876543210 rsvd bm7_irq_sts bm6_irq_sts bm5_irq_sts bm4_irq_sts bm3_irq_sts bm2_irq_sts bm1_irq_sts bm0_irq_sts wu_irq_sts irq_sts acc_irq_status bit descriptions bit name description 15:10 rsvd reserved. reads return 0. 9 bm7_irq_sts audio bus master 7 irq status. if this bit is set, it indicates that an irq was caused by an event occurring on audio bus master 7. reading the bus master 7 irq status register clears this bit. 8 bm6_irq_sts audio bus master 6 irq status. if this bit is set, it indicates that an irq was caused by an event occurring on audio bus master 6. reading the bus master 6 irq status register clears this bit. 7 bm5_irq_sts audio bus master 5 irq status. if this bit is set, it indicates that an irq was caused by an event occurring on audio bus master 5. reading the bus master 5 irq status register clears this bit. 6 bm4_irq_sts audio bus master 4 irq status. if this bit is set, it indicates that an irq was caused by an event occurring on audio bus master 4. reading the bus master 4 irq status register clears this bit. 5 bm3_irq_sts audio bus master 3 irq status. if this bit is set, it indicates that an irq was caused by an event occurring on audio bus master 3. reading the bus master 3 irq status register clears this bit. acc_codec_cntl bit descriptions (continued) bit name description amd geode? cs5535 companion device data book 257 ac97 audio codec controller register descriptions 31506b 6.3.2.6 bus master engine cont rol register (acc_engine_cntl) 4 bm2_irq_sts audio bus master 2 irq status. if this bit is set, it indicates that an irq was caused by an event occurring on audio bus master 2. reading the bus master 2 irq status register clears this bit. 3 bm1_irq_sts audio bus master 1 irq status. if this bit is set, it indicates that an irq was caused by an event occurring on audio bus master 1. reading the bus master 1 irq status register clears this bit. 2 bm0_irq_sts audio bus master 0 irq status. if this bit is set, it indicates that an irq was caused by an event occurring on audio bus master 0. reading the bus master 0 irq status register clears this bit. 1wu_irq_sts codec gpio wakeup irq status. if this bit is set, it indicates that an irq was caused by a gpio wakeup interrupt event (serial data in going high during power-down). reading the codec gpio status register clears this bit. 0irq_sts codec gpio irq status. if this bit is set, it indicates that an irq was caused by a gpio event in the ac97 codec (slot 12, bit 0). reading the codec gpio status regis- ter clears this bit. acc i/o offset 14h ty p e r / w reset value 00000000h acc_engine_cntl register map 313029282726252423222120191817161514131211109876543210 rsvd ssnd_mode acc_engine_cntl bit descriptions bit name description 31:1 rsvd reserved. reads return 0. 0 ssnd_mode surround sound (5.1) synchronization mode. enables synchronization of bus mas- ters 0, 4, 6, and 7. this bit should be set whenever playing back multi-channel surround sound. it ensures that the four bus master s stay synchronized and do not introduce any temporal skew between the separate channels. acc_irq_status bit descriptions (continued) bit name description 258 amd geode? cs5535 companion device data book ac97 audio codec controller register descriptions 31506b 6.3.2.7 audio bus master 0-7 co mmand registers (acc_bm[x]_cmd) bus master 0 command (acc_bm0_cmd) bus master 1 command (acc_bm1_cmd) bus master 2 command (acc_bm2_cmd) bus master 3 command (acc_bm3_cmd) bus master 4 command (acc_bm4_cmd) bus master 5 command (acc_bm5_cmd) bus master 6 command (acc_bm6_cmd) bus master 7 command (acc_bm7_cmd) acc i/o offset 20h ty p e r / w reset value 00h acc i/o offset 28h ty p e r / w reset value 08h acc i/o offset 30h ty p e r / w reset value 00h acc i/o offset 38h ty p e r / w reset value 08h acc i/o offset 40h ty p e r / w reset value 00h acc i/o offset 48h ty p e r / w reset value 08h acc i/o offset 50h ty p e r / w reset value 00h acc i/o offset 58h ty p e r / w reset value 00h acc_bm[x]_cmd register map 76543210 rsvd rw byte_ord bm_ctl acc_bm[x]_cmd bit descriptions bit name description 7:4 rsvd reserved. reads return 0 3rw (ro) read or write (read only). indicates the transfer direction of the audio bus master. this bit always reads 0 for bm [0,2,4,6,7]. this bit always reads 1 for bm[1,3,5]. 0: memory to codec. 1: codec to memory. 2 byte_ord byte-order. sets the byte order for 16-bit sa mples that this bus master uses. 0: little endian (intel) byte-order (lsbs at lower address). 1: big endian (motorola) byte-o rder (msbs at lower address). 1:0 bm_ctl bus master pause/enable control. enables, disables, or pauses the bus master. 00: disable bus master. 01: enable bus master. 10: reserved. 11: pause bus master (if currently enabled) or do nothing (if currently disabled). when the bus master is enabled by writing 01 , the bus master starts up by using the address in its associated prd table address register. writing 00 while the bus master is enabled causes the bus master to stop immediately. upon resuming the bus master uses the address in its prd table address register. the prd table address register must be re-initialized by software before enabling the bus master, or there is a risk that the bus master may overstep the bounds of the prd table. note: when the bus master reaches a prd with the eot bit set, these bits are set to 00. amd geode? cs5535 companion device data book 259 ac97 audio codec controller register descriptions 31506b 6.3.2.8 audio bus master 0-7 irq st atus registers (acc_bm[x]_status) bus master 0 irq status (acc_bm0_status) bus master 1 irq status (acc_bm1_status) bus master 2 irq status (acc_bm2_status) bus master 3 irq status (acc_bm3_status) bus master 4 irq status (acc_bm4_status) bus master 5 irq status (acc_bm5_status) bus master 6 irq status (acc_bm6_status) bus master 7 irq status (acc_bm7_status) acc i/o offset 21h ty p e r c reset value 00h acc i/o offset 29h ty p e r c reset value 00h acc i/o offset 31h ty p e r c reset value 00h acc i/o offset 39h ty p e r c reset value 00h acc i/o offset 41h ty p e r c reset value 00h acc i/o offset 49h ty p e r c reset value 00h acc i/o offset 51h ty p e r c reset value 00h acc i/o offset 59h ty p e r c reset value 00h acc_bm[x]_status register map 76543210 rsvd bm_eop_err eop acc_bm[x]_status bit descriptions bit name description 7:2 rsvd reserved. reads return 0 1 bm_eop_err bus master error. if this bit is set, it indicates that hardware encountered a second eop before software cleared the first eop. if hardware encounters a second eop (end of page) before software clears the first eop, it causes the bus master to pause until th is register is read to clear the error. read to clear. 0eop end of page. if this bit is set, it indicates the bu s master transferred data that is marked by the eop bit in the prd table (bit 30). read to clear. 260 amd geode? cs5535 companion device data book ac97 audio codec controller register descriptions 31506b 6.3.2.9 audio bus master 7-0 prd tabl e address registers (acc_bm[x]_prd) bus master 0 prd table address (acc_bm0_prd) bus master 1 prd table address (acc_bm1_prd) bus master 2 prd table address (acc_bm2_prd) bus master 3 prd table address (acc_bm3_prd) bus master 4 prd table address (acc_bm4_prd) bus master 5 prd table address (acc_bm5_prd) bus master 6 prd table address (acc_bm6_prd) bus master 7 prd table address (acc_bm7_prd) acc i/o offset 24h ty p e r / w reset value 00000000h acc i/o offset 2ch ty p e r / w reset value 00000000h acc i/o offset 34h ty p e r / w reset value 00000000h acc i/o offset 3ch ty p e r / w reset value 00000000h acc i/o offset 44h ty p e r / w reset value 00000000h acc i/o offset 4ch ty p e r / w reset value 00000000h acc i/o offset 54h ty p e r / w reset value 00000000h acc i/o offset 5ch ty p e r / w reset value 00000000h acc_bm[x]_prd register map 313029282726252423222120191817161514131211109876543210 prd_pntr rsvd acc_bm[x]_prd bit descriptions bit name description 31:2 prd_pntr pointer to the physical region descriptor table. this register is a prd table pointer for audio bus master [x]. when written, this register po ints to the first entry in a prd table. once audio bus mas- ter [x] is enabled (command register bit 0 = 1), it loads the pointer and updates this register to the next prd by adding 08h. when read, this register points to the next prd. 1:0 rsvd reserved. reads return 0 amd geode? cs5535 companion device data book 261 ac97 audio codec controller register descriptions 31506b 6.3.2.10 bus master 0-7 dma pointer registers (acc_bm[x]_pntr) bus master 0 dma pointer (acc_bm0_pntr) bus master 1 dma pointer (acc_bm1_pntr) bus master 2 dma pointer (acc_bm2_pntr) bus master 3 dma pointer (acc_bm3_pntr) bus master 4 dma pointer (acc_bm4_pntr) bus master 5 dma pointer (acc_bm5_pntr) bus master 6 dma pointer (acc_bm6_pntr) bus master 7 dma pointer (acc_bm7_pntr) acc i/o offset 60h ty p e r o reset value 00000000h acc i/o offset 64h ty p e r o reset value 00000000h acc i/o offset 68h ty p e r o reset value 00000000h acc i/o offset 6ch ty p e r o reset value 00000000h acc i/o offset 70h ty p e ro reset value 00000000h acc i/o offset 74h ty p e ro reset value 00000000h acc i/o offset 78h ty p e ro reset value 00000000h acc i/o offset 7ch ty p e ro reset value 00000000h acc_bm[x]_pntr register map 313029282726252423222120191817161514131211109876543210 dma_pntr acc_bm[x]_pntr bit descriptions bit name description 31:0 dma_pntr dma buffer pointer. address of current sample being fetched (bm [0,2,4,6,7]) or writ- ten (bm [1,3,5]) by the dma bus master [x]. 262 amd geode? cs5535 companion device data book ata-5 controller register descriptions 31506b 6.4 ata-5 controller register descriptions the control registers for the ata-5 compatible ide control- ler (atac) are divided into three sets: standard geodelink device (gld) msrs atac specific msrs atac native registers the msrs are accessed via the rdmsr and wrmsr pro- cessor instructions. the msr address is derived from the perspective of the cpu core. see section 4.2 "msr addressing" on page 59 for more details. the native registers are acce ssed as i/o offsets from a gliu iod descriptor and are byte, word and dword accessible. tables 6-10 through 6-12 are atac register summary tables that include reset values and page references where the bit descriptions are provided. table 6-10. standard geodelink? device msrs summary msr address type register name reset value reference 51300000h ro gld capabilities msr (atac_gld_msr_cap) 00000000_002470xxh page 263 51300001h r/w gld master configuration msr (atac_gld_msr_config) 00000000_0000f000h page 264 51300002h r/w gld smi msr (atac_gld_msr_smi) 00000000_00000000h page 265 51300003h r/w gld error msr (atac_gld_msr_error) 00000000_00000100h page 266 51300004h r/w gld power management msr (atac_gld_msr_pm) 00000000_00000000h page 267 51300005h r/w gld diagnostic msr (atac_gld_msr_diag) 00000000_00000000h page 268 table 6-11. atac specific msrs summary msr address type register name reset value reference 51300008h r/w i/o base address (atac_io_bar) 00000000_00000001h page 269 51300009h --- unused --- --- 51300010h r/w reset decode (atac_reset) 00000000_00000000h page 269 51300011h- 5130001fh --- unused --- --- 51300020h r/w channel 0 drive 0 pio (atac_ch0d0_pio) 00000000_00009172h page 270 51300021h r/w channel 0 drive 0 dma (atac_ch0d0_dma) 00000000_00077771h page 271 51300022h r/w channel 0 drive 1 pio (atac_ch0d1_pio) 00000000_00009172h page 273 51300023h r/w channel 0 drive 1 dma (atac_ch0d1_dma) 00000000_00077771h page 273 51300024h r/w pci abort error (atac_pci_abrterr) 00000000_00000000h page 273 amd geode? cs5535 companion device data book 263 ata-5 controller register descriptions 31506b 6.4.1 standard geodelink? device (gld) msrs 6.4.1.1 gld capabilities msr (atac_gld_msr_cap) table 6-12. atac native registers summary atac i/o offset type width (bits) register name reset value reference 00h r/w 8 bus master 0 command - primary (atac_bm0_cmd_prim) 00h page 274 01h --- --- unused --- --- 02h r/w 8 bus master 0 status - primary (atac_bm0_sts_prim) 00h page 274 03h --- --- unused --- --- 04h r/w 32 bus master 0 prd table address - pri- mary (atac_bm0_prd) 00000000h page 275 08h-0fh --- --- reserved. write accesses are ignored, read accesses return 0. msr address 51300000h ty p e r o reset value 00000000_002470xxh atac_gld_msr_cap register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd dev_id rev_id atac_gld_msr_cap bit descriptions bit name description 63:24 rsvd reserved. reads as 0. 23:8 dev_id device id. identifies module (2470h). 7:0 rev_id revision id. identifies module revision. see amd geode?cs5535 companion device specification update document for value. 264 amd geode? cs5535 companion device data book ata-5 controller register descriptions 31506b 6.4.1.2 gld master configurat ion msr (atac_gld_msr_config) msr address 51300001h ty p e r / w reset value 00000000_0000f000h atac_gld_msr_config register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd prg_prefetch prefetch_sel fix_prefetch discard non_coh_wr non_coh_rd rsvd pri rsvd pid atac_gld_msr_config bit descriptions bit name description 63:23 rsvd reserved. reads as 0. 22:20 prg_prefetch programmable prefetch code. when bit 19 is set, these three bits determine the prefetch policy for non-prd read accesses. prd read accesses use 001 setting. 000: no prefetch. 001: prefetch 8 bytes. 010: prefetch 16 bytes. 011: prefetch 32 bytes. 100: prefetch 32 bytes, additional 32 bytes prefetch after 16 bytes have been read. all other values are reserved. 19 prefetch_sel prefetch select. select between fixed (when clear) or programmable prefetch policy codes (when set). 18:16 fix_prefetch fixed prefetch code. when bit 19 is clear, these three bits determine the prefetch pol- icy for all read accesses. 000: no prefetch. 001: prefetch 8 bytes. 010: prefetch 16 bytes. 011: prefetch 32 bytes. 100: prefetch 32 bytes, additional 32 bytes prefetch after 16 bytes have been read. all other values are reserved. 15:14 discard discard. read prefetch discard policy. 00: reserved. 01: discard all data not taken under current local bus grant. 10: discard all data on an y local bus transaction. 11: discard all data on any local bus write transaction. always use this value. (default) 13 non_coh_wr non-coherent write. 0: write requests are coherent. 1: write requests are non-coherent. always use this value. (default) 12 non_coh_rd non-coherent read. 0: read requests are coherent. 1: read requests are non-coherent. always use this value. (default) 11:7 rsvd reserved. reads as 0. 6:4 pri priority level. always write 0. amd geode? cs5535 companion device data book 265 ata-5 controller register descriptions 31506b 6.4.1.3 gld smi msr (atac_gld_msr_smi) the flags are set by internal conditions. the internal conditions are enabled if the en bit is 1. reading the flag bit returns the value; writing 1 clears the flag; writ ing 0 has no effect. (see section 4.8.3 "msr address 2: smi control" on page 74 for further details.) 3 rsvd (ro) reserved (read only). returns 0. 2:0 pid priority id. always write 0. msr address 51300002h ty p e r / w reset value 00000000_00000000h atac_gld_msr_smi register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd ide_ch0_irq_asmi_flag ide_pio_ssmi_flag 313029282726252423222120191817161514131211109876543210 rsvd ide_ch0_irq_asmi_en ide_pio_ssmi_en atac_gld_msr_smi bit descriptions bit name description 63:34 rsvd reserved. read returns 0. 33 ide_ch0_irq_ asmi_flag ide channel 0 irq asmi flag. if high, records that an asmi was generated due to an irq event. write 1 to clear; writing 0 has no effect. ide_ch0_irq_asmi_en (bit 1) must be set to enable this event and set flag. 32 ide_pio_ssmi flag ide programmable i/o ssmi flag. if high, records that an ssmi was generated due to a pio transaction occurring during a dma command. write 1 to clear; writing 0 has no effect. ide_pio_smi_en (bit 0) must be set to enable this event and set flag. 31:2 rsvd reserved. read returns 0. 1 ide_ch0_irq_ asmi_en ide channel 0 irq asmi mask. write 1 to enable ide_ch0_irq_asmi_flag (bit 33) and to allow the event to generate an asmi. 0 ide_pio_ssmi en ide programmable i/o ssmi mask. write 1 to enable ide_pio_ssmi_flag (bit 32) and to allow the event to generate an ssmi. atac_gld_msr_config bit descriptions (continued) bit name description 266 amd geode? cs5535 companion device data book ata-5 controller register descriptions 31506b 6.4.1.4 gld error msr (atac_gld_msr_error) the flags are set by internal conditions. the internal conditions are enabled if the en bit is 1. reading the flag bit returns the value; writing 1 clears t he flag; writing 0 has no effect. msr address 51300003h ty p e r / w reset value 00000000_00000100h atac_gld_msr_error register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd ide_pio_err_flag resp_excep_err_flag ssmi_err_flag blockio_ssmi_flag unexp_type_err_flag 313029282726252423222120191817161514131211109876543210 rsvd blockio rsvd ide_pio_err_en resp_excep_err_en ssmi_err_en blockio_ssmi_en unexp_type_err_en atac_gld_msr_error bit descriptions bit name description 63:37 rsvd reserved. write as read. 36 ide_pio_err_ flag ide pio error. if high, records that an err was generated due to a pio access during a dma command. write 1 to clear; writing 0 has no effect. ide_pio_err_en (bit 4) must be high to generate err and set flag. if ide_pio_err_en = 1 and ide_pio_asmi_en (msr 51300002h[0]) = 0 and the error occurs, this bit gets set, and the glcp master error signal is asserted. if both ide_pio_err_en = 1 and ide_pio_asmi_en = 1 and the error occurs, this bit gets set, the glcp master error sig nal is asserted, and an ssmi is generated. 35 resp_excep_ err_flag response exception error flag. if high, records that an err was generated and the glcp master error signal was asserted due to the excep bit being set in the response packet. write 1 to clear; writing 0 has no effect. resp_excep_err_en (bit 3) must be high to enable these events. 34 ssmi_err_flag ssmi error flag. if high, records that an err was generated due to an uncleared ssmi. write 1 to clear; writing 0 has no effect. ssmi_err_en (bit 2) must be high to generate err and set flag. if ssmi_err_en and ide_pio_ssmi_flag (msr 51300002h[32]) = 1 and the error occurs, this bit gets set, the glcp master error signal is asserted, lb_slav_rdy is asserted, and an ssmi is generated. 33 blockio_ssmi_ flag ssmi on i/o write during dma. if high, records that an i/o write during dma had occurred. write 1 to clear; writing 0 has no effect. blockio_ssmi_en (bit 1) and blockio (bit 8) must be high to set flag. amd geode? cs5535 companion device data book 267 ata-5 controller register descriptions 31506b 6.4.1.5 gld power manageme nt msr (atac_gld_msr_pm) 32 unexp_type_ err_flag unexpected type error flag. if high, records that err was generated and the glcp master error signal was asserted due to an unexpected type occurring. write 1 to clear; writing 0 has no effect. unexp_type_err_flag (bit 0) must be high to generate err, set flag, and assert the glcp master error signal. once clear, the glcp master error signal is de-asserted. 31:9 rsvd reserved. write as read. 8blockio ide device register i/o in dma blocked. when this bit is set, and if ide_pio_ssmi_en (msr 51300002h[0]) is 0 a nd if ide_pio_err_en (bit 4) is 0, ignore all pio writes during dma, return 80h on all pio reads during dma, and gener- ate an ssmi. the glcp master error signal will not be asserted. when this bit is clear, ide device register i/o during dma will not be blocked. 7:5 rsvd reserved. write as read. 4ide_pio_ err_en ide pio error enable. write 1 to enable ide_pio_err_flag (bit 36) and to allow a pio access during a dma command event to generate an err. 3 resp_excep_ err_en response exception enable. write 1 to enable resp_exc ep_err_flag (bit 35) and to allow when the excep bit is set in the response packet to generate an err. 2 ssmi_err_en uncleared ssmi enable. write 1 to enable ssmi_err_flag (bit 34) and to the allow an uncleared ssmi to generate an err. 1 blockio_ssmi_ en ssmi on i/o write enable. write 1 to enable blockio_ssmi_flag (bit 33) when i/o writes during dma with blockio (bit 8) set occur. 0 unexp_type_ err_flag unexpected type enable. write 1 to enable unexp_type_err_flag (bit 32) and to the allow an unexpected type occurring to generate an err. msr address 51300004h ty p e r / w reset value 00000000_00000000h atac_gld_msr_pm register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd iomodea rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd pmode1 pmode0 atac_gld_msr_error bit descriptions (continued) bit name description 268 amd geode? cs5535 companion device data book ata-5 controller register descriptions 31506b 6.4.1.6 gld diagnostic msr (atac_gld_msr_diag) this register is reserved for internal use by amd and should not be written to. atac_gld_msr_pm bit descriptions bit name description 63:50 rsvd reserved. returns 0 on read. 49:48 iomodea i/o mode a control. these bits determine how the associated ide inputs and outputs behave when the pmc asserts two internal si gnals that are controlled by pms i/o off- set 20h and 0ch. the list of affected signals is in table 4-12 "sleep driven ide sig- nals" on page 79. 00: no gating of i/o cells during a sleep sequence (default). 01: during a power management sleep sequence, force inputs to their non-asserted state when pm_in_slpctl is enabled. 10: during a power management sleep sequence, force inputs to their non-asserted state when pm_in_slpctl is enabled, and park (force) outputs low when pm_out_slpctl is enabled. 11: immediately and unconditionally, force inpu ts to their not asserted state, and park (force) outputs low. 47:4 rsvd reserved. returns 0 on read. 3:2 pmode1 power mode 1. power mode for channel 1 clock domain. 00: disable clock gating. clocks are always on. 01: enable active hardware clock gating. clock goes off whenever this module?s cir- cuits are not busy. 10: reserved. 11: reserved. 1:0 pmode0 power mode 0. power mode for channel 0 clock domain. 00: disable clock gating. clocks are always on. 01: enable active hardware clock gating. clock goes off whenever this module?s cir- cuits are not busy. 10: reserved. 11: reserved. msr address 51300005h ty p e r / w reset value 00000000_00000000h amd geode? cs5535 companion device data book 269 ata-5 controller register descriptions 31506b 6.4.2 atac specific msrs 6.4.2.1 i/o base address (atac_io_bar) this register sets the base address of the i/o mapped bus mast ering ide and controller registers. bits [2:0] are read only (001), indicating an 8-byte i/o address range. 6.4.2.2 reset deco de (atac_reset) msr address 51300008h ty p e r / w reset value 00000000_00000001h atac_io_bar register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd bm_ide_bar_en 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd bm_ide_bar add_rng atac_io_bar bit descriptions bit name description 63:33 rsvd reserved. write as 0. return 0 on read. 32 bm_ide_bar_ en bus mastering ide base address enable. this bit should be set to enable access to the native register set after the base address has been set. 0: disable (i.e., cannot acce ss native registers in atac). 1: enable (normal operation). 31:17 rsvd reserved. write to 0. return 0 on read. 16:3 bm_ide_bar bus mastering ide base address. these bits form the base address of the atac native register set. users may write the full address, including bits [2:0], knowing that bits [2:0] will drop off and be assumed as 000. 2:0 add_rng (ro) address range (read only). hard wired to 001. this indicates that the i/o base address is in units of bytes. msr address 51300010h ty p e r / w reset value 00000000_00000000h atac_reset register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd atac_reset ide_reset 270 amd geode? cs5535 companion device data book ata-5 controller register descriptions 31506b 6.4.2.3 channel 0 drive 0 pio (atac_ch0d0_pio) note: the reset value of this register is not a valid pio mode. atac_reset bit descriptions bit name description 63:2 rsvd reserved. set to 0. return 0 on read. 1 atac_reset ide controller reset. reset the ide controller. 0: normal state (operate). 1: reset. write 0 to clear. this bit is level-sensitive and must be cleared after reset is performed. 0 ide_reset ide reset. reset the ide bus. 0: normal state (operate). 1: reset. write 0 to clear. this bit is level-sensitive and must be cleared after reset is performed. msr address 51300020h ty p e r / w reset value 00000000_00009172h atac_ch0d0_pio register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd piomode t2i t3 t2w t1 t2ic t3c t2wc t1c t2id t3d t2wd t1d atac_ch0d0_pio bit descriptions bit name description 63:32 rsvd reserved. set to 0. if msr 51300021h[31] = 0, format 0. selects slowest piomode per channe l (by comparing bit [19:16] of msr 50302020h and msr 50302022h) for commands. format 0 settings for: pio mode 0 = 0000f7f4h pio mode 1 = 000153f3h pio mode 2 = 000213f1h pio mode 3 = 00035131h pio mode 4 = 00041131h 31:20 rsvd reserved. set to 0. 19:16 piomode pio mode. 0000: pio mode 0 0011: pio mode 3 0001: pio mode 1 0100: pio mode 4 0010: pio mode 2 all other values are reserved 15:12 t2i recovery time. value + 1 cycle. 11:8 t3 ide_iow# data setup time. value + 1 cycle. 7:4 t2w ide_iow# width minus t3. value + 1 cycle. 3:0 t1 address setup time. value + 1 cycle. amd geode? cs5535 companion device data book 271 ata-5 controller register descriptions 31506b 6.4.2.4 channel 0 drive 0 dma (atac_ch0d0_dma) if msr 50302021h[31] = 1, format 1. allows independent control of command and data. format 1 settings for: pio mode 0 = f7f4f7f4h pio mode 1 = 53f3f173h pio mode 2 = 13f18141h pio mode 3 = 51315131h pio mode 4 = 11311131h 31:28 t2ic command cycle recovery time. value + 1 cycle. 27:24 t3c command cycle ide_iow# data setup. value + 1 cycle. 23:20 t2wc command cycle ide_iow# pulse width minus t3. value + 1 cycle. 19:16 t1c command cycle address setup time. value + 1 cycle. 15:12 t2id data cycle recovery time. value + 1 cycle. 11:8 t3d data cycle ide_io w# data setup. value + 1 cycle. 7:4 t2wd data cycle ide_iow# pulse width minus t3. value + 1 cycle. 3:0 t1d data cycle address setup time. value + 1 cycle. note: register settings described as ?val ue + n cycle(s)? will produce timings fo r the indicated parameter as measured in 66 mhz clock cycles. the ?value? that is entered is the desired number of 66 mhz clock cycles in hexadecimal; the actual parameter timing ge nerated by that entry is the entered ?value ? plus the indicated number of ?cycles? (?n?) as listed in the description of that parameter. msr address 51300021h ty p e r / w reset value 00000000_00077771h atac_ch0d0_dma register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pio_form mode66_sel rsvd dma_sel tkr tdr tkw tdw tm pio_form mode66_sel rsvd dma_sel tcrc tss tcyc trp tack atac_ch0d0_pio bit descriptions (continued) bit name description 272 amd geode? cs5535 companion device data book ata-5 controller register descriptions 31506b atac_ch0d0_dma bit descriptions bit name description 63:32 rsvd reserved. set to 0. if bit 20 = 0, multi-word dma. settings for: multi-word dma mode 0 = 7f0ffff3h multi-word dma mode 1 = 7f035352h multi-word dma mode 2 = 7f024241h 31 pio_form pio mode format. 0: format 0. 1: format 1. 30:24 mode66_sel mode 66 select : set to 7fh for 66 mhz system clock. 23:21 rsvd reserved . set to 0. 20 dma_sel dma select . dma operation. 0: multi-word dma. 1: ultra dma. 19:16 tkr ide_ior# recovery time (4-bit). value + 1 cycle. 15:12 tdr ide_ior# pulse width. value + 1 cycle. 11:8 tkw ide_iow# recovery time (4-bit). value + 1 cycle. 7:4 tdw ide_iow# pulse width. value + 1 cycle. 3:0 tm ide_cs0#/cs1# to ide_ior#/iow# setup; ide_cs0#/cs1# setup to ide_dack0#/dack1#. if bit 20 = 1, ultra dma. settings for: ultra dma mode 0 = 7f7436a1h ultra dma mode 1 = 7f733481h ultra dma mode 2 = 7f723261h ultra dma mode 3 = 7f713161h ultra dma mode 4 = 7f703061h 31 pio_form pio mode format. 0: format 0. 1: format 1. 30:24 mode66_sel mode 66 select : set to 7fh for 66 mhz system clock. 23:21 rsvd reserved . set to 011. will read back as 011. 20 dma_sel dma select . dma operation. 0: multi-word dma. 1: ultra dma. 19:16 tcrc crc setup udma in ide_dack#. value + 1 cycle (for host terminate crc setup = tmli + tss). 15:12 tss udma out. value + 1 cycle. 11:8 tcyc data setup and cycle time udma out. value + 2 cycles. 7:4 trp ready to pause time. value + 1 cycle. used only for udma-in. note: trfs + 1 trp on next clock. 3:0 tack ide_cs0#/cs1# setup to ide_dack0#/dack1#. value + 1 cycle. note: register settings described as ?value + n cycle(s)? produce timings for the indicated parameter as measured in 66 mhz clock cycles. the ?value? that is entered is the desired number of 66 mhz clock cycles in hexadecimal; the actual parameter timing ge nerated by that entry is the entered ?value ? plus the indicated number of ?cycles? (?n?) as listed in the description of that parameter. amd geode? cs5535 companion device data book 273 ata-5 controller register descriptions 31506b 6.4.2.5 channel 0 drive 1 pio (atac_ch0d1_pio) refer to section 6.4.2.3 "channel 0 drive 0 pio (atac_ch0d0_pio)" on page 270 for bit descriptions. 6.4.2.6 channel 0 drive 1 dma (atac_ch0d1_dma) refer to section 6.4.2.4 "channel 0 drive 0 dma (atac_ch0d0_dma)" on page 271 for bit descriptions. 6.4.2.7 pci abort error (atac_pci_abrterr) msr address 51300022h ty p e r / w reset value 00000000_00009172h msr address 51300023h ty p e r / w reset value 00000000_00077771h msr address 51300024h ty p e r / w reset value 00000000_00000000h atac_pci_abrterr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 read: rsvd; write: pci_abort 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read: rsvd; write: pci_abort atac_pci_abrterr bit descriptions bit name description 63:0 rsvd/pci_abort reserved. return 0 on read. pci abort. write (of any value) to this register will set bit 1 of bus master 0 status register. 274 amd geode? cs5535 companion device data book ata-5 controller register descriptions 31506b 6.4.3 atac native registers 6.4.3.1 bus master 0 command - primary (atac_bm0_cmd_prim) 6.4.3.2 bus master 0 status - primary (atac_bm0_sts_prim) atac i/o address 00h ty p e r / w reset value 00h atac_bm0_cmd_prim register map 76543210 rsvd rwctl rsvd bmctl atac_bm0_cmd_prim bit descriptions bit name description 7:4 rsvd reserved. set to 0. return 0 on read. 3rwctl read or write control. sets the direction of bus master transfers. 0: pci reads performed. 1: pci writes performed. this bit should not be changed when the bus master is active. 2:1 rsvd reserved. set to 0. return 0 on read. 0bmctl bus master control. controls the state of the bus master. 0: disable master. 1: enable master. bus master operations can be halted by setting bit 0 to 0. once an operation has been halted, it can not be resumed. if bit 0 is set to 0 while a bus master operation is active, the command is aborted and the data transfe rred from the drive is discarded. this bit should be reset after completion of data transfer. atac i/o address 02h ty p e r / w reset value 00h atac_bm0_sts_prim register map 76543210 mode d1dma d0dma rsvd bmint bmerr bmsts atac_bm0_sts_prim bit descriptions bit name description 7 mode (ro) simplex mode (read only). can both the primary and secondary channel operate independently? 0: yes. 1: no (simplex mode). 6d1dma drive 1 dma capable. allows drive 1 to be capable of dma transfers. 0: disable. 1: enable. amd geode? cs5535 companion device data book 275 ata-5 controller register descriptions 31506b 6.4.3.3 bus master 0 prd table address - primary (atac_bm0_prd) 5d0dma drive 0 dma capable. allows drive 0 to be capable of dma transfers. 0: disable. 1: enable. 4:3 rsvd reserved : set to 0. must return 0 on reads. 2bmint bus master interrupt. has the bus master detected an interrupt? 0: no. 1: yes. write 1 to clear. 1bmerr bus master error. has the bus master detected an error during data transfer? (this bit is set by a write access to msr 51300024h.) 0: no. 1: yes. write 1 to clear. 0bmsts (ro) bus master status (read only). is the bus master active? 0: no. 1: yes. atac i/o address 04h ty p e r / w reset value 00000000h atac_bm0_prd register map 313029282726252423222120191817161514131211109876543210 prd_pntr rsvd atac_bm0_prd bit descriptions bit name description 31:2 prd_pntr pointer to the physical region descriptor table. this register is a prd table pointer for ide bus master 0. when written, this register points to the firs t entry in a prd table. once ide bus master 0 is enabled (command register bit 0 = 1), it loads the pointer and updates this register to the next prd by adding 08h. when read, this register points to the next prd. 1:0 rsvd reserved. set to 0. atac_bm0_sts_prim bit descriptions (continued) bit name description 276 amd geode? cs5535 companion device data book usb controller register descriptions 31506b 6.5 usb controller re gister descriptions the control registers allow software to communicate with the usb controller. these control registers can be broadly divided into four register sets: standard geodelink (gld) device msrs usb specific msrs usb embedded pci configuration registers host controller native registers the msrs (both standard and specific) are accessed via the rdmsr and wrmsr processor instructions. the msr address is derived from the perspective of the cpu core. see section 4.2 "msr addressing" on page 59 for more details. the usb transceiver control msr (msr_usbxcvr) is dedicated to the usb transceivers and allows software to control transceiver voltage and cur- rent settings. it also provides a mechanism by which the software can turn on or turn off the transmitter side of the transceiver for power management purposes. the embedded pci configuration registers are 32-bit reg- isters decoded from the embedded pci address bits 7 through 2 and c/be[3:0]#, when idsel is high, ad[10:8] select the appropriate function, and ad[1:0] are 00. this embedded pci bus is accessed via special geodelink adapter msr accesses. bytes within a 32-bit address are selected with the valid byte enables. all registers can be accessed via 8, 16, or 32-bit cycles (i.e., each byte is indi- vidually selected by the byte enables.) registers marked as reserved, and reserved bits within a register are not implemented and should return 0s when read. writes have no effect for reserved registers. the host controller (hc) c ontains a set of on-chip opera- tional registers that are mapped into a non-cacheable por- tion of the system addressable space. these registers are used by the host controller driver (hcd). according to the function of these registers, they are divided into four parti- tions, specifically for control and status, memory pointer, frame counter and root hub. all of the registers should be read and written as dwords. to ensure interoperabil- ity, the host controller driver that does not use a reserved field should not assume that the reserved field contains 0. furthermore, the host controller driver should always pre- serve the value(s) of the re served field. when a r/w regis- ter is modified, the host controller driver should first read the register, modify the bits desired, then write the register with the reserved bits still containing the read value. alter- natively, the host controller driver can maintain an in- memory copy of previously written values that can be mod- ified and then written to the host controller register. when a write to set/clear register is written, bits written to reserved fields should be 0. these registers can be grouped into four functional groups: host controller control and status registers, memory pointers, frame counter and control registers, and root hub status and control. host controller control and status registers define the operating mode of the host controller. they reflect current status of the host controller, provide interrupt control and status, and reflect error status conditions. memory pointers provide pointers to the data structure that are required to communica te with the host controller driver and perform transactions based on the transfer descriptors that reside in memory. frame counter and control provide frame timing status and control. this set of registers also govern start of the frame (sof) timing and control events that are tied to frame timing intervals. root hub status and control registers are dedicated to the root hub function. two sets of registers are included to control the two ports. tables 6-13 through 6-16 are register summary tables that include reset values and page references where the regis- ter maps and bit descriptions are provided. table 6-13. standard geodelink? device msrs summary msr address type register name reset value reference usbc1: 51600000h usbc2: 51200000h ro gld capabilities msr (usbc_gld_msr_cap) 00000000_002420xxh page 279 usbc1: 51600001h usbc2: 51200001h r/w gld master configuration msr (usbc_gld_msr_config) 00000000_0000f000h page 279 usbc1: 51600002h usbc2: 51200002h r/w gld smi msr (usbc_gld_msr_smi) 00000000_00000000h page 281 usbc1: 51600003h usbc2: 51200003h r/w gld error msr (usbc_gld_msr_error) 00000000_00000000h page 282 usbc1: 51600004h usbc2: 51200004h r/w gld power management msr (usbc_gld_msr_pm) 00000000_00000000h page 284 usbc1: 51600005h usbc2: 51200005h r/w gld diagnostic msr (usbc_gld_msr_diag) 00000000_00000000h page 284 amd geode? cs5535 companion device data book 277 usb controller register descriptions 31506b table 6-14. usb specific msrs summary msr address type register name reset value reference usbc1: 51600008h usbc2: 51200008h r/w usb transceiver control (usbc_xcvr_cntrl) 00000000_00020100h page 285 table 6-15. usb embedded pci configuration registers summary index type width (bits) register name reset value reference 00h ro 16 vendor identification (usbc_pci_ venid) 0e11h page 286 02h ro 16 device identification (usbc_pci_devid) a0f8h page 286 04h r/w 16 command (usbc_pci_cmd) 0000h page 287 06h r/w 16 status (usbc_pci_sts) 0280h page 288 08h ro 8 device revision identification (usbc_pci_devrevid) 06h page 289 09h ro 24 pci class code (usbc_pci_class) 0c0310h page 289 0ch r/w 8 cache line size (usbc_pci_cache) 00h page 289 0dh r/w 8 latency timer (usbc_pci_ltncy_tmr) 00h page 290 0eh r/w 8 header type (usbc_pci_header) 00h page 290 0fh ro 8 bist (usbc_pci_bist) 00h page 290 10h r/w 32 base address register (usbc_pci_bar) 00000000h page 291 3ch r/w 8 interrupt line (u sbc_pci_int_line) 00h page 291 3dh r/w 8 interrupt pin (usbc_pci_int_pin) 01h page 292 3eh r/w 8 minimum grant (usbc_pci_min_gnt) 00h page 292 3fh r/w 8 maximum latency (usbc_pci_max_ltncy) 50h page 292 40h r/w 32 asic test mode enable (u sbc_pci_asic_test) 000f0000h page 293 44h r/w 16 asic operational mode enable (usbc_pci_asic_mode) 0000h page 293 table 6-16. usb host controller native registers summary usb memory offset width (bits) type register name reset value reference hcd hc 00h 32 ro ro host controller revision (usbc_hcrevision) 00000110h page 294 04h 32 r/w r/w host controller control (usbc_hccontrol) 00000000h page 294 08h 32 r/w r/w host contro ller command status (usbc_hccommandstatus) 00000000h page 296 0ch 32 r/w r/w host controller interrupt status (usbc_hcinterruptstatus) 00000000h page 297 10h 32 r/w ro host controller interrupt enable (usbc_hcinterruptenable) 00000000h page 298 278 amd geode? cs5535 companion device data book usb controller register descriptions 31506b 14h 32 r/w ro host controller interrupt disable (usbc_hcinterruptdisable) 00000000h page 299 18h 32 r/w ro host controller hcca (usbc_hchcca) 00000000h page 300 1ch 32 ro r/w host controller current period list ed (usbc_hcperiodcurrented) 00000000h page 300 20h 32 r/w ro host controller control list head ed (usbc_hccontrolheaded) 00000000h page 300 24h 32 r/w r/w host controller current control list ed (usbc_hccontro lcurrented) 00000000h page 301 28h 32 r/w ro host controller bulk list head ed (usbc_hcbulkheaded) 00000000h page 301 2ch 32 r/w r/w host controller current bulk list ed (usbc_hcbulkcurrented) 00000000h page 301 30h 32 ro r/w host controller current done list head ed (usbc_hcdonehead) 00000000h page 302 34h 32 r/w ro host controller frame interval (usbc_hcfminterval) 00002edfh page 302 38h 32 ro r/w host controller frame remaining (usbc_hcframeremaining) 00000000h page 303 3ch 32 ro r/w host controller frame number (usbc_hcfmnumber) 00000000h page 303 40h 32 r/w ro host controller periodic start (usbc_hcperiodicstart) 00000000h page 304 44h 32 r/w ro host controller low speed threshold (usbc_hclsthreshold) 00000628h page 304 48h 32 r/w ro host controller root hub descriptor a (usbc_hcrhdescriptora) 01000002h page 305 4ch 32 r/w ro host controller root hub descriptor b (usbc_hcrhdescriptorb) 00000000h page 306 50h 32 r/w r/w host contro ller root hub status (usbc_hcrhstatus) 00000000h page 307 54h 32 r/w r/w host controller root hub port status 1 (usbc_hcrhportstatus[1]) 00000000h page 308 58h 32 r/w r/w host controller root hub port status 2 (usbc_hcrhportstatus[2]) 00000000h page 310 table 6-16. usb host controller native registers summary (continued) usb memory offset width (bits) type register name reset value reference hcd hc amd geode? cs5535 companion device data book 279 usb controller register descriptions 31506b 6.5.1 standard geodelink device (gld) msrs 6.5.1.1 gld capabilities msr (usbc_gld_msr_cap) 6.5.1.2 gld master configurat ion msr (usbc_gld_msr_config) msr address usbc1: 51600000h usbc2: 51200000h ty p e r o reset value 00000000_002420xxh usbc_gld_msr_cap register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd dev_id rev_id usbc_gld_msr_cap bit descriptions bit name description 63:24 rsvd reserved. reads as 0. 23:8 dev_id device id. identifies module (2420h). 7:0 rev_id revision id. identifies module revision. see amd geode? cs5535 companion device specification update document for value. msr address usbc1: 51600001h usbc2: 51200001h ty p e r / w reset value 00000000_0000f000h usbc_gld_msr_config register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd pci_mast_stop_en pdp sel fix_prefetch rsvd usb_lopwr_en usb_glitchfix_en rsvd 280 amd geode? cs5535 companion device data book usb controller register descriptions 31506b usbc_gld_msr_config bit descriptions bit name description 63:23 rsvd reserved. writes ?don?t care? and reads return 0. 22 pci_mast_sto p_en pci master stop enable. 21:20 pdp pci master prefetch decode policy. 19 sel select. 0: use field [18:16]. 1: use field [22:20]. 18:16 fix_prefetch fixed read prefetch policy. 000: none. each read takes a complete trip to memory. 001: initial read 08 bytes. read next 8 only when requested. 010: initial read 16 bytes. read next 16 only when requested. 011: initial read 32 bytes. read next 32 only when requested. 100: initial read 32 bytes. read next 32 when 16 bytes left. 101, 110, and 111: reserved. 15:14 rsvd reserved. read as written. 13 usb_lopwr_en usb low power enable. when 0, the transceiver is prevented from entering the low power suspend state. this bit has no functional impact on the transceiver or usb con- troller. defaults to 1 (i.e., suspend allowed). 12 usb_glitchfix _en usb glitch fix enable: when 0, enable transceiver de-glitch logic. this logic sup- presses a glitch that can occur when: 1) the transceiver moves from the suspend state to any other state. and 2) a low speed device is connected. th e state is defined by hccontrol[7:6]. defaults to 1 (i.e., no glitch suppression). note that this bit represents a deviation from the standard msr_config register in section 4.8.2 "msr address 1: master configuration" on page 74. 11:0 rsvd reserved. read as written. amd geode? cs5535 companion device data book 281 usb controller register descriptions 31506b 6.5.1.3 gld smi msr (usbc_gld_msr_smi) msr address usbc1: 51600002h usbc2: 51200002h ty p e r / w reset value 00000000_00000000h usbc_gld_msr_smi register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd usb_int_asmi_flag usb_asmi_flag 313029282726252423222120191817161514131211109876543210 rsvd usb_int_asmi_en usb_asmi_en gld_msr_smi bit descriptions bit name description 63:34 rsvd reserved. returns 0 on read. 33 usb_int_asmi flag usb interrupt flag. if high, records that an asmi was generated due to an int being generated by the usb module. the int condition is cleared inside the usb module core. write 1 to clear the flag; writing 0 has no effect. (also see bit 1 description.) 32 usb_asmi_flag usb asmi flag. if high, records that an asmi was generated by the usb module. the asmi condition is cleared inside the usb module. write 1 to clear the flag; writing 0 has no effect. (also see bit 0 description.) 31:2 rsvd reserved. returns 0 on read. 1 usb_int_asmi_ en usb interrupt enable. if this bit is high, the int generated by the usb module is used to generate a geodelink asmi. 0 usb_asmi_en usb asmi enable. if this bit is high, the asmi generated by the usb module is used to generate a geodelink asmi. 282 amd geode? cs5535 companion device data book usb controller register descriptions 31506b 6.5.1.4 gld error msr (usbc_gld_msr_error) msr address usbc1: 51600003h usbc2: 51200003h ty p e r / w reset value 00000000_00000000h usbc_gld_msr_error register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd cmd_err_flag sys_err_flag parin_err_flag parout_err_flag timeout_err_flag pa_svadrs_err_flag pa_tabort_err_flag pa_mabort_err_flag excep_err_flag rsvd unexp_type_err_flag 313029282726252423222120191817161514131211109876543210 rsvd cmd_err_en sys_err_en parin_err_en parout_err_en timeout_err_en pa_svadrs_err_en pa_tabort_err_en pa_mabort_err_en excep_err_en rsvd unexp_type_err_en usbc_gld_msr_error bit descriptions bit name description 63:44 rsvd reserved. returns 0 on read. 43 cmd_err_flag command error flag. if high, records that an err was generated because a pci device asserted the embedded pci bus parity error signal. (the pci adapter slave interface generated a command error on a command received from the pci device, or when the 2 lsbs of the address received from the pci device in the address phase are non-zero.) write 1 to clear the flag; writing 0 has no effect. cmd_err_en (bit 11) must be high to generate err and set flag. 42 sys_err_flag system error flag. if high, records that an err was generated because a pci device asserted the embedded pci bus system error signal. write 1 to clear the flag; writing 0 has no effect. sys_err_en (bit 10) must be high to generate err and set flag. 41 parin_err_ flag parity error in error flag. if high, records that an err was generated because a par- ity error on a pci device master to pc i adapter target transaction occurred. write 1 to clear the flag; writing 0 has no effect. parin_ err_en (bit 9) must be high to generate err and set flag. 40 parout_err_ flag parity error out error flag. if high, records that an err was generated because a parity error on pci adapter master to pci device target transaction occurred. write 1 to clear the flag; writing 0 has no effect. pa rout_err_en (bit 8) must be high to gener- ate err and set flag. 39 timeout_err_ flag master timeout error flag. if high, records that an err was generated because the pci adapter completed a master bus cycle to the geodelink adapter when the pci device failed to perform an expected retry after a disconnect. write 1 to clear the flag; writing 0 has no effect. timeout_err_en (bit 7) must be high to generate err and set flag. amd geode? cs5535 companion device data book 283 usb controller register descriptions 31506b 38 pa_svadrs_ err_flag pci adapter slave interface address parity error flag. if high, records that an err was generated because the pci adapter slave interface generated a parity error on the address received from the pci device in the address phase. write 1 to clear the flag; writing 0 has no effect. pa_svadrs_err_en (bit 6) must be high to generate err and set flag. 37 pa_tabort_ err_flag pci adapter target abort error flag. if high, records that an err was generated because the pci adapter, as a target, aborted the pci bus cycle. the geodelink adapter and the pci adapter complete the geodelink transaction. write 1 to clear the flag; writing 0 has no effect. pa_tabort_e rr_en (bit 5) must be high to generate err and set flag. 36 pa_mabort_ err_flag pci adapter master abort error. if high, records that an err was generated because the pci device did not respond as a target. the pci adapter aborted the pci bus cycle and indicated to the geodelink adapter to abort the geodelink adapter transaction. the geodelink adapter completes the geodelink transaction and sets the excp bit in any response packet. write 1 to clear the flag; writing 0 has no effect. pa_mabort_err_en (bit 4) must be high to generate err and set flag. 35 excep_err_ flag exception bit error flag. if high, records that an err was generated because the excep bit was set in the response packet associated with a device master request. write 1 to clear the flag; writing 0 has no effect. excep_err_en (bit 3) must be high to generate err and set flag. 34:33 rsvd reserved. writes don?t care. reads return 0. 32 unexp_type_ err_flag unexpected type error flag. if high, records that an err was generated because an unexpected type or other ?bad? geodelink tran saction. this error is fatal and there is no system recovery. the device (geodelink adapter) will hang. write 1 to clear the flag; writing 0 has no effe ct. unexp_type_err_en (bit 0) must be high to generate err and set flag. 31:12 rsvd reserved . writes don?t care. reads return 0. 11 cmd_err_en command error enable. write 1 to enable cmd_err_flag (bit 43) and to allow the event to generate an err. 10 sys_err_en system error enable. write 1 to enable sys_err_flag (bit 42 ) and to allow the event to generate an err. 9 parin_err_en parity error in enable. write 1 to enable parin_err_flag (bit 41) and to allow the event to generate an err. 8 parout_err_ en parity error out enable. write 1 to enable parout_err_flag (bit 40) and to allow the event to generate an err. 7 timeout_err_ en timeout error enable. write 1 to enable timeout_err_flag (bit 39) and to allow the event to generate an err. 6 pa_svadrs_ err_en pci adapter slave interface address parity error enable. write 1 to enable pa_svadrs_err_flag (bit 38) and to allow the event to generate an err. 5 pa_tabort_ err_en pci adapter target abort error enable. write 1 to enable pa_tabort_err_flag (bit 37) and to allow the event to generate an err. 4 pa_mabort_er r_en pci adapter master abort error enable. write 1 to enable pa_mabort_err_flag (bit 36) and to allow the event to generate an err. 3 excep_err_en exception bit error enable. write 1 to enable excep_err_flag (bit 35) and to allow the event to generate an err. 2:1 rsvd reserved. writes don?t care. reads return zero. 0 unexp_type_ err_en unexpected type error enable. write 1 to enable un exp_type_err_flag (bit 32) and to allow the event to generate an err. usbc_gld_msr_error bit de scriptions (continued) bit name description 284 amd geode? cs5535 companion device data book usb controller register descriptions 31506b 6.5.1.5 gld power manageme nt msr (usbc_gld_msr_pm) 6.5.1.6 gld diagnostic msr (usbc_gld_msr_diag) this register is reserved for internal use by amd and should not be written to. msr address usbc1: 51600004h usbc2: 51200004h ty p e r / w reset value 00000000_00000000h usbc_gld_msr_pm register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd pmode2 pmode1 pmode0 usbc_gld_msr_pm bit descriptions bit name description 63:6 rsvd reserved. returns 0 on read. 5:4 pmode2 power mode 2. controls clock behavior for the usb core. 00: disable clock gating. clocks are always on. 01: enable active hardware clock gating. clock goes off whenever this module?s cir- cuits are not busy. 10: reserved. 11: reserved. 3:2 pmode1 power mode 1. controls clock behavior for the usb pci adapter 00: disable clock gating. clocks are always on. 01: enable active hardware clock gating. clock goes off whenever this module?s cir- cuits are not busy. 10: reserved. 11: reserved. 1:0 pmode0 power mode 0. controls clock behavior for the usb geodelink adapter 00: disable clock gating. clocks are always on. 01: enable active hardware clock gating. clock goes off whenever this module?s cir- cuits are not busy. 10: reserved. 11: reserved. msr address usbc1: 51600005h usbc2: 51200005h ty p e r / w reset value 00000000_00000000h amd geode? cs5535 companion device data book 285 usb controller register descriptions 31506b 6.5.2 usb specific msrs 6.5.2.1 usb transceiver control (usbc_xcvr_cntrl) msr address usbc1: 51600008h usbc2: 51200008h ty p e r / w reset value 00000000_00020100h usbc_xcvr_cntrl register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd xceiv2_pm rcvr2_vadj xmit2_cadj xceiv1_pm rcvr1_vadj xmit1_cadj usbc_xcvr bit description bit name description 63:18 rsvd reserved. read as 0. 17 xceiv2_pm transceiver 2 power management bit. disables transceiver #2 and puts the trans- ceiver in a low power state. 0: enable transceiver. 1: disable transceiver. 16:14 rcvr2_vadj single ended receiver #2 threshold voltage adjustment . for proper operation this must be set to 100 (4h). see electrical s pecifications section 7.3.6 "usb signals" on page 560. 13:9 xmit2_cadj differential transmitter #2 sl ew rate current adjustment . for proper operation this must be set to 010 (2h). see electrical s pecifications section 7.3.6 "usb signals" on page 560. 8xceiv1_pm transceiver 1 power management bit. disables transceiver #1 and puts the trans- ceiver in a low power state. 0: enable transceiver. 1: disable transceiver. 7:5 rcvr1_vadj single ended receiver #1 threshold voltage adjustment . for proper operation this must be set to 100 (4h). see electrical s pecifications section 7.3.6 "usb signals" on page 560. 4:0 xmit1_cadj differential transmitter #1 sl ew rate current adjustment. for proper operation this must be set to 010 (2h). see electrical s pecifications section 7.3.6 "usb signals" on page 560. 286 amd geode? cs5535 companion device data book usb controller register descriptions 31506b 6.5.3 usb embedded pci configuration registers 6.5.3.1 vendor identifica tion (usbc_pci_ venid) 6.5.3.2 device identification (usbc_pci_devid) index 00h ty p e r o reset value 0e11h usbc_pci_venid register map 1514131211109876543210 vendor_id usbc_pci_venid bit descriptions bit name description 15:0 vendor_id vendor id. index 02h ty p e r o reset value a0f8h usbc_devid register map 1514131211109876543210 device_id usbc_devid bit descriptions bit name description 15:0 device_id device id. amd geode? cs5535 companion device data book 287 usb controller register descriptions 31506b 6.5.3.3 command (usbc_pci_cmd) index 04h ty p e r / w reset value 0000h usbc_pci_cmd register map 1514131211109876543210 rsvd fb2b_en serr ws_ctl pa r vga_snp_en memw_inv spc_cyc mstr_en mem io usbc_pci_cmd bit descriptions bit name description 15:10 rsvd reserved. set to 0. 9 fb2b_en (ro) fast back-to-back enable (read only). usb only acts as a master to a single device, so this functionality is not needed. it is always disabled (must always be set to 0). 8 serr system error. usb asserts serr# when it de tects an address parity error. 0: disable; 1: enable. 7ws_ctl wait cycle control. usb does not need to insert a wait state between the address and data on the ad lines. it is always disabled (bit is set to 0). 6par parity error. usb asserts perr# when it is the age nt receiving data and it detects a data parity error. 0: disable; 1: enable. 5vga_snp_en (ro) vga palette snoop enable (read only). usb does not support this function. it is always disabled (bit is set to 0). 4memw_inv memory write and invalidate: allow usb to run memory write and invalidate com- mands. 0: disable; 1: enable. the memory write and invalidate commands only occur if the cache line size is set to 32 bytes and the memory write is exactly one cache line. this bit is ignored by the geodelink adapter and hence the setting is a ?don?t care?. 3 spc_cyc special cycles. usb does not run special cycles on pci. it is always disabled (bit is set to 0). 2 mstr_en pci master enable. allow usb to run pci master cycles. 0: disable; 1: enable. 1mem memory space. allow usb to respond as a target to memory cycles. 0: disable; 1: enable. 0io i/o space. allow usb to respond as a target to i/o cycles. 0: disable; 1: enable. 288 amd geode? cs5535 companion device data book usb controller register descriptions 31506b 6.5.3.4 status (usbc_pci_sts) index 06h ty p e r / w reset value 0280h usbc_pci_sts register map 1514131211109876543210 pa r _ e r r serr_sts rcvd_mstr_abt_sts rcvd_trgt_abt_sts sig_trgt_abt_sts devsel_time data_par fb2b rsvd usbc_pci_sts bit descriptions bit name description 15 par_err detected parity error. this bit is set whenever the usb detects a parity error, even if the parity error (response) detection enable bit (index 04h[6]) is disabled. write 1 to clear. 14 serr_err serr# status. this bit is set whenever the usb detects a pci address error. write 1 to clear. 13 rcvd_mstr_ abt_sts received master abort status. this bit is set when the usb, acting as a pci master, aborts a pci bus memory cycle. write 1 to clear. 12 rcvd_trgt_ abt_sts received target abort status. this bit is set when a usb generated pci cycle (usb is the pci master) is aborted by a pci target. write 1 to clear. 11 sig_trgt_ abt_sts signaled target abort status. this bit is set whenever the usb signals a target abort. write 1 to clear. 10:9 devsel_time devsel# timing (read only). these bits indicate the devsel# timing when per- forming a positive decode. since devsel# is asserted to meet the medium timing, these bits are encoded as 01. 8 data _ pa r data parity reported. set to 1 if the parity error bit (command register bit 6) is set, and usb detects perr# asserted while ac ting as pci master (whether perr# was driven by usb or not). 7fb2b fast back-to-back capable (read only). usb does support fast back-to-back trans- actions when the transactions are not to the same agent. this bit is always 1. 6:0 rsvd reserved. set to 0. amd geode? cs5535 companion device data book 289 usb controller register descriptions 31506b 6.5.3.5 device revision identi fication (usbc_pci_devrevid) 6.5.3.6 pci class code (usbc_pci_class) 6.5.3.7 cache line size (usbc_pci_cache) index 08h ty p e r o reset value 06h usbc_pci_devrevid register map 76543210 dev_rev_id usbc_pci_devrevid bit descriptions bit name description 7:0 dev_rev_id device revision id. index 09h ty p e r o reset value 0c0310h usbc_pci_class register map 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pci_class usbc_pci_class bit descriptions bit name description 23:0 pci_class pci class. this register identifies this function as an openhci device. the base class is 0ch (serial bus controller). the sub class is 03h (universal serial bus). the program- ming interface is 10h (openhci). index 0ch ty p e r / w reset value 00h usbc_pci_cache register map 76543210 pci_cache usbc_pci_cache bit descriptions bit name description 7:0 pci_cache pci cache. the usb controller stores the system cache line size, in units of 32-bit words in bit 3 of this register. a cache line size of 32 bytes is the only one applicable to this design. users must set this register to 08h for proper operation. any value other than 08h written to this regi ster is read back as 00h. 290 amd geode? cs5535 companion device data book usb controller register descriptions 31506b 6.5.3.8 latency timer (usbc_pci_ltncy_tmr) 6.5.3.9 header type (usbc_pci_header) 6.5.3.10 bist (usbc_pci_bist) index 0dh ty p e r / w reset value 00h usbc_pci_ltncy_tmr register map 76543210 lt n c y _ t m r usbc_pci_ltncy_tmr bit descriptions bit name description 7:0 ltncy_tmr latency timer. this register identifies the value of the latency timer in pci clocks for pci bus master cycles. index 0eh ty p e r o reset value 00h usbc_pci_header register map 76543210 pci_header usbc_pci_header bit descriptions bit name description 7:0 pci_header pci header type. this register identifies the type of the predefined header in the con- figuration space. since the usb is a single function device and not a pci-to-pci bridge, this byte should be read as 00h. index 0fh ty p e r o reset value 00h usbc_pci_bist register map 76543210 pci_bist usbc_pci_bist bit descriptions bit name description 7:0 pci_bist pci bist. this register identifies the control and status of built in self test. the usb does not implement bist, so this register is read only. amd geode? cs5535 companion device data book 291 usb controller register descriptions 31506b 6.5.3.11 base address register (usbc_pci_bar) this bar sets the base address of the memory mapped usb co ntroller registers. bits [ 11:0] are read only (0000 0000 0000), indicating a 4 kb memory address range. refer to section 6.5.4 "host controller native registers" on page 294 for the usb controller register bit formats and reset values. 6.5.3.12 interrupt line (usbc_pci_int_line) index 10h ty p e r / w reset value 00000000h usbc_pci_bar register map 313029282726252423222120191817161514131211109876543210 base_addr addr_rng prefetch width mem usbc_pci_bar bit descriptions bit name description 31:12 base_addr base address. post writes the value of the memory base address to this register. 11:4 addr_rng address range (always 0.) indicates a 4k byte address range is requested. 3prefetch prefetch (always 0). indicates there is no support for prefetchable memory. 2:1 width width (always 0). indicates that the base register is 32-bits wide and can be placed anywhere in 32-bit memory space. 0mem memory (always 0). indicates that the operational registers are mapped into memory space. index 3ch ty p e r / w reset value 00h usbc_pci_int_line register map 76543210 int_line usbc_pci_int_line bit descriptions bit name description 7:0 int_line interrupt line. this register identifies which of the system interrupt controllers the devices interrupt pin is connected to. the value of this register is used by device drivers and has no direct meaning to the usb. 292 amd geode? cs5535 companion device data book usb controller register descriptions 31506b 6.5.3.13 interrupt pin (usbc_pci_int_pin) 6.5.3.14 minimum grant (usbc_pci_min_gnt) 6.5.3.15 maximum latency (usbc_pci_max_ltncy) index 3dh ty p e r / w reset value 01h usbc_pci_int_pin register map 76543210 int_pin usbc_pci_int_pin bit descriptions bit name description 7:0 int_pin interrupt pin. this register identifies which interrupt pin a device uses. since the usb uses inta#, this value is set to 01h. index 3eh ty p e r / w reset value 00h usbc_pci_min_gnt register map 76543210 min_gnt usbc_pci_min_gnt bit descriptions bit name description 7:0 min_gnt minimum grant. this register specifies the desired settings for how long a burst the usb needs assuming a clock rate of 33 mhz. the value specifies a period of time in units of 1/4 microsecond. index 3fh ty p e r / w reset value 50h usbc_pci_max_ltncy register map 76543210 max_ltncy usbc_pci_max_ltncy bit descriptions bit name description 7:0 max_ltncy maximum latency. this register specifies the desired settings for how often the usb needs access to the pci bus assuming a clock rate of 33 mhz. the value specifies a period of time in units of 1/4 microsecond. amd geode? cs5535 companion device data book 293 usb controller register descriptions 31506b 6.5.3.16 asic test mode enable (usbc_pci_asic_test) 6.5.3.17 asic operational mode enable (usbc_pci_asic_mode) index 40h ty p e r / w reset value 000f0000h usbc_pci_asic_test register map 313029282726252423222120191817161514131211109876543210 rsvd usbc_pci_asic_test bit descriptions bit name description 31:0 rsvd reserved. these bits are reserved for internal testing only. these bits should not be written to. index 44h ty p e r / w reset value 0000h usbc_pci_asic_mode register map 1514131211109876543210 rsvd sie_pipe_dis rsvd buff_size usbc_pci_asic_mode bit descriptions bit reset description 15:9 rsvd reserved. write 0s; reads undefined. 8 sie_pipe_dis sie pipeline disable. when set, waits for all usb bus activity to complete prior to returning completion status to the list proc essor. should normally be cleared to 0. this is a fail-safe mechanism to avoid potential problems with the clk_dr transition between 1.5 mhz and 12 mhz. 7:1 rsvd reserved. write 0s; reads undefined. 0buff_size data buffer size. when set, the size of the region for the data buffer is 16 bytes. when clear, the size is 32 bytes. 294 amd geode? cs5535 companion device data book usb controller register descriptions 31506b 6.5.4 host controller native registers 6.5.4.1 host controller re vision (usbc_hcrevision) 6.5.4.2 host controller control (usbc_hccontrol) usb memory offset 00h type hcd: hc: ro ro reset value 00000110h usbc_hcrevision register map 313029282726252423222120191817161514131211109876543210 rsvd rev usbc_hcrevision bit descriptions bit name hcd hc description 31:8 rsvd ro ro reserved. read/write 0s. 7:0 rev ro ro revision (read only). indicates the open hci specification revision number implemented by the hardware. usb supports 1.0a specification. (x.y = xyh). usb memory offset 04h type hcd: hc: r/w r/w reset value 00000000h usbc_hccontrol register map 313029282726252423222120191817161514131211109876543210 rsvd remotewakeupconnectedenable remotewakeupconnected interruptrouting hostcontrollerfunctionalstate bulklistenable controllistenable isochronousenable periodiclistenable controlbulkserviceratio amd geode? cs5535 companion device data book 295 usb controller register descriptions 31506b usbc_hccontrol bit descriptions bit name hcd hc description 31:11 rsvd r/w r/w reserved. read/write 0s. 10 remotewakeup connected enable r/w ro remote wakeup connected enable. this bit is used by the hcd to enable or disable the remote wakeup feature upon the detection of upstream resume signaling. when this bit is set and the resumedetected bit in hcinte rruptstatus is set, a remote wakeup is signaled to the host system. setting this bit has no impact on the generation of hardware interrupt. in the host controller, this bit is cleared to 0 on hardware reset and is write-read. otherwise, it does nothing. it can be used as a flag by software as indicated ab ove. setting this bit will not enable or disable remote wakeup. that is covered in the power management controller. 9 remotewakeup connected r/w r/w remote wakeup connected. this bit indicates whether the hc supports remote wakeup signaling. if remote wakeup is sup- ported and used by t he system it is the responsibility of system firmware to set this bit during post. the hc clears the bit upon a hardware reset but does not alter it upon a software reset. remote wakeup signaling of the host system is host-bus-specific and is not described in this specification. in the host controller, it is cleared to 0 on hardware reset and is write-read. otherwise, it does nothing. it can be used as a flag by software as indicated above. 8 interruptrouting r/w ro interrupt routing. this bit is used for interrupt routing. 0: interrupts routed to normal interrupt mechanism (int). 1: interrupts routed to smi. 7:6 hostcontroller functionalstate r/w r/w host controller functional state. this field sets the hc state. the hc may force a state change from usbsuspend to usbre- sume after detecting resume signaling from a downstream port. states are: 00: usbreset. 01: usbresume. 10: usboperational. 11: usbsuspend. 5 bulklistenable r/w ro bulk list enable. when set, this bit enables processing of the bulk list. 4 controllist enable r/w ro control list enable. when set, this bit enables processing of the control list. 3 isochronous enable r/w ro isochronous enable. when clear, this bit disables the isochro- nous list when the periodic list is enabled (so interrupt eds may be serviced). while processing the periodic list, the hc will check this bit when it finds an isochronous ed. 2 periodiclist enable r/w ro periodic list enable. when set, this bit enables processing of the periodic (interrupt and isochronous) list. the hc checks this bit prior to attempting any periodic transfers in a frame. 1:0 controlbulk serviceratio r/w ro control bulk service ratio. specifies the number of control endpoints serviced for every bulk endpoint. encoding is n-1 where n is the number of control endpoints (i.e., 00 = 1 control endpoint; 11 = 3 control endpoints). 296 amd geode? cs5535 companion device data book usb controller register descriptions 31506b 6.5.4.3 host controller command status (usbc_hccommandstatus) usb memory offset 08h type hcd: hc: r/w r/w reset value 00000000h usbc_hccommandstatus register map 313029282726252423222120191817161514131211109876543210 rsvd scheduleoverruncount rsvd ownershipchangerequest bulklistfilled controllistfilled hostcontrollerreset usbc_hccommandstatus bit descriptions bit name hcd hc description 31:18 rsvd r/w r/w reserved. read/write 0s. 17:16 schedule overruncount ro r/w schedule overrun count. this field increments every time the schedulingoverrun bit in hcinterruptstatus is set. the count wraps from 11 to 00. 15:4 rsvd r/w r/w reserved. read/write 0s. 3 ownership changerequest r/w r/w ownership change request. when set by software, this bit sets the ownershipchange field in hcinterruptstatus. the bit is cleared by software. this field always reads back as 0. 2 bulklistfilled r/w r/w bulk list filled. set to indicate there is an active ed on the bulk list. the bit may be set by either software or the hc and cleared by the hc each time it begins processing the head of the bulk list. 1 controllistfilled r/w r/w control list filled. set to indicate there is an active ed on the control list. it may be set by either software or the hc and cleared by the hc each time it begins processing the head of the control list. 0 hostcontrollerre- set r/w r/w host controller reset. this bit is set to initiate a software reset. this bit is cleared by the hc upon completion of the reset opera- tion. this field always reads back as 0. amd geode? cs5535 companion device data book 297 usb controller register descriptions 31506b 6.5.4.4 host controller interrupt status (usbc_hcinterruptstatus) all bits are set by the hardware and cleared by software. usb memory offset 0ch type hcd: hc: r/w r/w reset value 00000000h usbc_hcinterruptstat us register map 313029282726252423222120191817161514131211109876543210 rsvd ownershipchange rsvd roothubstatuschange framenumberoverflow unrecoverableerror resumedetected startofframe writebackdonehead schedulingoverrun usbc_hcinterruptstatus bit descriptions bit name hcd hc description 31 rsvd r/w r/w reserved. read/write 0s. 30 ownership change r/w r/w ownership change. this bit is set when the ownershipchang- erequest bit of hccommandstatus is set. 29:7 rsvd r/w r/w reserved. read/write 0s. 6 roothubstatus change r/w r/w root hub status change. this bit is set w hen the content of hcrhstatus or the content of an y hcrhportstatus register has changed. 5 framenumber overflow r/w r/w frame number overflow. set when bit 15 of framenumber changes value. 4 unrecoverable error r/w r/w unrecoverable error (read only). this event is not imple- mented and is hard-coded to 0. hcd clears this bit. 3 resume detected r/w r/w resume detected. set when hc detects resume signaling on a downstream port. 2 startofframe r/w r/w start of frame. set when the frame management block signals a start of frame event. 1 writebackdone head r/w r/w writeback done head. set after the hc has written hcdone- head. 0 scheduling overrun r/w r/w scheduling overrun. set when the list processor determines a schedule overrun has occurred. 298 amd geode? cs5535 companion device data book usb controller register descriptions 31506b 6.5.4.5 host controller interrupt enable (usbc_hcinterruptenable) writing a 1 to a bit in this register sets the corresponding bit, while writing a 0 leaves the bit unchanged. usb memory offset 10h type hcd: hc: r/w ro reset value 00000000h usbc_hcinterruptenab le register map 313029282726252423222120191817161514131211109876543210 masterinterruptenable ownershipchangeenable rsvd roothubstatuschangeenable framenumberoverflowenable unrecoverableerrorenable resumedetectedenable startofframeenable writebackdoneheadenable schedulingoverrunenable usbc_hcinterruptenable bit descriptions bit name hcd hc description 31 masterinterrupt enable r/w ro master interrupt enable. this bit is a global interrupt enable. a write of 1 allows interrupts to be enabled via the specific enable bits listed above. 30 ownership changeenable r/w ro ownership change enable. 0: ignore. 1: enable interrupt generation due to ownership change. 29:7 rsvd r/w ro reserved. read/write 0s. 6 roothubstatus changeenable r/w ro roothub status change enable. 0: ignore. 1: enable interrupt generation due to root hub status change. 5 framenumber overflowenable r/w ro frame number overflow enable. 0: ignore. 1: enable interrupt generation due to frame number overflow. 4 unrecoverable errorenable r/w ro unrecoverable error enable. this event is not implemented. all writes to this bit are ignored. 3 resume detectedenable r/w ro resume detected enable. 0: ignore. 1: enable interrupt generation due to resume detected. 2startofframe enable r/w ro start of frame enable. 0: ignore. 1: enable interrupt generation due to start of frame. 1 writebackdone headenable r/w ro writeback done head enable. 0: ignore. 1: enable interrupt generation due to writeback done head. 0 scheduling overrunenable r/w ro scheduling overrun enable. 0: ignore. 1: enable interrupt generation due to scheduling overrun. amd geode? cs5535 companion device data book 299 usb controller register descriptions 31506b 6.5.4.6 host controller interrupt disable (usbc_hcinterruptdisable) writing a 1 to a bit in this register clears the corresponding bit, while writing a 0 leaves the bit unchanged. usb memory offset 14h type hcd: hc: r/w ro reset value 00000000h usbc_hcinterruptdisa ble register map 313029282726252423222120191817161514131211109876543210 masterinterruptenable ownershipchangeenable rsvd roothubstatuschangeenable framenumberoverflowenable unrecoverableerrorenable resumedetectedenable startofframeenable writebackdoneheadenable schedulingoverrunenable usbc_hcinterruptdisable bit descriptions bit name hcd hc description 31 masterinterrupt enable r/w ro master interrupt disable. global interrupt disable. a write of 1 disables all interrupts. 30 ownership changeenable r/w ro ownership change disable. 0: ignore. 1: disable interrupt generation due to ownership change. 29:7 rsvd r/w ro reserved. read/write 0s. 6 roothubstatus changeenable r/w ro root hub status change disable. 0: ignore. 1: disable interrupt generation due to root hub status change. 5 framenumber overflowenable r/w ro frame number overflow disable. 0: ignore. 1: disable interrupt generation due to frame number overflow. 4 unrecoverable errorenable r/w ro unrecoverable error disable. this event is not implemented. all writes to this bit will be ignored. 3 resume detectedenable r/w ro resume detected disable. 0: ignore. 1: disable interrupt generation due to resume detected. 2startofframe enable r/w ro start of frame disable. 0: ignore. 1: disable interrupt generation due to start of frame. 1 writebackdone headenable r/w ro writeback done head disable. 0: ignore. 1: disable interrupt generation due to writeback done head. 0 scheduling overrunenable r/w ro scheduling overrun disable. 0: ignore. 1: disable interrupt generation due to scheduling overrun. 300 amd geode? cs5535 companion device data book usb controller register descriptions 31506b 6.5.4.7 host controller hcca (usbc_hchcca) 6.5.4.8 host controller current period list ed (usbc_hcperiodcurrented) 6.5.4.9 host controller control list head ed (usbc_hccontrolheaded) usb memory offset 18h type hcd: hc: r/w ro reset value 00000000h usbc_hchcca register map 313029282726252423222120191817161514131211109876543210 hcca rsvd usbc_hchcca bit descriptions bit name hcd hc description 31:8 hcca r/w ro hcca. pointer to hcca base address. 7:0 rsvd r/w ro reserved. read/write 0s. usb memory offset 1ch type hcd: hc: ro r/w reset value 00000000h usbc_hcperiodcurrented register map 313029282726252423222120191817161514131211109876543210 periodcurrented rsvd usbc_hcperiodcurrented bit descriptions bit name hcd hc description 31:4 periodcurrented ro r/w period current ed. pointer to the current periodic list ed. 3:0 rsvd ro r/w reserved. read/write 0s. usb memory offset 20h type hcd: hc: r/w ro reset value 00000000h usbc_hccontrolheaded register map 313029282726252423222120191817161514131211109876543210 controlheaded rsvd usbc_hccontrolheaded bit descriptions bit name hcd hc description 31:4 controlheaded r/w ro control head ed. pointer to the control list head ed. 3:0 rsvd r/w ro reserved. read/write 0s. amd geode? cs5535 companion device data book 301 usb controller register descriptions 31506b 6.5.4.10 host controller current contro l list ed (usbc_hccontrolcurrented) 6.5.4.11 host controller bulk li st head ed (usbc_hcbulkheaded) 6.5.4.12 host controller current bulk list ed (usbc_hcbulkcurrented) usb memory offset 24h type hcd: hc: r/w r/w reset value 00000000h usbc_hccontrolheaded register map 313029282726252423222120191817161514131211109876543210 controlcurrented rsvd usbc_hccontrolheaded bit descriptions bit name hcd hc description 31:4 controlcurrented r/w r/w control current ed. pointer to the current control list ed. 3:0 rsvd r/w r/w reserved. read/write 0s. usb memory offset 28h type hcd: hc: r/w ro reset value 00000000h usbc_hcbulkheaded register map 313029282726252423222120191817161514131211109876543210 bulkheaded rsvd usbc_hcbulkheaded bit descriptions bit name hcd hc description 31:4 bulkheaded r/w ro bulk head ed. pointer to the bulk list head ed. 3:0 rsvd r/w ro reserved. read/write 0s. usb memory offset 2ch type hcd: hc: r/w r/w reset value 00000000h usbc_hcbulkcurrente d register map 313029282726252423222120191817161514131211109876543210 bulkcurrented rsvd usbc_hcbulkcurrented bit descriptions bit name hcd hc description 31:4 bulkcurrented r/w r/w bulk current ed. pointer to the current bulk list ed. 3:0 rsvd r/w r/w reserved. read/write 0s. 302 amd geode? cs5535 companion device data book usb controller register descriptions 31506b 6.5.4.13 host controller current done list head ed (usbc_hcdonehead) 6.5.4.14 host controller frame interval (usbc_hcfminterval) usb memory offset 30h type hcd: hc: ro r/w reset value 00000000h usbc_hcdonehead register map 313029282726252423222120191817161514131211109876543210 donehead rsvd usbc_hcdonehead bit descriptions bit name hcd hc description 31:4 donehead ro r/w done head. pointer to the current done list head ed. 3:0 rsvd ro r/w reserved. read/write 0s. usb memory offset 34h type hcd: hc: r/w ro reset value 00002edfh usbc_hcfminterval register map 313029282726252423222120191817161514131211109876543210 frameintervaltoggle fslargestdatapacket rsvd frameinterval usb_hcfminterval bit descriptions bit name hcd hc description 31 frameinterval toggle r/w ro frame interval toggle this bit is toggled by hcd when it loads a new value into frameinterval. 30:16 fslargest datapacket r/w ro fs largest data packet. this field specifies a value that is loaded into the largest data packet counter at the beginning of each frame. 15:14 rsvd r/w ro reserved. read/write 0s. 13:0 frameinterval r/w ro frame interval. this field specifies the le ngth of a frame as (bit times - 1). for 12,000 bit times in a frame, a value of 11,999 is stored here. amd geode? cs5535 companion device data book 303 usb controller register descriptions 31506b 6.5.4.15 host controller frame re maining (usbc_hcframeremaining) 6.5.4.16 host controller fram e number (usbc_hcfmnumber) usb memory offset 38h type hcd: hc: ro r/w reset value 00000000h usbc_hcframeremaini ng register map 313029282726252423222120191817161514131211109876543210 frameremainingtoggle rsvd frameremaining usbc_hcframeremaini ng bit descriptions bit name hcd hc description 31 frameremaining toggle ro r/w frame remaining toggle. loaded with frameintervaltoggle when frameremaining is loaded. 30:14 rsvd ro r/w reserved. read/write 0s. 13:0 frameremaining ro r/w frame remaining. when the hc is in the usboperational state, this 14-bit field decrements each 12 mhz clock period. when the count reaches 0, (end of frame) the counter reloads with frameinterval. in addition, the c ounter loads when the hc transi- tions into usboperational. usb memory offset 3ch type hcd: hc: ro r/w reset value 00000000h usbc_hcfmnumber register map 313029282726252423222120191817161514131211109876543210 rsvd framenumber usbc_hcfmnumber bit descriptions bit name hcd hc description 30:16 rsvd ro r/w reserved. read/write 0s. 15:0 framenumber ro r/w frame number. this 16-bit incrementin g counter field is incre- mented coincident with the lo ading of frameremaining. the count rolls over from ffffh to 0h. 304 amd geode? cs5535 companion device data book usb controller register descriptions 31506b 6.5.4.17 host controller period ic start (usbc_hcperiodicstart) 6.5.4.18 host controller low spee d threshold (usbc_hclsthreshold) usb memory offset 40h type hcd: hc: r/w ro reset value 00000000h usbc_hcperiodicstart register map 313029282726252423222120191817161514131211109876543210 rsvd periodicstart usbc_hcperiodicstart bit descriptions bit name hcd hc description 31:14 rsvd r/w ro reserved. read/write 0s. 13:0 periodicstart r/w ro periodic start. this field contains a value used by the list pro- cessor to determine where in a frame the periodic list process- ing must begin. usb memory offset 44h type hcd: hc: r/w ro reset value 00000628h usbc_hclsthreshold register map 313029282726252423222120191817161514131211109876543210 rsvd lsthreshold usbc_hclsthreshold bit descriptions bit name hcd hc description 30:12 rsvd r/w ro reserved. read/write 0s. 11:0 lsthreshold r/w ro ls threshold. this field contains a value used by the frame management block to determine whether or not a low speed transaction can be started in the current frame. amd geode? cs5535 companion device data book 305 usb controller register descriptions 31506b 6.5.4.19 host controller root hub descriptor a (usbc_hcrhdescriptora) this register is only reset by a power-on reset (pcirst#). it is writ ten during system initialization to configure the root hub . these bit should not be written during normal operation. usb memory offset 48h type hcd: hc: r/w ro reset value 01000002h usbc_hcrhdescriptor a register map 313029282726252423222120191817161514131211109876543210 powerontopowergoodtime rsvd noovercurrentprotection overcurrentprotectionmode devicetype nopowerswitching powerswitchingmode numberdownstreamports usbc_hcrhdescriptora bit descriptions bit name hcd hc description 31:24 poweronto powergoodtime r/w ro poweron to powergood time. this field value is represented as the number of 2 ms intervals, ensuring that the power switch- ing is effective within 2 ms. only bits [25:24] are implemented as r/w. the remaining bits are read only as 0. it is not expected that these bits be written to anything other than 1h, but limited adjustment is provided. this fi eld should be written to support system implementation. this fiel d should always be written to a non-zero value. 23:13 rsvd r/w ro reserved. read/write 0s. 12 noovercurrent protection r/w ro no over-current protection. this bit should be written to sup- port the external system port over-current implementation. 0: over-current status is reported. 1: over-current status is not reported. 11 overcurrent protectionmode r/w ro over current protection mode. this bit should be written 0 and is only valid when noovercurrentprotection is cleared. 0: global over-current. 1: individual over-current 10 devicetype ro ro device type (read only). usb is not a compound device, therefore this field will return 0. 9nopower switching r/w ro no power switching. this bit should be written to support the external system port power switching implementation. 0: ports are power switched. 1: ports are always powered on. 8 powerswitching mode r/w ro power switching mode. this bit is only valid when nopower- switching is cleared. this bit should be written 0. 0: global switching. 1: individual switching 7:0 numberdown- streamports ro ro number downstream ports (read only). usb supports two downstream ports, therefore this field will return 02h. 306 amd geode? cs5535 companion device data book usb controller register descriptions 31506b 6.5.4.20 host controller root hub descriptor b (usbc_hcrhdescriptorb) this register is only reset by a power-on reset (pcirst#). it is writ ten during system initialization to configure the root hub . these bit should not be written during normal operation. usb memory offset 4ch type hcd: hc: r/w ro reset value 00000000h usbc_hcrhdescriptor b register map 313029282726252423222120191817161514131211109876543210 portpowercontrolmask deviceremoveable usbc_hcrhdescriptorb bit descriptions bit name hcd hc description 31:16 portpower controlmask r/w ro port power control mask. global-power switching. this field is only valid if nopowerswitching is cleared and powerswitching- mode is set (individual port switching). when set, the port only responds to individual port power switching commands (set/clearportpower). when cleared, the port only responds to global power switching commands (set/clearglobalpower). 0: device not removable. 1: global-power mask. port bit relationship - unimplemented ports are reserved, read/write 0. 0: reserved 1: port 1 2: port 2 ... 15: port 15 15:0 device removeable r/w ro device removeable. usb ports default to removable devices. 0: device not removable. 1: device removable. port bit relationship - unimplemented ports are reserved, read/write 0. 0: reserved 1: port 1 2: port 2 ... 15: port 15 amd geode? cs5535 companion device data book 307 usb controller register descriptions 31506b 6.5.4.21 host controller root hub status (usbc_hcrhstatus) this register is reset by the usbreset state. note: read back are 0s. usb memory offset 50h type hcd: hc: r/w r/w reset value 00000000h usbc_hcrhstatus register map 313029282726252423222120191817161514131211109876543210 clearremotewakeupenable rsvd overcurrentindicatorchange dual function dual function rsvd overcurrentindicator dual function usbc_hcrhstatus bit descriptions bit name hcd hc description 31 clearremote wakeupenable wo ro clear remote wakeup enable. writing a 1 to this bit clears deviceremotewakeupenable. writing a 0 has no effect. 30:18 rsvd r/w r/w reserved. read/write 0s. 17 overcurrent indicatorchange r/w r/w over current indicator change. this bit is set when overcur- rentindicator changes. writing a 1 clears this bit. writing a 0 has no effect. 16 dual function r/w ro read: local power status change. not supported. always read 0. write: set global power. write a 1 issues a setglobalpower command to the ports. writing a 0 has no effect. 15 dual function r/w ro read: device remote wakeup enable. this bit enables ports' connectstatuschange as a remote wakeup event. 0: disabled. 1: enabled. write: set remote wakeup enable. writing a 1 sets devicere- motewakeupenable. writing a 0 has no effect. 14:2 rsvd r/w r/w reserved. read/write 0s. 1 overcurrent indicator rr/w over current indicator. this bit reflects the state of the ovr- cur pin. this field is only valid if noovercurrentprotection and overcurrentprotectionmode are cleared. 0: no over-current condition. 1: over-current condition. 0 dual function r/w ro read: local power status. not supported. always read 0. write: clear global power. writing a 1 issues a clearglo- balpower command to the ports. writing a 0 has no effect. 308 amd geode? cs5535 companion device data book usb controller register descriptions 31506b 6.5.4.22 host controller root hub po rt status 1 (usbc_hcrhportstatus[1]) this register is reset by the usbreset state. note: there must be a device connect detected by the host to be able to set other bits. usb memory offset 54h type hcd: hc: r/w r/w reset value 00000000h usbc_hcrhportstatus[1] register map 313029282726252423222120191817161514131211109876543210 rsvd portresetstatuschange portovercurrentindicatorchange portsuspendstatuschange portenablestatuschange connectstatuschange rsvd dual function dual function rsvd dual function dual function dual function dual function dual function usbc_hcrhportstatus[1 ] bit descriptions bit name hcd hc description 31:21 rsvd r/w r/w reserved. read/write 0s. 20 portreset statuschange r/w r/w port reset status change. this bit indicates that the port reset signal has completed. 0: port reset is not complete. 1: port reset is complete. 19 portovercurrent indicatorchange r/w r/w port over current indicator change. this bit is set when over- currentindicator changes. writing a 1 clears this bit. writing a 0 has no effect. 18 portsuspend statuschange r/w r/w port suspend status change. this bit indicate s the completion of the selective resume sequence for the port. 0: port is not resumed. 1: port resume is complete. 17 portenable statuschange r/w r/w port enable status change. this bit indicates that the port has been disabled due to a hardware event (cleared portenablesta- tus). 0: port has not been disabled. 1: portenablestatus has been cleared. 16 connectstatus change r/w r/w connect status change. this bit indicates a connect or discon- nect event has been detected. writin g a 1 clears this bit. writing a 0 has no effect. 0: no connect/disconnect event. 1: hardware detection of connect/disconnect event. if deviceremoveable is set, this bit resets to 1. 15:10 rsvd r/w r/w reserved. read/write 0s. amd geode? cs5535 companion device data book 309 usb controller register descriptions 31506b 9 dual function r/w r/w read: low speed device attached. this bit defines the speed of the attached device. it is only valid when currentconnectsta- tus is set. 0: full speed device. 1: low speed device. write: clear port power. writing a 1 clears portpowerstatus. writing a 0 has no effect. 8 dual function r/w r/w read: port power status. this bit reflects the power state of the port regardless of the power switching mode. 0: port power is off. 1: port power is on. note: if nopowerswitching is set, th is bit is always read as 1. write: set port power. writing a 1 sets portpowerstatus. writ- ing a 0 has no effect. 7:5 rsvd r/w r/w reserved. read/write 0s. 4 dual function r/w r/w read: port reset status. 0: port reset signal is not active. 1: port reset signal is active. write: set port reset. writing a 1 sets portresetstatus. writing a 0 has no effect. 3 dual function r/w r/w read: port over current indicator. this bit reflects the state of the ovrcur pin dedicated to this port. this field is only valid if noovercurrentprotection is cl eared and overcurrentprotection- mode is set. 0: no over-current condition. 1: over-current condition. write: clear port suspend. writing a 1 initiates the selective resume sequence for the port. writing a 0 has no effect. 2 dual function r/w r/w read: port suspend status. 0: port is not suspended. 1: port is selectively suspended. write: set port suspend. writing a 1 sets portsuspendstatus. writing a 0 has no effect. 1 dual function r/w r/w read: port enable status. 0: port disabled. 1: port enabled. write: set portenable. writing a 1 sets portenablestatus. writ- ing a 0 has no effect. 0 dual function r/w r/w read: current connect status. 0: no device connected. 1: device connected. note: if deviceremoveable is set (not removable) this bit is always 1. write: clear port enable. writing 1 a clears portenablestatus. writing a 0 has no effect. usbc_hcrhportstatus[1] bit descriptions (continued) bit name hcd hc description 310 amd geode? cs5535 companion device data book usb controller register descriptions 31506b 6.5.4.23 host controller root hub po rt status 2 (usbc_hcrhportstatus[2]) this register is reset by the usbreset state. note: there must be a device connect detected by the host to be able to set other bits. usb memory offset 58h type hcd: hc: r/w r/w reset value 00000000h usbc_hcrhportstatus[2] register map 313029282726252423222120191817161514131211109876543210 rsvd portresetstatuschange portovercurrentindicatorchange portsuspendstatuschange portenablestatuschange connectstatuschange rsvd dual function dual function rsvd dual function dual function dual function dual function dual function usbc_hcrhportstatus[2 ] bit descriptions bit name hcd hc description 31:21 rsvd r/w r/w reserved. read/write 0s. 20 portreset statuschange r/w r/w port reset status change. this bit indicates that the port reset signal has completed. 0: port reset is not complete. 1: port reset is complete. 19 portovercurrent indicatorchange r/w r/w port over current indicator change. this bit is set when over- currentindicator changes. writing a 1 clears this bit. writing a 0 has no effect. 18 portsuspend statuschange r/w r/w port suspend status change. this bit indicate s the completion of the selective resume sequence for the port. 0: port is not resumed. 1: port resume is complete. 17 portenable statuschange r/w r/w port enable status change. this bit indicates that the port has been disabled due to a hardware event (cleared portenablesta- tus). 0: port has not been disabled. 1: portenablestatus has been cleared. 16 connectstatus change r/w r/w connect status change. this bit indicates a connect or discon- nect event has been detected. writin g a 1 clears this bit. writing a 0 has no effect. 0: no connect/disconnect event. 1: hardware detection of connect/disconnect event. if deviceremoveable is set, this bit resets to 1. 15:10 rsvd r/w r/w reserved. read/write 0s. amd geode? cs5535 companion device data book 311 usb controller register descriptions 31506b 9 dual function r/w r/w read: low speed device attached. this bit defines the speed (and bud idle) of the attached device. it is only valid when cur- rentconnectstatus is set. 0: full speed device. 1: low speed device. write: clear port power. writing a 1 clears portpowerstatus. writing a 0 has no effect. 8 dual function r/w r/w read: port power status. this bit reflects the power state of the port regardless of the power switching mode. 0: port power is off. 1: port power is on. note: if nopowerswitching is set, th is bit is always read as 1. write: set port power. writing a 1 sets portpowerstatus. writ- ing a 0 has no effect. 7:5 rsvd r/w r/w reserved. read/write 0s. 4 dual function r/w r/w read: port reset status. 0: port reset signal is not active. 1: port reset signal is active. write: set port reset. writing a 1 sets portresetstatus. writing a 0 has no effect. 3 dual function r/w r/w read: port over current indicator. this bit reflects the state of the ovrcur pin dedicated to this port. this field is only valid if noovercurrentprotection is cl eared and overcurrentprotection- mode is set. 0: no over-current condition. 1: over-current condition. write: clear port suspend. writing a 1 initiates the selective resume sequence for the port. writing a 0 has no effect. 2 dual function r/w r/w read: port suspend status. 0: port is not suspended. 1: port is selectively suspended. write: set port suspend. writing a 1 sets portsuspendstatus. writing a 0 has no effect. 1 dual function r/w r/w read: port enable status. 0: port disabled. 1: port enabled. write: set port enable. writing a 1 sets portenablestatus. writ- ing a 0 has no effect. 0 dual function r/w r/w read: current connect status. 0: no device connected. 1: device connected. if deviceremoveable is set (not removable) this bit is always 1. write: clear port enable. writing 1 a clears portenablestatus. writing a 0 has no effect. usbc_hcrhportstatus[2] bit descriptions (continued) bit name hcd hc description 312 amd geode? cs5535 companion device data book diverse integration logic register descriptions 31506b 6.6 diverse integration logi c register descriptions all registers associated with diverse integration logic (divil) are msrs: standard geodelink device (gld) msrs divil specific msrs the msrs are accessed via the rdmsr and wrmsr pro- cessor instructions. the msr address is derived from the perspective of the cpu core. see section 4.2 "msr addressing" on page 59 for more details. all msrs are 64 bits, however, some divil msrs are called out as 32 bits. the divil (dd) treats writes to the upper 32 bits (i.e., bits [63:32] ) of the 32-bit msrs as don?t cares and always returns 0 on these bits. the standard geodelink device msrs are summarized in table 6-17 and the divil specific msrs are summarized in table 6-18. the reference column in the tables point to the page where the register maps and bit descriptions are listed. some notations in the reference column also point to other chapters. these msrs are physically located in the divil, but the descriptions are documented with the asso- ciated module and are listed here only for completeness. table 6-17. standard geodelink? device msrs summary msr address type register name reset value reference 51400000h ro gld capabilities msr (divil_gld_msr_cap) 00000000_002df0xxh page 317 51400001h r/w gld master configuration msr (divil_gld_msr_config) 00000000_0000f000h page 317 51400002h r/w gld smi msr (divil_g ld_msr_smi) 00000000_00000000h page 318 51400003h r/w gld error msr (divil_gld_msr_error) 00000000_00000000h page 321 51400004h r/w gld power management msr (divil_gld_msr_pm) 00000000_00000000h page 323 51400005h r/w gld diagnostic msr (divil_gld_msr_diag) 00000000_00000000h page 324 51400006h- 51400007h r/w dd reserved msrs (dd_msr_rsvd) (reads return 1; writes have no effect.) ffffffff_ffffffffh --- table 6-18. divil specific msrs summary msr address type register name reset value reference 51400008h r/w local bar - irq mapper (divil_lbar_irq) i/o space - use of this lbar is optional. irq mapper is always accessible via msr space. 00000000_00000000h page 325 51400009h r/w local bar - kel from usb host controller 1 (divil_lbar_kel1) memory space - first of two ways to access kel. kel operation is not dependent on kel1 or kel2 access. 00000000_00000000h page 326 5140000ah r/w local bar - kel from usb host controller 2 (divil_lbar_kel2) memory space - second of two ways to access kel. kel operation is not dependent on kel1 or kel2 access. 00000000_00000000h page 326 5140000bh r/w local bar - smb (divil_lbar_smb) i/o space - local base address register for smb controller native registers. 00000000_00000000h page 327 amd geode? cs5535 companion device data book 313 diverse integration logic register descriptions 31506b 5140000ch r/w local bar - gpio and icfs (divil_lbar_gpio) i/o space - local base address register for gpios and icfs. 00000000_00000000h page 328 5140000dh r/w local bar - mfgpts (divil_lbar_mfgpt) i/o space - local base address register for mfgpts. 00000000_00000000h page 329 5140000eh r/w local bar - acpi (divil_lbar_acpi) i/o space - local base address register for mfgpts. 00000000_00000000h page 330 5140000fh r/w local bar - power management support (divil_lbar_pms) i/o space - local base address register for power management support registers. 00000000_00000000h page 331 51400010h r/w local bar - flash chip select 0 (divil_lbar_flsh0) local base address register for flash controller, chip select 0. 00000000_00000000h page 332 51400011h r/w local bar - flash chip select 1 (divil_lbar_flsh1) local base address register for flash controller, chip select 1. 00000000_00000000h page 332 51400012h r/w local bar - flash chip select 2 (divil_lbar_flsh2) local base address register for flash controller, chip select 2. 00000000_00000000h page 332 51400013h r/w local bar - flash chip select 3 (divil_lbar_flsh3) local base address register for flash controller, chip select 3. 00000000_00000000h page 332 51400014h r/w legacy i/o space controls (divil_leg_io) legacy i/o space controls. 04000003h page 334 51400015h r/w ball options control (divil_ball_opts) controls ide and lpc pin options. 00000x7xh page 335 51400016h r/w soft irq (divil_soft_irq) software generated irq. 00000000h page 337 51400017h r/w soft reset (divil_soft_reset) software generated reset. 00000000h page 337 51400018h r/w nor flash control (norf_ctl) 00000000h page 520 (flash spec) 51400019h r/w nor flash timing for chip selects 0 and 1 (nortf_t01) 07770777h page 522 (flash spec) 5140001ah r/w nor flash timing for chip selects 2 and 3 (nortf_t23) 07770777h page 523 (flash spec) table 6-18. divil specific msrs summary (continued) msr address type register name reset value reference 314 amd geode? cs5535 companion device data book diverse integration logic register descriptions 31506b 5140001bh r/w nand flash data timing msr (nandf_data) 07770777h page 524 (flash spec) 5140001ch r/w nand flash control timing (nandf_ctl) 00000777h page 525 (flash spec) 5140001dh r/w flash reserved (nandf_rsvd) 00000000h page 525 (flash spec) 5140001eh r/w access control dma request (divil_ac_dma) 00000000h page 338 5140001fh r/w keyboard emulation logic control register (kelx_ctl) 00000010h page 365 (kel spec) 51400020h r/w irq mapper unrestricted y and z select low (pic_[y/z]sel_low) 00000000h page 350 (pic spec) 51400021h r/w irq mapper unre stricted y select high (pic_ysel_high) 00000000h page 351 (pic spec) 51400022h r/w irq mapper unrestricted z select low (pic_zsel_low) 00000000h page 350 (pic spec) 51400023h r/w irq mapper unrestricted z select high (pic_zsel_high) 00000000h page 351 (pic spec) 51400024h r/w irq mapper primary mask (pic_irqm_prim) 0000ffffh page 352 (pic spec) 51400025h r/w irq mapper lpc mask (pic_irqm_lpc) 00000000h page 352 (pic spec) 51400026h ro irq mapper extended interrupt request status low (pic_xirr_sts_low) xxxxxxxxh page 353 (pic spec) 51400027h ro irq mapper extended interrupt request status high (pic_xirr_sts_high) xxxxxxxxh page 354 (pic spec) 51400028h r/w mfgpt irq mask (mfgpt_irq) 00000000h page 484 (mfgpt spec) 51400029h r/w mfgpt nmi and reset mask (mfgpt_nr) 00000000h page 487 (mfgpt spec) 5140002ah r/w mfgpt reserved (mfgpt_rsvd) 00000000h page 488 (mfgpt spec) 5140002bh wo mfgpt clear setup test (mfgpt_setup) 00000000h page 488 (mfgpt spec) 5140002ch- 5140002fh r/w reserved. reads return 1. writes have no effect. ffffffffh --- 51400030h ro floppy port 3f2h shadow (flpy_3f2_shdw) xxh page 339 (floppy spec) 51400031h ro floppy port 3f7h shadow (flpy_3f7_shdw) xxh page 339 (floppy spec) 51400032h ro floppy port 372h shadow (flpy_372_shdw) xxh page 340 (floppy spec) 51400033h ro floppy port 377h shadow (flpy_377_shdw) xxh page 340 (floppy spec) 51400034h ro pic shadow (pic_shdw) xxh page 354 (pic spec) 51400035h r/w reserved. reads return 1. writes have no effect. ffffffffh --- table 6-18. divil specific msrs summary (continued) msr address type register name reset value reference amd geode? cs5535 companion device data book 315 diverse integration logic register descriptions 31506b 51400036h ro pit shadow (pit_shdw) 00h page 342 (pit spec) 51400037h r/w pit count enable (pit_cntrl) 03h page 342 (pit spec) 51400038h r/w uart1 primary dongle and modem interface (uart[1]_mod) 0xh page 380 (uart spec) 51400039h r/w uart1 secondary dongle and status (uart[1]_dong) xxh page 381 (uart spec) 5140003ah r/w uart1 interface configuration (uart[1]_conf) 42h page 382 (uart spec) 5140003bh r/w uart1 reserved msr (uart1_rsvd_msr) - reads return 1; writes have no effect. 11h --- 5140003ch r/w uart2 primary dongle and modem interface (uart[2]_mod) 0xh page 380 (uart spec) 5140003dh r/w uart2 secondary dongle and status (uart[2]_dong) xxh page 381 (uart spec) 5140003eh r/w uart2 interface configuration (uart[2]_conf) 42h page 382 (uart spec) 5140003fh r/w uart2 reserved msr (uart2_rsvd_msr) - reads return 1; writes have no effect. 11h --- 51400040h r/w dma mapper (dma_map) 0000h page 420 (dma spec) 51400041h ro dma shadow channel 0 mode (dma_shdw_ch0) 00xxh page 421 (dma spec) 51400042 ro dma shadow channel 1 mode (dma_shdw_ch1) 00xxh page 421 (dma spec) 51400043 ro dma shadow channel 2 mode (dma_shdw_ch2) 00xxh page 421 (dma spec) 51400044 ro dma shadow channel 3 mode (dma_shdw_ch3) 00xxh page 421 (dma spec) 51400045h ro dma shadow channel 4 mode (dma_shdw_ch4] 00xxh page 421 (dma spec) 51400046h ro dma shadow channel 5 mode (dma_shdw_ch5) 00xxh page 421 (dma spec) 51400047h ro dma shadow channel 6 mode (dma_shdw_ch6) 00xxh page 421 (dma spec) 51400048h ro dma shadow channel 7 mode (dma_shdw_ch7) 00xxh page 421 (dma spec) 51400049h ro dma shadow mask (dma_msk_shdw) 00ffh page 422 (dma spec) 5140024ah r/w reserved msr (rsvd_msr) - reads return 1; writes have no effect. 11h --- 5140024bh r/w reserved msr (rsvd_msr) - reads return 1; writes have no effect. 11h --- 5140004ch ro lpc address error (lpc_eaddr) 00000000h page 435 (lpc spec) table 6-18. divil specific msrs summary (continued) msr address type register name reset value reference 316 amd geode? cs5535 companion device data book diverse integration logic register descriptions 31506b 5140004dh ro lpc error status (lpc_estat) 00000000h page 436 (lpc spec) 5140004eh r/w lpc serial irq control (lpc_sirq) 00000000h page 436 (lpc spec) 5140004fh r/w lpc reserved (lpc_rsvd) 00000000h page 437 (lpc spec) 51400050h r/w pmc logic timer (pmc_ltmr) 00000000h page 496 (pmc spec) 51400051h r/w pmc reserved (pmc_rsvd) 00000000h page 496 (pmc spec) 51400052h- 51400053h r/w reserved msr (rsvd_msr) - reads return 1; writes have no effect. 11h --- 51400054h r/w rtc ram lock (rtc_ram_lock) 00h page 439 (rtc spec) 51400055h r/w rtc date of month alarm offset (rtc_doma_offset) 00h page 440 (rtc spec) 51400056h r/w rtc month alarm offs et (rtc_mona_offset) 00h page 440 (rtc spec) 51400057h r/w rtc century offset (rtc_cen_offset) 00h page 441 (rtc spec) 51400058h- 514000ffh r/w reserved msr (rsvd_msr) - reads return 1; writes have no effect. 11h --- table 6-18. divil specific msrs summary (continued) msr address type register name reset value reference amd geode? cs5535 companion device data book 317 diverse integration logic register descriptions 31506b 6.6.1 standard geodelink? device (gld) msrs 6.6.1.1 gld capabilities msr (divil_gld_msr_cap) 6.6.1.2 gld master configuratio n msr (divil_gld_msr_config) msr address 51400000h ty p e r o reset value 00000000_002df0xxh divil_gld_msr_cap register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd dev_id rev_id divil_gld_msr_cap bit descriptions bit name description 63:24 rsvd reserved. reads return 0. 23:8 dev_id device id. identifies module (2df0h). 7:0 rev_id revision id. identifies module revision. see amd geode? cs5535 companion device specification update document for value. msr address 51400001h ty p e r / w reset value 00000000_0000f000h divil_gld_msr_conf ig register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd fix_prefetch discard non_coh_wr non_coh_rd rsvd pri rsvd pid divil_gld_msr_config bit descriptions bit name description 63:19 rsvd reserved. reads return 0. writes have no effect. 18:16 fix_prefetch fixed read prefetch policy. 000: none. each read takes a complete trip to memory. 001: initial read 08 bytes. read next 8 only when requested. 010: initial read 16 bytes. read next 16 only when requested. 011: initial read 32 bytes. read next 32 only when requested. 100: initial read 32 bytes. read next 32 when 16 bytes left. 101, 110, and 111: reserved. 318 amd geode? cs5535 companion device data book diverse integration logic register descriptions 31506b 6.6.1.3 gld smi msr (divil_gld_msr_smi) the flags are set by internal conditions. the internal conditions are enabled if the en bit is 1. reading the flag bit returns the value; writing 1 clears the flag; writ ing 0 has no effect. (see section 4.8.3 "msr address 2: smi control" on page 74 for further smi/asmi generation details.) 15:14 discard read prefetch discard policy. 00: reserved. 01: discard all data not taken under current local bus grant. 10: discard all data on an y local bus transaction. 11: discard all data on any local bus write transaction. always use this value. 13 non_coh_wr non-coherent write. 0: write requests are coherent. 1: write requests are non-cohe rent. always use this value. 12 non_coh_rd non-coherent read. 0: read requests are coherent. 1: read requests are non-coherent. always use this value. 11:7 rsvd reserved. reads as 0. 6:4 pri priority level. always write 0. 3 rsvd (ro) reserved (read only). returns 0. 2:0 pid priority id. always write 0. msr address 51400002h ty p e r / w reset value 00000000_00000000h divil_gld_msr_sm i register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd pm1_cnt_ssmi_flag pm2_cnt_ssmi_flag kel_a20_asmi_flag dma_ssmi_flag lpc_ssmi_flag rsvd uart2_ssmi_flag uart1_ssmi_flag porta_init_asmi_flag porta_a20_asmi_flag kel_init_asmi_flag pm_asmi_flag pic_asmi_flag kel_ee_asmi_flag shtdwn_asmi_flag hlt_asmi_flag 313029282726252423222120191817161514131211109876543210 rsvd pm1_cnt_ssmi_en pm2_cnt_ssmi_en kel_a20_asmi_en dma_ssmi_en lpc_ssmi_en rsvd uart2_ssmi_en uart1_ssmi_en porta_init_asmi_en porta_a20_asmi_en kel_init_asmi_en pm_asmi_en pic_asmi_en kel_ee_asmi_en shtdwn_asmi_en hlt_asmi_en divil_gld_msr_config bit descriptions (continued) bit name description amd geode? cs5535 companion device data book 319 diverse integration logic register descriptions 31506b divil_gld_msr_smi bit descriptions bit name description 63:48 rsvd reserved. reads return 0. writes have no effect. 47 pm1_cnt_ssmi_ flag power management 1 control register ssmi flag. if high, records that an ssmi was generated on a write to pm1_cnt (acpi i/o of fset 08h). write 1 to clear; writing 0 has no effect. pm1_cnt_ssmi_en (bit 15) must be high to generate ssmi and set flag. 46 pm2_cnt_ssmi_ flag power management 2 control register ssmi flag. if high, records that an ssmi was generated on a write to pm2_cnt (acpi i/o offset 0ch). write 1 to clear; writing 0 has no effect. pm2_cnt_ssmi_en (bit 14) must be high to generate ssmi and set flag. 45 kel_a20_asmi_ flag kel gate a20 asmi flag. if high, records that an asmi was generated in the kel due to keyboard gate a20 signal change. write 1 to clear; writing 0 has no effect. kela20_asmi_en (bit 13) must be high to generate asmi and set flag. 44 dma_ssmi_ flag dma ssmi flag. if high, records that an ssmi was generated on the 8237s during dma. write 1 to clear; writing 0 has no effe ct. dma_ssmi_en (bit 12) must be high to generate ssmi and set flag. (also see sect ion 6.6.2.14 "access control dma request (divil_ac_dma)" on page 338.) 43 lpc_ssmi_flag lpc ssmi flag. if high, records that an ssmi was generated on the lpc during dma. write 1 to clear; writing 0 has no effect. lpc_ssmi_en (bit 11) must be high to gener- ate ssmi and set flag. (also see sectio n 6.6.2.14 "access control dma request (divil_ac_dma)" on page 338.) 42 rsvd reserved. reads return 0. writes have no effect. 41 uart2_ssmi_ flag uart2 ssmi flag. if high, records that an ssmi was generated on uart2 during dma. write 1 to clear; writing 0 has no ef fect. uart2_ssmi_en (bit 9) must be high to generate ssmi and set flag. (also see sect ion 6.6.2.14 "access control dma request (divil_ac_dma)" on page 338.) 40 uart1_ssmi_ flag uart1 ssmi flag. if high, records that an ssmi was generated on uart1 during dma. write 1 to clear; writing 0 has no ef fect. uart1_ssmi_en (bit 8) must be high to generate ssmi and set flag. (also see sect ion 6.6.2.14 "access control dma request (divil_ac_dma)" on page 338.) 39 porta_init_ asmi_flag port a init asmi flag. if high, records that an asmi was generated in the kel due to an init on port a (092h). write 1 to clear; writing 0 has no effect. porta_init_asmi_en (bit 7) must be high to generate asmi and set flag. 38 porta_a20_ asmi_flag port a a20 asmi flag. if high, records that an asmi was generated in the kel due to a a20 change on port a (092h). write 1 to clear; writing 0 has no effect. porta_a20_asmi_en (bit 6) must be high to generate asmi and set flag. 37 kel_init_asmi_ flag kel init asmi flag. if high, records that an asmi was generated in the kel due to a keyboard init sequence. write 1 to clear; writing 0 has no effect. kel_init_asmi_en (bit 5) must be high to generate asmi and set flag. 36 pm_asmi_flag power management asmi flag. if high, records that an asmi was generated in the power management logic. write 1 to clear; wr iting 0 has no effect. pm_asmi_en (bit 4) must be high to generate asmi and set flag. 35 pic_asmi_flag pic asmi flag. if high, records that an asmi was generated in the extended pic map- per. write 1 to clear; writing 0 has no effec t. pic_asmi_en (bit 3) must be high to gen- erate asmi and set flag. 34 kel_ee_asmi_ flag kel emulation event asmi flag. if high, records that an asmi was generated in the kel due to a kel emulation event. write 1 to clear; writing 0 has no effect. kel_ee_asmi_en (bit 2) must be high to generate asmi and set flag. 33 shtdwn_asmi_ flag shutdown asmi flag. if high, records that an asmi was generated on a shutdown special cycle. write 1 to clear; writing 0 ha s no effect. shtdwn_asmi_en (bit 1) must be high to generate asmi and set flag. 320 amd geode? cs5535 companion device data book diverse integration logic register descriptions 31506b 32 hlt_asmi_flag halt asmi flag. if high, records that an asmi was generated on a halt special cycle. write 1 to clear; writing 0 has no effect. hlt_asmi_en (bit 0) must be high to generate an asmi and set flag. 31:16 rsvd reserved. reads return 0. writes have no effect. 15 pm1_cnt_ssmi_ en power management 1 control register ssmi enable. write 1 to enable pm1_cnt_ssmi_flag (bit 47) and to allow wr ites to pm1_cnt (acpi i/o offset 08h) to generate an ssmi. 14 pm2_cnt_ssmi_ en power management 2 control register ssmi enable. write 1 to enable pm2_cnt_ssmi_flag (bit 46) and to allow writes to pm2_cnt (acpi i/o offset 0ch) to generate an ssmi. 13 kel_a20_asmi_ en kel gate a20 asmi enable. write 1 to enable kel_a20_asmi_flag (bit 45) and to allow a keyboard gate a20 signal change in the kel to generate an asmi. 12 dma_ssmi_en dma ssmi enable. write 1 to enable dma_ssmi_flag (bit 44) and to allow 8237s during dma to generate an ssmi. 11 lpc_ssmi_en lpc ssmi enable. write 1 to enable lpc_ssmi_flag (bit 43) and to allow the lpc to generate an ssmi. 10 rsvd reserved. reads return 0. writes have no effect. 9 uart2_ssmi_en uart2 ssmi enable. write 1 to enable uart2_ssmi_flag (bit 41) and to allow uart2 to generate an ssmi. 8 uart1_ssmi_en uart1 ssmi enable. write 1 to enable uart1_ssmi_flag (bit 40) and to allow uart1 to generate an ssmi. 7porta_init_ asmi_en port a init asmi enable. write 1 to enable porta_init_asmi_flag (bit 39) and to allow an init on port a in the kel to generate an asmi. 6 porta_a20_ asmi_en port a a20 asmi enable. write 1 to enable porta_a20_asmi_flag (bit 38) and to allow an a20 change on port a in the kel to generate an asmi. 5 kel_init_asmi_ en kel init asmi enable. write 1 to enable kel_init_asmi_flag (bit 37) and to allow a keyboard init sequence in the kel to generate an asmi. 4 pm_asmi_en power management asmi enable. write 1 to enable pm_asmi_flag (bit 36) and to allow the power management logic to generate an asmi. 3 pic_asmi_en pic asmi enable. write 1 to enable pic_asmi_f lag (bit 35) and to allow the extended pic mapper to generate an asmi. 2 kel_ee_asmi_ en kel emulation event asmi enable. write 1 to enable kel_ee_asmi_flag (bit 34) and to allow the kel to generate an asmi. 1 shtdwn_asmi_ en shutdown asmi enable. write 1 to enable shtdwn_asmi_flag (bit 33) and to allow a shutdown special cycle to generate an asmi. 0hlt_asmi_en halt asmi enable. write 1 to enable hlt_asmi_flag (bit 32) and to allow a halt special cycle to generate an asmi. divil_gld_msr_smi bit descriptions (continued) bit name description amd geode? cs5535 companion device data book 321 diverse integration logic register descriptions 31506b 6.6.1.4 gld error msr (divil_gld_msr_error) the flags are set by internal conditions. the internal conditions are enabled if the en bit is 1. reading the flag bit returns the value; writing 1 clears the flag; writing 0 has no effect. (see section 4.8.4 "msr address 3: error control" on page 78 for further on err generation details.) msr address 51400003h ty p e r / w reset value 00000000_00000000h divil_gld_msr_erro r register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd uart1xuart2_err_flag mem_lbar_decode_err_flag io_lbar_decode_err_flag rsvd shtdwn_err_flag nand_dist_err_flag rsvd dma_dma_err_flag lpc_dma_err_flag rsvd uart2_dma_err_flag uart1_dma_err_flag rsvd lpc_mast_err_flag lpc_slv_err_flag mast_resp_excep_flag repeat_ssmi_err_flag decode_err_flag lb_adap_bad_flag 313029282726252423222120191817161514131211109876543210 rsvd lpc_excp_en shtdwn_err_en nand_dist_err_en rsvd dma_dma_err_en lpc_dma_err_en rsvd uart2__dma_err_en uart1_dma_err_en rsvd lpc_mast_err_en lpc_slv_err_en mast_resp_excep_en repeat_ssmi_err_en decode_err_en lb_adap_bad_en divil_gld_msr_error bit descriptions bit name description 63:55 rsvd reserved. reads return 0. writes have no effect. 54 uart1xuart2_ err_flag uart1 and uart2 error flag. if high, records that an err was generated due to a collision between the two uarts. uart1 and uart2 are set to the same i/o address base. no chip selects are asserted and decode_err_flag (bit 33) is asserted. decode_err_en (bit 1) must be high to ge nerate err and set flag. write 1 to clear; writing 0 has no effect. 53 mem_lbar_ decode_ err_flag memory lbar decode error flag. if high, records that an err was generated due to a collision between one memory lbar and another memory lbar hit. in this case, no chip select is generated and decode_err_flag (bit 33) is asserted. decode_err_en (bit 1) must be high to ge nerate err and set flag. write 1 to clear; writing 0 has no effect. 52 io_lbar_ decode_err_ flag i/o lbar decode error flag. if high, records that an err was generated due to a collision between one i/o lbar and another i/o lbar hit. in this case, no chip select is generated and decode_err_flag (bit 33 ) is asserted.decode_err_en (bit 1) must be high to generate err and set flag. write 1 to clear; writing 0 has no effect. 51:48 rsvd reserved. reads return 0. writes have no effect. 47 shtdwn_ err_flag shutdown error flag. if high, records that an err was generated due to a shutdown cycle occurrence. shtdwn_err_en (bit 15) must be high to generate err and set flag. write 1 to clear; writing 0 has no effect. 322 amd geode? cs5535 companion device data book diverse integration logic register descriptions 31506b 46 nand_dist_ err_flag nand distract error flag. if high, records that an err was generated due to a nand distract error. nand_dist_err_en (bit 14) must be high to generate err and set flag. write 1 to clear; writing 0 has no effect. 45 rsvd reserved. reads return 0. writes have no effect. 44 dma_dma_ err_flag 8237 dma error flag. if high, records that an err was generated due to an access on the 8237s during dma. dma_dma_err_en (bit 12) must be high to generate err and set flag. write 1 to clear; writing 0 has no effect. 43 lpc_dma_ err_flag lpc dma error flag. if high, records that an err was generated due to an lpc access during dma. lpc_dma_err_en (bit 11) must be high to generate err and set flag. write 1 to clear; writing 0 has no effect. 42 rsvd reserved. reads return 0. writes have no effect. 41 uart2_dma_ err_flag uart2 dma error flag. if high, records that an err was generated due to a uart2 access during dma. uart2_dma_err_en (bit 9) must be high to generate err and set flag. write 1 to clear; writing 0 has no effect. 40 uart1_dma_ err_flag uart1 dma error flag. if high, records that an err was generated due to a uart1 access during dma. uart1_dma_err_en (bit 8) must be high to generate err and set flag. write 1 to clear; writing 0 has no effect. 39:38 rsvd reserved. reads return 0. writes have no effect. 37 lpc_mast_ err_flag lpc master error flag. if high, records that an err was generated on the lpc due to a master <=> geodelink adapter transacti on. lpc_mast_err_en (bit 5) must be high to generate err and set flag. write 1 to clear; writing 0 has no effect. 36 lpc_slv_ err_flag lpc slave error flag. if high, records that an err was generated on the lpc due to a slave <=> geodelink adapter transaction. lpc_slv_err_en (bit 4) must be high to generate err and set flag. write 1 to clear; writing 0 has no effect. 35 mast_resp_ excep_flag master response exception flag. if high, records that an err was generated due to the geodelink adapter detecting the excep bit set in a local bus master response packet. mast_resp_excp_en (bit 3) must be high to generat e err and set flag. write 1 to clear; writing 0 has no effect. 34 repeat_ssmi_ err_flag repeat ssmi error flag. if high, records that an err was generated due to a second ssmi occurring on an address before the first was cleared. repeat_ssmi_err_en (bit 2) must be high to generate err and set flag. write 1 to clear; writing 0 has no effect. 33 decode_err_ flag decode error flag. if high, records that an err was generated during the address decode cycle due to one or more devices being decoded to the same address. bits [54:52] record further information about th is type of error. decode_err_en (bit 1) must be high to generate err and set flag. write 1 to clear; writing 0 has no effect. 32 lb_adap_bad_ flag lbus adapter bad flag. if high, records that an err was generated due to the geodelink adapter detected an error at the geodelink interface (e.g., packet type not supported). lb_adap_bad_en (bit 0) must be high to generate err and set flag. write 1 to clear; writing 0 has no effect. 31:17 rsvd reserved. reads return 0. writes have no effect. 16 lpc_excp_en lpc exception enable. write 1 to enable excep bit in response packet for lpc address errors. 15 shtdwn_ err_en shutdown error enable. write 1 to enable shtdwn_err_flag (bit 47) and to allow a shutdown cycle to generate an err. 14 nand_dist_ err_en nand distract error enable. write 1 to enable nand_dist_err_flag (bit 46) and to allow a nand distract error to generate an err. 13 rsvd reserved. reads return 0. writes have no effect. divil_gld_msr_error bit de scriptions (continued) bit name description amd geode? cs5535 companion device data book 323 diverse integration logic register descriptions 31506b 6.6.1.5 gld power manageme nt msr (divil_gld_msr_pm) 12 dma_dma_ err_en 8237 dma error enable. write 1 to enable dma_dma_err_flag (bit 44) and to allow an access on the 8237s during dma to generate an err. 11 lpc_dma_ err_en lpc dma error enable. write 1 to enable lpc_dma_err_flag (bit 43) and to allow an lpc access during dma an lpc access during dma to generate an err. 10 rsvd reserved. reads return 0. writes have no effect. 9uart2_dma_ err_en uart2 dma error enable. write 1 to enable uart2_dma_err_flag (bit 41) and to allow uart2 accesses during dma to generate an err. 8uart1_dma _err_en uart1 dma error enable. write 1 to enable uart1_dma_err_flag (bit 40) and to allow uart1 accesses during dma to generate an err. 7:6 rsvd reserved. reads return 0. writes have no effect. 5 lpc_mast_ err_en lpc master error enable. write 1 to enable lpc_mast_err_flag (bit 37) and to allow master <=> geodelink adapter transactions to generate an err. 4lpc_slv_ err_en lpc slave error enable. write 1 to enable lpc_slv_err_flag (bit 36) and to allow slave <=> geodelink adapter transactions to generate an err. 3 mast_resp_ excep_en master response exception enable. write 1 to enable mast_resp_excep_flag (bit 35) and to allow when the geodelink adapter detects the excep bit set in a local bus master response packet to generate an err. 2 repeat_ssmi_ err_en repeat ssmi error enable. write 1 to enable repeat_ssmi_err_flag (bit 34) and to allow when a second ssmi occurs on an address before the first was cleared to generate an err. 1 decode_ err_en decode error enable. write 1 to enable flag bits [54:52] and to allow when one or more devices are decoded to the same address during the address decode cycle to generate an err. 0 lb_adap_ bad_en lbus adapter bad enable. write 1 to enable lb_adap_bad_flag (bit 32) and to allow when the geodelink adapter detects an error at the geodelink interface to gen- erate an err. msr address 51400004h ty p e r / w reset value 00000000_00000000h divil_gld_msr_pm register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 pmode15 pmode14 rsvd pmode11 pmode10 pmode9 pmode8 pmode7 pmode6 pmode5 pmode4 rsvd pmode2 pmode1 pmode0 divil_gld_msr_error bit de scriptions (continued) bit name description 324 amd geode? cs5535 companion device data book diverse integration logic register descriptions 31506b 6.6.1.6 gld diagnostic msr (divil_gld_msr_diag) this register is reserved for internal use by amd and should not be written to. divil_gld_msr_pm bit descriptions bit name description 63:48 rsvd reserved. reads return 0. writes have no effect. 47:46 rsvd reserved. do not write. reads return 0. 45:44 rsvd reserved. reads return 0. writes have no effect. 43:36 rsvd reserved. do not write. reads return 0. 35 rsvd reserved. reads return 0. writes have no effect. 34:32 rsvd reserved. do not write. reads return 0. 31:30 pmode15 power mode for gpio standby power domain 32 khz clock domain. 00: disable clock gating. clocks are always on. 01: enable active hardware clock gating. clock goes off whenever this module?s cir- cuits are not busy. 10: reserved. 11: reserved. 29:28 pmode14 power mode for gpio working power domain 32 khz clock domain. see bits [31:30] for decode. 27:24 rsvd reserved. reads will return the value written. 23:22 pmode11 power mode for mfgpt standby powe r domain 32 khz clock domain. see bits [31:30] for decode. 21:20 pmode10 power mode for mfgpt working po wer domain 32 khz clock domain. see bits [31:30] for decode. 19:18 pmode9 power mode for mfgpt working power domain 14 mhz clock domain. see bits [31:30] for decode. 17:16 pmode8 power mode for lpc. see bits [31:30] for decode. 15:14 pmode7 power mode for uart2. see bits [31:30] for decode. 13:12 pmode6 power mode for uart1. see bits [31:30] for decode. 11:10 pmode5 power mode for system management bus controller. see bits [31:30] for decode. 9:8 pmode4 power mode for dma (8237). see bits [31:30] for decode. 7:6 rsvd reserved. reads return 0. writes have no effect. 5:4 pmode2 power mode for pit (8254). see bits [31:30] for decode. 3:2 pmode1 power mode for geodelink adapter loca l bus interface an d local bus clock. see bits [31:30] for decode. 1:0 pmode0 power mode for geodelink adapter geodelink interface. see bits [31:30] for decode. msr address 51400005h ty p e r / w reset value 00000000_00000000h amd geode? cs5535 companion device data book 325 diverse integration logic register descriptions 31506b 6.6.2 divil specific msrs refer to section 5.6 "diverse integration logic" on page 104 for an explanation and block diagram of the address compari- son mechanism of the base address and the address lines. note that the i/o space 04ffh- 0000h is off limits to i/o lbars. 6.6.2.1 local bar - irq ma pper (divil_lbar_irq) see section 5.6.1 "lbars and comparators" on page 105 for operational details. the irq mapper takes 32 bytes of i/o space. use of this l bar is optional. the irq mapper is always available via msr space. msr address 51400008h ty p e r / w reset value 00000000_00000000h divil_lbar_irq register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd io_mask rsvd lbar_en 313029282726252423222120191817161514131211109876543210 rsvd base_addr rsvd divil_msr_lbar_irq bit descriptions bit name description 63:49 rsvd reserved. reads return 0; writes have no effect. 48 rsvd reserved. always write 0. 47:44 io_mask i/o address mask value. see discussion in section 5.6.1 "lbars and comparators" on page 105. 43:33 rsvd reserved. reads return 0; writes have no effect. 32 lbar_en lbar enable. 0: disable address detection by this lbar. 1: enable address detection by this lbar. 31:20 rsvd reserved. reads return 0; writes have no effect. 16 rsvd reserved. always write 0. 15:5 base_addr base address in i/o space. see discussion in section 5.6.1 "lbars and compara- tors" on page 105. 4:0 rsvd reserved. reads return 0; writes have no effect. 326 amd geode? cs5535 companion device data book diverse integration logic register descriptions 31506b 6.6.2.2 local bar - kel from usb ho st controller 1 (divil_lbar_kel1) see section 5.6.1 "lbars and comparators" on page 105 for operational details. the kel registers take 4 kb of memory space. however, onl y offsets 100h, 104h, 108h, and 10ch contain registers. all other writes are ?don?t care? and reads return 0. this is one of two kel lbars. each lbar ?hits? to the same kel. this allows usb host controllers at different addresses to be used, if desired. both lbars do not have to be used. 6.6.2.3 local bar - kel from usb ho st controller 2 (divil_lbar_kel2) see section 5.6.1 "lbars and comparators" on page 105 for operational details. the kel registers take 4 kb of memory space. however, onl y offsets 100h, 104h, 108h, and 10ch contain registers. all other writes are ?don?t care? and reads return 0. this is one of two kel lbars. each lbar "hits" to the same kel. this allows usb host controllers at different addresses to be used if desired. both lbars do not have to be used. msr address 51400009h ty p e r / w reset value 00000000_00000000h divil_lbar_kel1 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 mem_mask rsvd lbar_en 313029282726252423222120191817161514131211109876543210 base_addr rsvd divil_lbar_kel1 bit descriptions bit name description 63:44 mem_mask memory address mask value. see discussion in section 5.6.1 "lbars and compar- ators" on page 105 43:33 rsvd reserved. reads return 0; writes have no effect. 32 lbar_en lbar enable. 0: disable lbar. 1: enable lbar. 31:12 base_addr base address in memory space. see discussion in section 5.6.1 "lbars and com- parators" on page 105 11:0 rsvd reserved. reads return 0; writes have no effect. msr address 5140000ah ty p e r / w reset value 00000000_00000000h divil_lbar_kel2 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 mem_mask rsvd lbar_en 313029282726252423222120191817161514131211109876543210 base_addr rsvd amd geode? cs5535 companion device data book 327 diverse integration logic register descriptions 31506b 6.6.2.4 local bar - smb (divil_lbar_smb) see section 5.6.1 "lbars and comparators" on page 105 for operational details. the smb controller takes 8 bytes of i/o space. divil_lbar_kel2 bit descriptions bit name description 63:44 mem_mask memory address mask value. see discussion in section 5.6.1 "lbars and compar- ators" on page 105 43:33 rsvd reserved. reads return 0; writes have no effect. 32 lbar_en lbar enable. 0: disable lbar. 1: enable lbar. 31:12 base_addr base address in memory space. see discussion in section 5.6.1 "lbars and com- parators" on page 105 11:0 rsvd reserved. reads return 0; writes have no effect. msr address 5140000bh ty p e r / w reset value 00000000_00000000h divil_lbar_smb register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd io_mask rsvd lbar_en 313029282726252423222120191817161514131211109876543210 rsvd base_addr rsvd divil_lbar_smb bit name description 63:49 rsvd reserved. reads return 0; writes have no effect. 48 rsvd reserved. always write 0. 47:44 io_mask i/o address mask value. see discussion in section 5.6.1 "lbars and comparators" on page 105 43:33 rsvd reserved. reads return 0; writes have no effect. 32 lbar_en lbar enable. 0: disable lbar. 1: enable lbar. 31:17 rsvd reserved. reads return 0; writes have no effect. 16 rsvd reserved. always write 0. 15:3 base_addr base address in i/o space. see discussion in section 5.6.1 "lbars and compara- tors" on page 105 2:0 rsvd reserved. reads return 0; writes have no effect. 328 amd geode? cs5535 companion device data book diverse integration logic register descriptions 31506b 6.6.2.5 local bar - gpio an d icfs (divil_lbar_gpio) see section 5.6.1 "lbars and comparators" on page 105 for operational details. the gpios and icfs take 256 bytes of i/o space. msr address 5140000ch ty p e r / w reset value 00000000_00000000h divil_lbar_gpio register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd io_mask rsvd lbar_en 313029282726252423222120191817161514131211109876543210 rsvd base_addr rsvd divil_lbar_gpio bit description bit name description 63:49 rsvd reserved. reads return 0; writes have no effect. 48 rsvd reserved. always write 0. 47:44 io_mask i/o address mask value. see discussion in section 5.6.1 "lbars and comparators" on page 105 43:33 rsvd reserved. reads return 0; writes have no effect. 32 lbar_en lbar enable. 0: disable lbar. 1: enable lbar. 31:17 rsvd reserved. reads return 0; writes have no effect. 16 rsvd reserved. always write 0. 15:8 base_addr base address in i/o space. see discussion in section 5.6.1 "lbars and compara- tors" on page 105 7:0 rsvd reserved. reads return 0; writes have no effect. amd geode? cs5535 companion device data book 329 diverse integration logic register descriptions 31506b 6.6.2.6 local bar - mfgp ts (divil_lbar_mfgpt) see section 5.6.1 "lbars and comparators" on page 105 for o perational details. the mfgpts take 64 bytes of i/o space. msr address 5140000dh ty p e r / w reset value 00000000_00000000h divil_lbar_mfgpt register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd io_mask rsvd lbar_en 313029282726252423222120191817161514131211109876543210 rsvd base_addr rsvd divil_lbar_mfgpt bit descriptions bit name description 63:49 rsvd reserved. reads return 0; writes have no effect. 48 rsvd reserved. always write 0. 47:44 io_mask i/o address mask value. see discussion in section 5.6.1 "lbars and comparators" on page 105 43:33 rsvd reserved. reads return 0; writes have no effect. 32 lbar_en lbar enable. 0: disable lbar. 1: enable lbar. 31:17 rsvd reserved. reads return 0; writes have no effect. 16 rsvd reserved. always write 0. 15:6 base_addr base address in i/o space. see discussion in section 5.6.1 "lbars and compara- tors" on page 105 5 rsvd reserved. reads return value written. default valu e is 0. note that this bit is reserved and performs no function. 4:0 rsvd reserved. reads return 0; writes have no effect. 330 amd geode? cs5535 companion device data book diverse integration logic register descriptions 31506b 6.6.2.7 local bar - ac pi (divil_lbar_acpi) see section 5.6.1 "lbars and comparators" on page 105 for operational details. the acpi registers take 32 bytes of i/o space. offsets are as follows: 00h pm1_sts 02h pm1_en 08h pm1_cnt 0ch pm2_cnt 10h pm_tmr 14h reserved 18h gpe0_sts 1ch gpe0_en msr address 5140000eh ty p e r / w reset value 00000000_00000000h divil_lbar_acpi register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd io_mask rsvd lbar_en 313029282726252423222120191817161514131211109876543210 rsvd base_addr rsvd divil_lbar_acpi bit descriptions bit name description 63:49 rsvd reserved. reads return 0; writes have no effect. 48 rsvd reserved. always write 0. 47:44 io_mask i/o address mask value. see discussion in section 5.6.1 "lbars and comparators" on page 105 43:33 rsvd reserved. reads return 0; writes have no effect. 32 lbar_en lbar enable. 0: disable lbar. 1: enable lbar. 31:17 rsvd reserved. reads return 0; writes have no effect. 16 rsvd reserved. always write 0. 15:5 base_addr base address in i/o space. see discussion in section 5.6.1 "lbars and compara- tors" on page 105 4:0 rsvd reserved. reads return 0; writes have no effect. amd geode? cs5535 companion device data book 331 diverse integration logic register descriptions 31506b 6.6.2.8 local bar - power manage ment support (divil_lbar_pms) see section 5.6.1 "lbars and comparators" on page 105 for operational details. the power management support regis- ters take 128 bytes of i/o space. msr address 5140000fh ty p e r / w reset value 00000000_00000000h divil_lbar_pms register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd io_mask rsvd lbar_en 313029282726252423222120191817161514131211109876543210 rsvd base_addr rsvd divil_lbar_pms bit descriptions bit name description 63:49 rsvd reserved. reads return 0; writes have no effect. 48 rsvd reserved. always write 0. 47:44 io_mask i/o address mask value. see discussion in section 5.6.1 "lbars and comparators" on page 105 43:33 rsvd reserved. reads return 0; writes have no effect. 32 lbar_en lbar enable. 0: disable lbar. 1: enable lbar. 31:17 rsvd reserved. reads return 0; writes have no effect. 16 rsvd reserved. always write 0. 15:7 base_addr base address in i/o space. see discussion in section 5.6.1 "lbars and compara- tors" on page 105 6:0 rsvd reserved. reads return 0; writes have no effect. 332 amd geode? cs5535 companion device data book diverse integration logic register descriptions 31506b 6.6.2.9 local bar - flash chip select (divil_lbar_flsh[x]) see section 5.6.1 "lbars and comparators" on page 105 for operational details. the nand flash control registers take 16 bytes of i/o space. nor flash maps into some multiple of 4k bytes. there are two forms of this lbar depending on the space, memory or i/o, flash device 0 is mapped into. space is determined by bit 34 of the lbar. local bar - flash chip se lect 0 (divil_lbar_flsh0) uses flash_cs0# and flash_ce0#. local bar - flash chip select 1 (divil_lbar_flsh1) uses flash_cs1# and flash_ce1#. local bar - flash chip select 2 (divil_lbar_flsh2) uses flash_cs2# and flash_ce2#. local bar - flash chip select 3 (divil_lbar_flsh3) uses flash_cs3# and flash_ce3#. msr address 51400010h ty p e r / w reset value 00000000_00000000h msr address 51400011h ty p e r / w reset value 00000000_00000000h msr address 51400012h ty p e r / w reset value 00000000_00000000h msr address 51400013h ty p e r / w reset value 00000000_00000000h divil_lbar_flsh[x] register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd io_mask rsvd 0 nor_nand lbar_en mem_mask rsvd 1 nor_nand lbar_en 313029282726252423222120191817161514131211109876543210 rsvd base_addr rsvd base_addr rsvd divil_lbar_flsh[x] bit descriptions bit name description if bit 34 = 0; i/o mapped 63:49 rsvd reserved. reads return value wr itten. defaults to 0 48 rsvd reserved. always write 0. 47:36 io_mask i/o address mask value. for standard nand flash, bits [48:36] should be set to all 1s. add 0s from the lsbs as needed for oem s pecific devices that take more than 16 bytes.see discussion in section 5.6.1 "lbars and comparators" on page 105 35 rsvd reserved. reads return value written. defaults to 0. 34 mem_io memory or i/o mapped. 0: lbar is i/o mapped). 1: lbar is memory mapped. 33 nor_nand nor or nand. 0: use nor chip select (flash_cs[x]#). 1: use nand chip select (flash_ce[x]#). amd geode? cs5535 companion device data book 333 diverse integration logic register descriptions 31506b 32 lbar_en lbar enable. 0: disable lbar. 1: enable lbar. 31:17 rsvd reserved. reads return value written. defaults to 0. 16 rsvd reserved. always write 0. 15:4 base_addr base address in i/o space . see discussion in section 5.6.1 "lbars and compara- tors" on page 105 3:0 rsvd reserved. reads return value written. defaults to 0. if bit 34 = 1; memory mapped 63:44 mem_mask memory address mask value. see discussion in section 5.6.1 "lbars and compar- ators" on page 105 43:35 rsvd reserved. reads return value written. defaults to 0. 34 mem_io memory or i/o mapped. 0: lbar is i/o mapped. 1: lbar is memory mapped. 33 nor_nand nor or nand. 0: use nor chip select (flash_cs[x]#). 1: use nand chip select (flash_ce[x]#). 32 lbar_en lbar enable. 0: disable lbar. 1: enable lbar. 31:12 base_addr base address in memory space. see discussion in section 5.6.1 "lbars and com- parators" on page 105 11:0 rsvd reserved. reads return value written. defaults to 0. divil_lbar_flsh[x] bit de scriptions (continued) bit name description 334 amd geode? cs5535 companion device data book diverse integration logic register descriptions 31506b 6.6.2.10 legacy i/o space controls (divil_leg_io) msr address 51400014h ty p e r / w reset value 04000003h divil_leg_io register map 313029282726252423222120191817161514131211109876543210 reset_shut_en reset_bad_en rsvd spec_cyc_md 0x000e_xxxx 0x000f_xxxx lpc_disable_mem lpc_disable_io rsvd uart2_enable[2:0] rsvd uart1_enable[2:0] rsvd rtc_enable1 rtc_enable0 divil_leg_io bit description bit name description 31 reset_shut_ en shutdown reset enable if set, this bit will enable the issuance of the reset_out# signal upon the detect ion of a pci shutdown cycle from the geode gx processor (or any other pci master). the reason for the re set is recorded in the pm_ssc register (pms i/o offset 54h[9], see section 6.18.3.19 on page 517 for bit details). 0: do not issue reset_out# upon detection of shutdown cycle. 1: issue reset_out# upon det ection of shutdown cycle. 30 reset_bad_en bad transaction reset enable if set, this bit will enable a system wide reset via the reset_out# signal, if the geodelink adapt er detects a ?bad? geodelink transaction. the reason for the reset is recorded in th e pm_ssc register (pms i/o offset 54h[12], see section 6.18.3.19 on page 517 for bit details). 0: do not issue reset_out# upon de tection of a ?bad? transaction. 1: issue reset_out# upon detecti on of a ?bad? transaction 29 rsvd reserved: this bit should always be written to 0. 28 spec_cyc_md special cycle mode. allows selection of how the divil decodes local bus address for geodelink special cycles. (defaults 0.) 0: decode is per the pci spec: 00h: shutdown. 01h: halt. all other values ignored. 1: decode is per the x86 standard: 00h: shutdown. 02h: halt. all other values ignored. 27 0x000e_xxxx 000exxxxh remap. if high, memory addresses in the range of 000exxxxh are re- mapped to fffexxxxh. applies to addresses except the lb ar comparators and other address decode functions. (defaults 0.) 26 0x000f_xxxx 000fxxxxh remap. if high, memory addresses in the range of 000fxxxxh are re- mapped to ffffxxxxh. applies to addresses except the lbar co mparators and other address decode functions. (defaults 1.) 25 lpc_disable_ mem lpc disable memory. if high, discard all memory writes which would otherwise go to the lpc by default. for reads, return all 1s . ?default? means any address not explicitly mapped into on-chip memory space or claimed by an lbar hit. 24 lpc_disable_ io lpc disable i/o. if high, discard all i/o writes which would otherwise go to the lpc by default. for reads, return all 1s. ?default? means any address not explicitly mapped into on-chip legacy i/o space or claimed by an lbar hit. amd geode? cs5535 companion device data book 335 diverse integration logic register descriptions 31506b 6.6.2.11 ball options cont rol (divil_ball_opts) 23 rsvd reserved. reads return value written. defaults to 0. 22:20 uart2_enable [2:0] uart2 enable. 0xx: uart2 not enabled into divil i/o space; use lpc. 100: uart2 enabled into i/o base 02e8h (com4). 101: uart2 enabled into i/o base 02f8h (com3). 110: uart2 enabled into i/o base 03e8h (com2). 111: uart2 enabled into i/o base 03f8h (com1). if uart1 and uart2 are set to the same i/o base, a decode error is generated on access. 19 rsvd reserved. reads return value wr itten. defaults to 0 18:16 uart1_enable [2:0] uart1 enable. 0xx: uart1 not enabled into divil i/o space; use lpc. 100: uart1 enabled into i/o base 02e8h (com4). 101: uart1 enabled into i/o base 02f8h (com3). 110: uart1 enabled into i/o base 03e8h (com2). 111: uart1 enabled into i/o base 03f8h (com1). if uart1 and uart2 are set to the same i/o base, a decode error is generated on access. 15:2 rsvd reserved. reads return value written. defaults to 0 1 rtc_enable1 real-time clock map 1. routes i/o port locations 072h and 073h to the internal rtc high ram or lpc. 0: rtc high ram routed to lpc bus. 1: rtc high ram routed to internal rtc. (default) 0 rtc_enable0 real-time clock map 0. routes i/o port locations 070h and 071h internal rtc or lpc. writes to port 070h (index) are always routed internal. the msb is used to estab- lish the nmi enable state. 0: rtc routed to lpc bus. 1: rtc routed to internal rtc. (default) msr address 51400015h ty p e r / w reset value 00000x7xh divil_ball_opts register map 313029282726252423222120191817161514131211109876543210 rsvd sec_boot_loc boot_op_latched rsvd pin_opt_lall pin_opt_lirq pin_opt_ldrq pri_boot_loc[1:0] rsvd pin_opt_ide divil_leg_io bit description (continued) bit name description 336 amd geode? cs5535 companion device data book diverse integration logic register descriptions 31506b divil_ball_opts bit descriptions bit name description 31:12 rsvd reserved. reads always return 0. writes have no effect; by convention, always write 0. 11:10 sec_boot_loc secondary boot location. determines which chip select asserts for addresses in the range f00f0000h to f00f 3fffh. defaults to the same value as boot option: 00: lpc rom. 01: reserved. 10: flash. 11: firmware hub. 9:8 boot_op_ latched (ro) latched value of boot option (read only). for values, see table 3-5 "boot options selection" on page 34. 7 rsvd reserved. reads return value written. by convention, always write 0. defaults low. 6 pin_opt_lall all lpc pin option selection. 0: all lpc pins become gpios including lpc_drq# and lpc_serirq. ball h3 functions as gpio22 ball h2 functions as gpio16 ball j2 functions as gpio17 ball j1 functions as gpio18 ball k1 functions as gpio19 ball g1 functions as gpio20 ball g2 functions as gpio21 1: all lpc pins are controlled by t he lpc controller except lpc_drq# and lpc_serirq use are determined by bits [5:4]. (default) ball h3 functions as lpc_frame# ball h2 functions as lpc_ad0 ball j2 functions as lpc_ad1 ball j1 functions as lpc_ad2 ball k1 functions as lpc_ad3 when this bit is low, there is an im plied high for the lpc_disable_mem and lpc_disable_io bits in divil_leg _io (divil msr 51400014h[25:24]). 5 pin_opt_lirq lpc_serirq or gpio21 pin option selection. 0: ball g2 is gpio21. 1: ball g2 functions as lpc_serirq. (default) 4 pin_opt_ldrq lpc_drq# or gpio20 pin option selection. 0: ball g1 is gpio20. 1: ball g2 functions as lpc_drq#. (default) 3:2 pri_boot_loc [1:0] primary boot location. determines which chip select asserts for addresses at or above f0000000h, except those in the range specified by sec_boot_loc (bits [11:10]). defaults to the same value as boot option. 00: lpc rom. 01: reserved. 10: flash. 11: firmware hub. 1 rsvd reserved. reads return value written. by convention, always write 0. defaults low. 0 pin_opt_ide ide or flash controller pin function selection. 0: all ide pins associated with flash co ntroller. default if bos[1:0] = 10. 1: all ide pins associated with ide contro ller. default if bos[1:0] = 00 or 11. ide_irq0 is multiplexed with gpio2; therefore, this bit has no affect with regards to programming ide_irq0. see table 3-5 "boot options selection" on page 34 for bos[1:0] programming values. amd geode? cs5535 companion device data book 337 diverse integration logic register descriptions 31506b 6.6.2.12 soft irq (divil_soft_irq) 6.6.2.13 soft reset (divil_soft_reset) msr address 51400016h ty p e r / w reset value 00000000h divil_soft_irq register map 313029282726252423222120191817161514131211109876543210 rsvd soft_irq divil_soft_irq bit descriptions bit name description 31:1 rsvd reserved. reads return 0. writes have no effect. 0 soft_irq soft irq. this bit can be written high or low. and is connected to the soft irq input of the irq mapper. hence, writing high causes an interrupt while writing low clears it. reads return the value written. msr address 51400017h ty p e r / w reset value 00000000h divil_soft_reset register map 313029282726252423222120191817161514131211109876543210 rsvd soft_reset divil_soft_reset bit descriptions bit name description 31:1 rsvd reserved. reads return 0. writes have no effect. 0 soft_reset soft reset. a bit that when written to a 1 c auses the system to hard reset. reads return 0. 338 amd geode? cs5535 companion device data book diverse integration logic register descriptions 31506b 6.6.2.14 access control dm a request (divil_ac_dma) the controls below only affect memory and i/o accesses to the target slaves. msr accesses are not affected. however, msr writes during dma may have unintended side effects. note that when in demand or block mode, the uart reads and writes are disallowed; no corresponding mechanism exists to allow uart controller reads or writes during uart activi ty. if attempted, cpu writes ha ve no effect and the cpu reads return all 1s. the enables default to 0. if 0, reads or writes to the indicated device are blocked during activity. this may cause an ssmi or error if enabled by the associated msr. thus, writes are discarded and reads return all fs. if an enable is 0, a chip select for the indicated device is not asserted. if an enable is 1, the indicated device is available for access during activit y. msr address 5140001eh ty p e r / w reset value 00000000h divil_ac_dma register map 313029282726252423222120191817161514131211109876543210 rsvd ac_dma_w ac_dma_r rsvd ac_dma_lpc_iw ac_dma_lpc_ir ac_dma_lpc_mw ac_dma_lpc_mr divil_ac_dma bi t descriptions bit name description 31:18 rsvd reserved. reads return 0; writes have no effect. 17 ac_dma_w allow dma writes during dma activity. if set, this bit allows writes to the dma con- troller during dma activity (data transfers). this mechanism may be used, among other things, to abort a hung dma transfer. if clear, dma controller writes are locked out dur- ing dma activity. 16 ac_dma_r allow dma reads duri ng dma activity. if set, this bit allows reads from the dma controller during dma activity (data transfers). if clear, dma controller reads are locked out during dma activity. 15:4 rsvd reserved. reads return 0; writes have no effect. 3 ac_dma_lpc_ iw lpc i/o writes during lpc dma if set, this bit allows i/o writes to the lpc bus during lpc dma transfer. if clear, i/o writes are locked out during lpc dma transfers. 2 ac_dma_lpc_ir lpc i/o reads during lpc dma. if set, this bit allows i/o reads to the lpc bus during lpc dma transfer. if clear, i/o reads are locked out during lpc dma transfers. 1 ac_dma_lpc_ mw lpc memory writes during lpc dma. if set, this bit allows memory writes to the lpc bus during lpc dma transfer. if clear, memory writes are locked out during lpc dma transfers. 0 ac_dma_lpc_ mr lpc memory reads during lpc dma. if set, this bit allows memory reads to the lpc bus during lpc dma transfer. if clear, memory reads are locked out during lpc dma transfers. amd geode? cs5535 companion device data book 339 floppy port register descriptions 31506b 6.7 floppy port re gister descriptions the registers for the floppy port are divided into two sets: standard geodelink device (gld) msrs (shared with divil, see section 6.6.1 "standard geodelink? device (gld) msrs" on page 317.) floppy port specific msrs the msrs are accessed via the rdmsr and wrmsr pro- cessor instructions. the msr address is derived from the perspective of the cpu core. see section 4.2 "msr addressing" on page 59 for more details. all msrs are 64 bits, however, the floppy port specific msrs are called out as 8 bits. the floppy port treats writes to the upper 56 bits (i.e., bits [63:8]) of the 8-bit msrs as don?t cares and always returns 0 on these bits. table 6-19 summarizes the floppy port specific msrs. the reference column in the tables point to the page where the register maps and bit descriptions are listed. 6.7.1 floppy port specific msrs 6.7.1.1 floppy port 3f2h shadow (flpy_3f2_shdw) 6.7.1.2 floppy port 3f7h shadow (flpy_3f7_shdw) table 6-19. floppy port specific msrs summary msr address type register name reset value reference 51400030h ro floppy port 3f2h shadow (flpy_3f2_shdw) xxh page 339 51400031h ro floppy port 3f7h shadow (flpy_3f7_shdw) xxh page 339 51400032h ro floppy port 372h shadow (flpy_372_shdw) xxh page 340 51400033h ro floppy port 377h shadow (flpy_377_shdw) xxh page 340 msr address 51400030h ty p e r o reset value xxh flpy_3f2_shdw register map 76543210 flpy_port_3f2_val flpy_3f2_shdw bit descriptions bit name description 7:0 flpy_port_3f2 _val floppy port shadow register value last written to i/o port 3f2h. required for support of fdc power on/off and ze ro volt suspend/resume coherency. this register is a copy of an i/o register t hat cannot safely be directly read. value in reg- ister is not deterministic of when the register is being read. it is provided here to assist in a save-to-disk operation. msr address 51400031h ty p e r o reset value xxh flpy_3f7_shdw register map 76543210 flpy_port_3f7_val 340 amd geode? cs5535 companion device data book floppy port register descriptions 31506b 6.7.1.3 floppy port 372h shadow (flpy_372_shdw) 6.7.1.4 floppy port 377h shadow (flpy_377_shdw) flpy_3f7_shdw bit descriptions bit name description 7:0 flpy_port_3f7 _val floppy port shadow register value last written to i/o port 3f7h. required for support of fdc power on/off and ze ro volt suspend/resume coherency. this register is a copy of an i/o register t hat cannot safely be directly read. value in reg- ister is not deterministic of when the register is being read. it is provided here to assist in a save-to-disk operation. msr address 51400032h ty p e r o reset value xxh flpy_372_shdw register map 76543210 flpy_port_372_val flpy_372_shdw bit descriptions bit name description 7:0 flpy_port_372 _val floppy port shadow register valu e last written to i/o port 372h. required for support of fdc power on/off and ze ro volt suspend/resume coherency. this register is a copy of an i/o register t hat cannot safely be directly read. value in reg- ister is not deterministic of when the register is being read. it is provided here to assist in a save-to-disk operation. msr address 51400033h ty p e r o reset value xxh flpy_377_shdw register map 76543210 flpy_port_377_val flpy_377_shdw bit descriptions bit name description 7:0 flpy_port_377 _val floppy port shadow register valu e last written to i/o port 377h. required for support of fdc power on/off and ze ro volt suspend/resume coherency. this register is a copy of an i/o register t hat cannot safely be directly read. value in reg- ister is not deterministic of when the register is being read. it is provided here to assist in a save-to-disk operation. amd geode? cs5535 companion device data book 341 programmable interval timer register descriptions 31506b 6.8 programmable interval ti mer register descriptions the registers for the progra mmable interval timer (pit) are divided into three sets: standard geodelink device (gld) msrs (shared with divil, see secti on 6.6.1 on page 317.) pit specific msrs pit native registers the msrs are accessed via the rdmsr and wrmsr pro- cessor instructions. the msr address is derived from the perspective of the cpu core. see section 4.2 "msr addressing" on page 59 for more details. all msrs are 64 bits, however, the pit specific msrs are called out as 8 bits. the pit treats writes to the upper 56 bits (i.e., bits [63:8]) of th e 64-bit msrs as don?t cares and always returns 0 on these bits. the pit specific msrs are summarized in table 6-20. the native registers associat ed with the pit are summa- rized in table 6-21 and are accessed as i/o addresses. the reference column in the tables point to the page where the register maps and bit descriptions are listed. table 6-20. pit specific msrs summary msr address type register name reset value reference 51400036h ro pit shadow (pit_shdw) 00h page 342 51400037h r/w pit count enable (pit_cntrl) 03h page 342 table 6-21. pit native registers summary i/o address type width (bits) register name reset value reference 40h w 8 pit timer 0 counter - system (pit_tmr0_cntr_sys) 00h page 343 r 8 pit timer 0 status - system (pit_tmr0_sts_sys) 00h page 344 41h w 8 pit timer 1 counter - refresh (pit_tmr1_cntr_rfsh) 00h page 345 r 8 pit timer 1 status - refresh (pit_tmr1_sts_rfsh) 00h page 345 42h w 8 pit timer 2 counter - speaker (pit_tmr2_cntr_spkr) 00h page 346 r 8 pit timer 2 status - speaker (pit_tmr2_sts_spkr) 00h page 346 43h r/w 8 pit mode control word (pit_modectl_word) 00h page 347 61h r/w 8 port b control (pit_portbctl) 00h page 348 342 amd geode? cs5535 companion device data book programmable interval timer register descriptions 31506b 6.8.1 pit specific msrs 6.8.1.1 pit shad ow (pit_shdw) 6.8.1.2 pit count enable (pit_cntrl) msr address 51400036h ty p e r o reset value 00h pit_shdw register map 76543210 pit_shdw pit_shdw bit descriptions bit name description 7:0 pit_shdw (ro) pit shadow (read only). this 8-bit port sequences through the following list of shad- owed programmable interval timer registers. at power on, a pointer starts at the first register in the list and consecutively reads to increment through it. a write to this regis- ter resets the read sequence to the first regi ster. each shadow register in the sequence contains the last data written to that location. the read sequence for this register is: 1. counter 0 lsb (least significant byte) 2. counter 0 msb 3. counter 1 lsb 4. counter 1 msb 5. counter 2 lsb 6. counter 2 msb 7. counter 0 command word 8. counter 1 command word 9. counter 2 command word note: the lsb / msb of the count is the counter base value, not the current value. in the case of counter mode 3, the lsb of th e count is the counter base value - 1 (even count value). bits [7:6] of the command words are not used. msr address 51400037h ty p e r / w reset value 03h pit_cntrl register map 76543210 rsvd pit_cntr_ acc_dly_en rsvd pit_cntr1_ en pit_cntr0_ en pit_cntrl bit descriptions bit name description 7:5 rsvd reserved. read zero. write ?don?t care?. amd geode? cs5535 companion device data book 343 programmable interval timer register descriptions 31506b 6.8.2 pit native registers 6.8.2.1 pit timer 0 counter - system (pit_tmr0_cntr_sys) 4 pit_cntr_acc_ dly_en pit counter access delay enable. used as an access delay enable for the read and write operations of the pit counters. this bit introduces a 1 s delay between succes- sive reads and/or writes of the pit counters. this bit is intended to ensure that older, dos-based programs that rely on the pit ti ming access to be 1 s still function prop- erly. 0: disable access delay. 1: enable access delay. 3:2 rsvd reserved. read zero. write ?don?t care?. 1pit_cntr1_en pit counter 1 enable. 0: sets gate1 input low. 1: sets gate1 input high. 0pit_cntr0_en pit counter 0 enable. 0: sets gate0 input low. 1: sets gate0 input high. note: pit_cntr2_en (pit counter 2 enable) bi t is located at i/o address 61h[0] (see section 6.8.2.8 "port b control (pit_portbctl)" on page 348). pit_cntrl bit descriptions (continued) bit name description i/o address 40h ty p e w reset value 00h pit_tmr0_cntr_sys_ register map 76543210 cntr0 pit_tmr0_cntr_sys bit description bit name description 7:0 cntr0 counter 0 value. provides the base counter value. 344 amd geode? cs5535 companion device data book programmable interval timer register descriptions 31506b 6.8.2.2 pit timer 0 status - system (pit_tmr0_sts_sys) i/o address 40h ty p e r reset value 00h pit_tmr0_sts_sys register map 76543210 i/o address 43h[7:0] = 1101xx10 or 0010xxxx cntr0_cur_count i/o address 43h[7:0] = 11110xx10 cntr0_out cntr0_load cntr0_rw cntr0_mode bcd pit_tmr0_sts_sys bit descriptions bit name description i/o address 43h[7:0] = 1101xx10 or 0010xxxx 7:0 cntr0_cur_ count counter 0 current count. reports the current count value in counter 0. i/o address 43h[7:0] = 11110xx10 7 cntr0_out counter 0 output. returns current state of counter output signal. 6 cntr0_load counter 0 loaded. last count written is loaded? 0: yes. 1: no. 5:4 cntr0_rw counter 0 read /write mode. 00: counter latch command. 01: r/w lsb only. 10: r/w msb only. 11: r/w lsb, followed by msb. 3:1 cntr0_mode counter 0 current mode. 000: interrupt on terminal count. 001: programmable one-shot. 010, 110: rate generator. 011, 111: square wave generator. 100: software triggered pulse generator. 101: hardware triggered pulse generator. 0bcd bcd mode. 0: binary. 1: bcd (binary coded decimal). amd geode? cs5535 companion device data book 345 programmable interval timer register descriptions 31506b 6.8.2.3 pit timer 1 counter - refresh (pit_tmr1_cntr_rfsh) 6.8.2.4 pit timer 1 status - refresh (pit_tmr1_sts_rfsh) i/o address 41h ty p e w reset value 00h pit_tmr1_cntr_rfsh register map 76543210 cntr1 pit_tmr1_cntr_rfsh bit description bit name description 7:0 cntr1 counter 1 value. provides the base counter value. i/o address 41h ty p e r reset value 00h pit_tmr1_sts_rfsh register map 76543210 i/o address 43h[7:0] = 1101x1x0 or 0110xxxx cntr1_cur_count i/o address 43h[7:0] = 1110x1x0 cntr1_out cntr1_load cntr1_rw cntr1_mode bcd pit_tmr1_sts_rfsh bit descriptions bit name description i/o address 43h[7:0] = 1101x1x0 or 0110xxxx 7:0 cntr1_cur_ count counter 1 current count. reports the current count value in counter 1. i/o address 43h[7:0] = 1110x1x0 7 cntr1_out counter 1 output. returns current state of counter output signal. 6 cntr1_load counter 1 loaded. last count written is loaded? 0: yes. 1: no. 5:4 cntr1_rw counter 1 read /write mode. 00: counter latch command. 01: r/w lsb only. 10: r/w msb only. 11: r/w lsb, followed by msb. 346 amd geode? cs5535 companion device data book programmable interval timer register descriptions 31506b 6.8.2.5 pit timer 2 counter - speaker (pit_tmr2_cntr_spkr) 6.8.2.6 pit timer 2 status - speaker (pit_t mr2_sts_spkr) 3:1 cntr1_mode counter 1 current mode. 000: interrupt on terminal count. 001: programmable one-shot. 010, 110: rate generator. 011, 111: square wave generator. 100: software triggered pulse generator. 101: hardware triggered pulse generator. 0bcd bcd mode. 0: binary. 1: bcd (binary coded decimal). i/o address 42h ty p e w reset value 00h pit_tmr2_cntr_spkr register map 76543210 cntr2 pit_tmr2_cntr_spkr bit description bit name description 7:0 cntr2 counter 2 value. provides the base counter value. i/o address 42h ty p e r reset value 00h pit_tmr2_sts_sp kr register map 76543210 i/o address 43h[7:0] = 11011xx0 or 1000xxxx cntr2_cur_count i/o address 43h[7:0] = 11101xx0 cntr2_out cntr2_load cntr2_rw cntr2_mode bcd pit_tmr2_sts_spkr bit descriptions bit name description i/o address 43h[7:0] = 11011xx0 or 1000xxxx 7:0 cntr2_cur_ count counter 2 current count. reports the current count value in counter 2. pit_tmr1_sts_rfsh bit descriptions (continued) bit name description amd geode? cs5535 companion device data book 347 programmable interval timer register descriptions 31506b 6.8.2.7 pit mode control word (pit_modectl_word) i/o address 43h[7:0] = 11101xx0 7 cntr2_out counter 2 output. returns current state of counter output signal. 6 cntr2_load counter 2 loaded. last count written is loaded? 0: yes. 1: no. 5:4 cntr2_rw counter 2 read /write mode. 00: counter latch command. 01: r/w lsb only. 10: r/w msb only. 11: r/w lsb, followed by msb. 3:1 cntr2_mode counter 2 current mode. 000: interrupt on terminal count. 001: programmable one-shot. 010, 110: rate generator. 011, 111: square wave generator. 100: software triggered pulse generator. 101: hardware triggered pulse generator. 0bcd bcd mode. 0: binary. 1: bcd (binary coded decimal). i/o address 43h ty p e r / w reset value 00h pit_modectl_word register map 76543210 cntr_sel r/w_mode cntr_mode bcd pit_modectl_word bit descriptions bit name description 7:6 cntr_sel counter select. 00: counter 0. 01: counter 1. 10: counter 2. 11: read-back command (note 1). 5:4 rw_mode current read/write mode. 00: counter latch command (note 2). 01: r/w lsb only. 10: r/w msb only. 11: r/w lsb, followed by msb. pit_tmr2_sts_spkr bit descriptions (continued) bit name description 348 amd geode? cs5535 companion device data book programmable interval timer register descriptions 31506b 6.8.2.8 port b cont rol (pit_portbctl) 3:1 cntr_mode current counter mode. 000: interrupt on terminal count. 001: programmable one-shot. 010, 110: rate generator. 011, 111: square wave generator. 100: software triggered pulse generator. 101: hardware triggered pulse generator. 0bcd bcd mode. 0: binary. 1: bcd (binary coded decimal). note 1. if bits [7:6] = 11: register functions as read status command bit 5 = latch count, bit 4 = latch status, bit 3 = select coun ter 2, bit 2 = select counter 1, bit 1 = select counter 0, and bit 0 = reserved. note 2. if bits [5:4] = 00: register functions as coun ter latch command bits [7:6] = selects counter , and [3:0] = don?t care. i/o address 61h ty p e r / w reset value 00h pit_portbctl register map 76543210 rsvd out2_sts toggle rsvd pit_cntr2_ spkr pit_cntr2_ en pit_portbctl bit descriptions bit name description 7:6 rsvd reserved. read 0. write ?don?t care?. 5 out2_sts (ro) pit counter 2 out state (read only). this bit reflects the current status of the pit counter 2 output (out2). write ?don?t care?. 4 toggle (ro) toggle (read only). this bit toggles on every falling edge of counter 1 output (out1). write ?don?t care?. 3:2 rsvd reserved. read 0. write ?don?t care?. 1pit_cntr2_ spkr pit counter 2 (speaker). 0: forces speaker output to 0. 1: allows counter 2 output (out2) to pass to the speaker (i.e., the ac_beep signal; a mux option on gpio1). 0pit_cntr2_en pit counter 2 enable. 0: sets gate2 input low. 1: sets gate2 input high. pit_modectl_word bit descriptions (continued) bit name description amd geode? cs5535 companion device data book 349 programmable interrupt controller register descriptions 31506b 6.9 programmable interrupt cont roller register descriptions the registers for the progra mmable interrupt controller (pic) are divided into three sets: standard geodelink device (gld) msrs (shared with divil, see secti on 6.6.1 on page 317.) pic specific msrs pic native registers the msrs are accessed via the rdmsr and wrmsr pro- cessor instructions. the msr address is derived from the perspective of the cpu core. see section 4.2 "msr addressing" on page 59 for more details. all msrs are 64 bits, however, the pic specific msrs are called out as 32 and 8 bits. the pic treats writes to the upper 32/56 bits (i.e., bits [63:32/63:8]) of the 64-bit msrs as don?t cares and always returns 0 on these bits. the pic specific msrs are also accessible in i/o space via msr_lbar_irq (msr 51400008h), except for msr_pic_shdw (msr 51400034h ) . see section 6.6.2.1 "local bar - irq mapper (divil_lbar_irq)" on page 325. the native registers associated with the pic are summa- rized in table 6-23 on page 349 and are accessed as i/o addresses. the reference column in the summary tables point to the page where the register maps and bit descriptions are listed. table 6-22. pic specific msrs summary msr address pic i/o offset type register name reset value reference 51400020h 00h r/w irq mapper unrestricted y select low (pic_ysel_low) 00000000h page 350 51400021h 04h r/w irq mapper unrestricted y select high (pic_ysel_high) 00000000h page 351 51400022h 08h r/w irq mapper unrestricted z select low (pic_zsel_low) 00000000h page 350 51400023h 0ch r/w irq mapper unrestricted z select high (pic_zsel_high) 00000000h page 351 51400024h 10h r/w irq mapper primary mask (pic_irqm_prim) 0000ffffh page 352 51400025h 14h r/w irq mapper lpc mask (pic_irqm_lpc) 00000000h page 352 51400026h 18h ro irq mapper extended interrupt request status low (pic_xirr_sts_low) xxxxxxxxh page 353 51400027h 1ch ro irq mapper extended interrupt request status high (pic_xirr_sts_high) xxxxxxxxh page 354 51400034h --- ro pic shadow (pic_shdw) xxh page 355 table 6-23. pic native registers summary i/o address type width (bits) register name reset value reference 020h wo 8 initialization command word 1 (pic_icw1) - master 00h page 357 0a0h wo 8 initialization command word 1 (pic_icw1) - slave 00h page 357 021h wo 8 initialization command word 2 (pic_icw2) - master 00h page 357 0a1h wo 8 initialization command word 2 (pic_icw2) - slave 00h page 357 021h wo 8 initialization command word 3 (pic_icw3) - master 00h page 358 0a1h wo 8 initialization command word 3 (pic_icw3) - slave 00h page 358 021h wo 8 initialization command word 4 (pic_icw4) - master 00h page 358 0a1h wo 8 initialization command word 4 (pic_icw4) - slave 00h page 358 350 amd geode? cs5535 companion device data book programmable interrupt controller register descriptions 31506b 6.9.1 pic specific msrs 6.9.1.1 irq mapper unrestricted y and z select low (pic_[y/z]sel_low) irq mapper unrestricted y select low (pic_ysel_low) irq mapper unrestricted z select low (pic_zsel_low) 021h r/w 8 operation command word 1 / interrupt mask (pic_ocw1/imr) - master 00h page 359 0a1h r/w 8 operation command word 1 / interrupt mask (pic_ocw1/imr) - slave 00h page 359 020h wo 8 operation command word 2 (pic_ocw2) - master 00h page 359 0a0h wo 8 operation command word 2 (pic_ocw2) - slave 00h page 359 020h wo 8 operation command word 3 (pic_ocw3) - master 00h page 360 0a0h wo 8 operation command word 3 (pic_ocw3) - slave 00h page 360 020h ro 8 interrupt request regist er (pic_irr) - master 00h page 361 0a0h ro 8 interrupt request register (pic_irr) - slave 00h page 361 020h ro 8 in-service register (pic_isr) - master 00h page 361 0a0h ro 8 in-service register (pic_isr) - slave 00h page 361 4d0h r/w 8 interrupt edge/level sele ct 1 (pic_int_sel1) 00h page 362 4d1h r/w 8 interrupt edge/level sele ct 2 (pic_int_sel2) 00h page 363 table 6-23. pic native registers summary (continued) i/o address type width (bits) register name reset value reference msr address 51400020h pic i/o offset 00h ty p e r / w reset value 00000000h msr address 51400022h pic i/o offset 08h ty p e r / w reset value 00000000h pic_[y/z]sel_low register map 313029282726252423222120191817161514131211109876543210 map_[y/z]7 map_[y/z]6 map_[y/z]5 map_[y/z]4 map_[y/z]3 map_[y/z]2 map_[y/z]1 map_[y/z]0 pic_[y/z]sel_low bit descriptions bit name description 31:28 map_[y/z]7 map unrestricted [y/z] input 7. 0000: disable 0100: ig4 1000: ig8 1100: ig12 0001: ig1 0101: ig5 1001: ig9 1101: ig13 0010: ig2 0110: ig6 1010: ig10 1110: ig14 0011: ig3 0111: ig7 1011: ig11 1111: ig15 for unrestricted y and z inputs [7:0] sources, see table 5-13 and table 5-14 on page 113. 27:24 map_[y/z]6 map unrestricted [y/z] input 6. see bits [31:28] for decode. 23:20 map_[y/z]5 map unrestricted [y/z] input 5. see bits [31:28] for decode. 19:16 map_[y/z]4 map unrestricted [y/z] input 4. see bits [31:28] for decode. 15:12 map_[y/z]3 map unrestricted [y/z] input 3. see bits [31:28] for decode. amd geode? cs5535 companion device data book 351 programmable interrupt controller register descriptions 31506b 6.9.1.2 irq mapper unrestricted y an d z select high (pic_[y/z]sel_high) irq mapper unrestricted y select high (pic_ysel_high) irq mapper unrestricted z select high (pic_zsel_high) 11:8 map_[y/z]2 map unrestricted [y/z] input 2. see bits [31:28] for decode. 7:4 map_[y/z]1 map unrestricted [y/z] input 1. see bits [31:28] for decode. 3:0 map_[y/z]0 map unrestricted [y/z] input 0. see bits [31:28] for decode. pic_[y/z]sel_low bit descriptions bit name description msr address 51400021h pic i/o offset 04h ty p e r / w reset value 00000000h msr address 51400023h pic i/o offset 0ch ty p e r / w reset value 00000000h pic_[y/z]sel_high register map 313029282726252423222120191817161514131211109876543210 map_[y/z]15 map_[y/z]14 map_[y/z]13 map_[y/z]12 map_[y/z]11 map_[y/z]10 map_[y/z]9 map_[y/z]8 pic_[y/z]sel_high bit descriptions bit name description 31:28 map_[y/z]_15 map unrestricted [y/z] input 15. 0000: disable 0100: ig4 1000: ig8 1100: ig12 0001: ig1 0101: ig5 1001: ig9 1101: ig13 0010: ig2 0110: ig6 1010: ig10 1110: ig14 0011: ig3 0111: ig7 1011: ig11 1111: ig15 for unrestricted y and z inputs [7:0] sources, see table 5-13 and table 5-14 on page 113. 27:24 map_[y/z]_14 map unrestricted [y/z] input 14. see bits [31:28] for decode. 23:20 map_[y/z]_13 map unrestricted [y/z] input 13. see bits [31:28] for decode. 19:16 map_[y/z]_12 map unrestricted [y/z] input 12. see bits [31:28] for decode. 15:12 map_[y/z]_11 map unrestricted [y/z] input 11. see bits [31:28] for decode. 11:8 map_[y/z]_10 map unrestricted [y/z] input 10. see bits [31:28] for decode. 7:4 map_[y/z]_9 map unrestricted [y/z] input 9. see bits [31:28] for decode. 3:0 map_[y/z]_8 map unrestricted [y/z] input 8. see bits [31:28] for decode. 352 amd geode? cs5535 companion device data book programmable interrupt controller register descriptions 31506b 6.9.1.3 irq mapper primar y mask (pic_irqm_prim) 6.9.1.4 irq mapper lpc mask (pic_irqm_lpc) msr address 51400024h pic i/o offset 10h ty p e r / w reset value 0000ffffh pic_irqm_prim register map 313029282726252423222120191817161514131211109876543210 rsvd prim15_msk prim14_msk prim13_msk prim12_msk prim11_msk prim10_msk prim9_msk prim8_msk prim7_msk prim6_msk prim5_msk prim4_msk prim3_msk rsvd prim1_msk prim0_msk pic_irqm_prim bit descriptions bit name description 31:16 rsvd reserved. set to 0. 15:0 prim[15:0]_msk primary inputs [15:0] mask. bits [15:0] correspond to prim ary inputs [15:0], bit 2 is reserved (i.e., no irq2). 0: mask the interrupt source. 1: do not mask the interrupt source. for primary inputs [15:0] sources, see table 5-12 on page 112. msr address 51400025h pic i/o offset 14h ty p e r / w reset value 00000000h pic_irqm_lpc register map 313029282726252423222120191817161514131211109876543210 rsvd lpc15_en lpc14_en lpc13_en lpc12_en lpc11_en lpc10_en lpc9_en lpc8_en lpc7_en lpc6_en lpc5_en lpc4_en lpc3_en rsvd lpc1_en lpc0_en pic_irqm_lpc bit descriptions bit name description 31:16 rsvd reserved. set to 0. 15:0 lpc[15:0]_en lpc inputs [15:0] enable. bits [15:0] correspond to lpc inputs [15:0], bit 2 is don?t care (i.e., no irq2). 0: disable interrupt source. 1: enable interrupt source. for lpc inputs [15:0] sources, see table 5-12 on page 112. amd geode? cs5535 companion device data book 353 programmable interrupt controller register descriptions 31506b 6.9.1.5 irq mapper extended interrupt request status low (pic_xirr_sts_low) msr address 51400026h pic i/o offset 18h ty p e r o reset value xxxxxxxxh pic_xirr_sts_low register map 313029282726252423222120191817161514131211109876543210 ig7_sts ig6_sts ig5_sts ig4_sts ig3_sts ig2_ sts rsvd ig1_sts rsvd ig0_ sts pic_xirr_sts_low bit descriptions bit name description 31:28 ig7_sts interrupt group 7 status. reports the status of the four interrupts in this group. bit 28: primary input 7. bit 29: lpc input 7. bit 30: unrestricted y input 7. bit 31: unrestricted source z input 7. 27:24 ig6_sts interrupt group 6 status. reports the status of the four interrupts in this group. bit 24: primary input 6. bit 25: lpc input 6. bit 26: unrestricted y input 6. bit 27: unrestricted z input 6. 23:20 ig5_sts interrupt group 5 status. reports the status of the four interrupts in this group. bit 20: primary input 5. bit 21: lpc input 5. bit 22: unrestricted y input 5. bit 23: unrestricted z input 5. 19:16 ig4_sts interrupt group 4 status. reports the status of the four interrupts in this group. bit 16: primary input 4. bit 17: lpc input 4. bit 18: unrestricted y input 4. bit 19: unrestricted z input 4. 15:12 ig3_sts interrupt group 3 status. reports the status of the four interrupts in this group. bit 12: primary input 3. bit 13: lpc input 3. bit 14: unrestricted y input 3. bit 15: unrestricted z input 3. 11:10 ig2_sts interrupt group 2 status. reports the status of the tw o interrupts in this group. bit10: unrestricted y input 2. bit 11: unrestricted z input 2. 9:8 rsvd reserved. always reads 0; no connection to any interrupts. 7:4 ig1_sts interrupt group 1 status. reports the status of the four interrupts in this group. bit 4: primary input 1. bit 5: lpc input 1. bit 6: unrestricted y input 1. bit 7: unrestricted z input 1. 3:2 rsvd reserved. always reads 0; no connection to any interrupts. 354 amd geode? cs5535 companion device data book programmable interrupt controller register descriptions 31506b 6.9.1.6 irq mapper extended interrupt re quest status high (pic_xirr_sts_high) 1:0 ig0_sts interrupt group 0 status. reports the status of the tw o interrupts in this group. bit 0: primary input 0. bit 1: lpc input 0. msr address 51400027h pic i/o offset 1ch ty p e r o reset value xxxxxxxxh pic_xirr_sts_high register map 313029282726252423222120191817161514131211109876543210 ig15_sts ig14_sts ig13_sts ig12_sts ig11_sts ig10_sts ig9_sts ig8_sts pic_xirr_sts_high bit descriptions bit name description 31:28 ig15_sts group 15 interrupt status. reports the status of the four interrupts in this group. bit 28: primary input 15. bit 29: lpc input 15. bit 30: unrestricted y input 15. bit 31: unrestricted z input 15. 27:24 ig14_sts group 14 interrupt status. reports the status of the four interrupts in this group. bit 24: primary input 14. bit 25: lpc input 14. bit 26: unrestricted y input 14. bit 27: unrestricted z input 14. 23:20 ig13_sts group 13 interrupt status. reports the status of the four interrupts in this group. bit 20: primary input 13. bit 21: lpc input 13. bit 22: unrestricted y input 13. bit 23: unrestricted z input 13. 19:16 ig12_sts group 12 interrupt status. reports the status of the four interrupts in this group. bit 16: primary input 12. bit 17: lpc input 12. bit 18: unrestricted y input 12. bit 19: unrestricted z input 12. 15:12 ig11_sts group 11 interrupt status. reports the status of the four interrupts in this group. bit 12: primary input 11. bit 13: lpc input 11. bit 14: unrestricted y input 11. bit 15: unrestricted z input 11. 11:8 ig10_sts group 10 interrupt status. reports the status of the four interrupts in this group. bit 08: primary input 10. bit 09: lpc input 10. bit 10: unrestricted y input 10. bit 11: unrestricted z input 10. pic_xirr_sts_low bit descriptions (continued) bit name description amd geode? cs5535 companion device data book 355 programmable interrupt controller register descriptions 31506b 6.9.1.7 pic shadow (pic_shdw) 7:4 ig9_sts group 9 interrupt status. reports the status of the four interrupts in this group. bit 4: primary input 9. bit 5: lpc input 9. bit 6: unrestricted y input 9. bit 7: unrestricted z input 9. 3:0 ig8_sts group 8 interrupt status. reports the status of the four interrupts in this group. bit 0: primary input 8. bit 1: lpc input 8. bit 2: unrestricted y input 8. bit 3: unrestricted z input8. msr address 51400034h ty p e r o reset value xxh pic_shdw register map 76543210 pic_shdw pic_shdw bit descriptions bit name description 7:0 pit_shdw (ro) pic shadow (read only). this 8-bit port sequences through the following list of shad- owed programmable interrupt controller register s. at power on, a pointer starts at the first register in the list and consecutively re ads incrementally through it. a write to this register resets the read sequence to the first register. each shadow register in the sequence contains the last data written to that location. the read sequence for this register is: 1. pic1 icw1. 2. pic1 icw2. 3. pic1 icw3. 4. pic1 icw4 - bits [7:5] of icw4 are always 0. 5. pic1 ocw2 - bits [6:3] of ocw2 are always 0 (note 1). 6. pic1 ocw3 - bits [7, 4] are 0 and bit [6, 3] are 1. 7. pic2 icw1. 8. pic2 icw2. 9. pic2 icw3. 10. pic2 icw4 - bits [7:5] of icw4 are always 0. 11. pic2 ocw2 - bits [6:3] of ocw2 are always 0 (note 1). 12. pic2 ocw3 - bits [7, 4] are 0 and bit [6, 3] are 1. note 1. to restore ocw2 to shadow register value, write the appropriate address twice. first with the shadow register val- ue, then with the shadow register value ored with c0h. pic_xirr_sts_high bit d escriptions (continued) bit name description 356 amd geode? cs5535 companion device data book programmable interrupt controller register descriptions 31506b 6.9.2 pic native registers there are two separate pic sub-blocks in the geode cs5535 companion device, connected in a cascaded arrangement, as is required for a pc-compatible system. each pic has its own native register set, apart from the msr registers (unique to the geode cs5535 companion device architecture), which are common. the master pic occupies i/o addresses 020h and 021h, and manages irq signals irq0 through irq7, with irq2 claimed as the cascade input for the slave pic. the slave pic occupies i/o addresses 0a0h and 0a1h, and man- ages irq signals irq8 through irq15. in this description, the two addresses of a pic ar e called the even address (a[0] = 0) and the odd address (a[0] = 1). the pic register set addressing is often confusing due to some very severe constraints the pic had in its earliest his- tory. when it was a separate chip, the package pinout lim- ited it to only one address line. to make up for this, two bits of the data written (bits 3 and 4) sometimes serve an addressing function to select registers. the chip functions in two f undamental modes with respect to register accesses: it is either in operation mode (normal operation), or it is in initialization mode (being initialized). different sets of registers are selected in each mode. operation mode when the pic is in operation mode, a set of registers may be accessed, called the operation command words (ocws). ocw1: the interrupt mask register (imr), may be read or written at any time except during initialization. ocw2: a write-only register that is given commands from software. for example, the end of interrupt command is written here at the end of interrupt service to terminate the blocking of interrupts on the basis of priority. ocw3: a write-only register that is given a different set of commands from software. for example, it is through this register that software can request images of two internal registers: ? irr: interrupt request register -- shows those irqs with pending interrupts that have not yet received an interrupt acknowledge from the cpu. ? isr: in-service register -- shows those irqs that have received interrupt acknowledge, but whose interrupt service routines have not yet completed. initialization mode the pic is placed into its initialization mode by a write of a reserved value (xxx1xxxx) to the even-numbered address (master 0020h / slave 00a0h). this is the first of a sequence of writes to a special set of initialization control word registers (icw1, icw2, icw3 and icw4) that hold permanent settings and are normally touched only while the operating syst em is booting. 6.9.2.1 register addressing scheme other write and read accesses do not depend directly on this form of addressing. writing to the odd address operation mode: writes to the interrupt mask register: ocw1. initialization mode: three successive writes to this address must immediately follow the write to icw1 (above), before any other accesses are performed to the pic. these writes load icw2, icw3 and icw4 in succession, after which the pic automatically transitions to operation mode. reading from the even address (operation mode only: the initialization mode does not involve reading.) reads from this address are generally for special or diag- nostic purposes. the read mu st be preceded by writing a command to ocw3 (above), to select an internal register to read. this will be the irr or isr. (another register, ?poll?, histor ically part of the pic archi- tecture, is not provided in the geode cs5535 companion device.) following that command, the read here will return the requested value. reading from the odd address (operation mode only: the initialization mode does not involve reading.) always reads from the interrupt mask register: ocw1. associated external registers two directly addressable read/write registers, outside the addresses of the pics themselves, have been added to allow individual control of which irqs are level sensitive vs. edge sensitive. int_sel1, i/o address 04d0h, controls irq1, irq3-7 int_sel2, i/o address 04d1h, controls irq8-15 writing to the even address data bit access performed 43 0 0 in operation mode, writes to ocw2, assert- ing a routine command. 0 1 in operation mode, writes to ocw3, assert- ing a special or diagnostic command. commands written to ocw3 may request to examine an internal pic register; if so, this (even) address must be immediately read to retrieve the requested value and terminate the command. see "reading from the even address" below. 1 0 or 1 triggers initialization mode and writes to icw1. bit 3 is used as a data bit in this case. amd geode? cs5535 companion device data book 357 programmable interrupt controller register descriptions 31506b 6.9.2.2 initialization co mmand word 1 (pic_icw1) 6.9.2.3 initialization comma nd word 2 (pic_icw2) i/o port master: 020h slave: 0a0h ty p e w o reset value 00h pic_icw1 register map 76543210 rsvd 1 trigger rsvd rsvd rsvd pic_icw1 bit descriptions bit name description 7:5 rsvd reserved. write to 0. 41 write to 1. write to 1 to write icw1 and enter initialization mode. (see section 6.9.2 "pic native registers" on page 356.) 3trigger trigger mode . 0: edge. 1: level. 2 rsvd reserved. write to 0. 1 rsvd reserved. write to 0. 0 rsvd reserved. write to 1. i/o port master: 021h slave: 0a1h ty p e w o reset value 00h pic_icw2 register map 76543210 a[7:3] rsvd pic_icw2 bit descriptions bit name description 7:3 a[7:3] address lines [7:3]. for base vector of interrupt controller. 2:0 rsvd reserved. write to 0. 358 amd geode? cs5535 companion device data book programmable interrupt controller register descriptions 31506b 6.9.2.4 initialization comma nd word 3 (pic_icw3) 6.9.2.5 initialization comma nd word 4 (pic_icw4) i/o port master: 021h slave: 0a1h ty p e w o reset value 00h pic_icw3 register map 76543210 master = cascade_irq; slave = slave_id pic_icw3 bit descriptions bit name description master 7:0 cascade_irq cascade irq. must be written to 04h. slave 7:0 slave_id slave id. must be written to 02h. i/o port master: 021h slave: 0a1h ty p e w o reset value 00h pic_icw4 register map 76543210 rsvd spec_nst rsvd auto_eoi rsvd pic_icw4 bit descriptions bit name description 7:5 rsvd reserved. write to 0. 4 spec_nst reserved (special fully nested mode is not supported). write to 0. 3:2 rsvd reserved. write to 0. 1auto_eoi auto end of interrupt. this feature is present, but is not recommended for use. when set to 1, this bit causes the pic to automa tically issue an end of interrupt internally, immediately after each interrupt acknowledge from the cpu. when cleared to 0 (the default), it requires software action (writing to the ocw2 register) to signal end of inter- rupt. 0: normal eoi. 1: auto eoi (not recommended). 0 rsvd reserved. write to 1 (8086/8088 mode). amd geode? cs5535 companion device data book 359 programmable interrupt controller register descriptions 31506b 6.9.2.6 operation command word 1 / interrupt mask (pic_ocw1/imr) 6.9.2.7 operation command word 2 (pic_ocw2) i/o port master: 021h slave: 0a1h ty p e r / w reset value 00h pic_ocw1/imr register map 76543210 irq7_15m irq6_14m irq5_13m irq4_12m irq3_11m irq2_10m irq1_9m irq0_8m pic_ocw1/imr bit descriptions bit name description 7 irq7_15m irq7 / irq15 mask. 0: not masked; 1: masked. 6 irq6_14m irq6 / irq14 mask. 0: not masked; 1: masked. 5 irq5_13m irq5 / irq13 mask. 0: not masked; 1: masked. 4 irq4_12m irq4 / irq12 mask. 0: not masked; 1: masked. 3 irq3_11m irq3 / irq11 mask. 0: not masked; 1: masked. 2 irq2_10m irq2 / irq10 mask. 0: not masked; 1: masked. 1 irq1_9m irq1 / irq9 mask. 0: not masked; 1: masked. 0 irq0_8m irq0 / irq8 mask. 0: not masked; 1: masked. i/o port master: 020h slave: 0a0h ty p e w o reset value 00h pic_ocw2 register map 76543210 rot_eoi 00 irq pic_ocw2 bit descriptions bit name description 7:5 rot_eoi rotate/eoi codes. 000: clear rotate in auto eoi mode. 100: set rotate in auto eoi mode. 001: non-specific eoi. 101: rotate on non-specific eoi command. 010: no operation. 110: set priority command (bits [2:0] must be valid). 011: specific eoi (bits [2:0] must be valid. 111: rotate on specific eoi command (bits [2:0] must be valid) 4:3 00 write to 0. write to 00 to write ocw2 (rather than ocw3 or icw1). (see section 6.9.2 "pic native registers" on page 356.) 2:0 irq irq number (000-111). 360 amd geode? cs5535 companion device data book programmable interrupt controller register descriptions 31506b 6.9.2.8 operation command word 3 (pic_ocw3) i/o port master: 020h slave: 0a0h ty p e w o reset value 00h pic_ocw3 register map 76543210 rsvd sp_mask 01 rsvd reg_read pic_ocw3 bit descriptions bit name description 7 rsvd reserved. write to 0. 6:5 sp_mask special mask mode. the internal smm bit can be set or cleared using this 2-bit field. 0x: no change to the internal smm bit. 10: clears the internal smm bit (i.e., value of smm bit = 0). (default after initialization.) 11: sets the internal smm bit (i.e., value of smm bit = 1). while the internal smm bit is 1, interrupt blocking by priority is disabled, and only the interrupt mask register (ocw1) is used to block interrupt requests to the cpu. while the internal smm bit is 0 (the default), an un masked irq must also be of higher priority than the irq of the currently running interrupt service routine. regardless of the setting of this bit, the irq priority is still used to arbitrate among multiple allowed irq requests at the time of an interrupt acknowledge access from the cpu. 4:3 01 write to 01. write to 01 to write ocw3 (rather than ocw2 or icw1). (see section 6.9.2 "pic native registers" on page 356.) 2 rsvd reserved. write to 0. (poll command at this address is not supported.) 1:0 reg_read register read mode. 00: no operation. 10: read interrupt request register on next read of i/o port 020h (master) or 0a0h (slave). 01: no operation. 11: read interrupt service register on next read of i/o port 020h (master) or 0a0h (slave). amd geode? cs5535 companion device data book 361 programmable interrupt controller register descriptions 31506b 6.9.2.9 interrupt request register (pic_irr) this register is accessible only after t he appropriate command is written to ocw3. 6.9.2.10 in-service re gister (pic_isr) this register is accessible only after t he appropriate command is written to ocw3. i/o port master: 020h slave: 0a0h ty p e r o reset value 00h pic_irr register map 76543210 irq7_15sts irq6_14sts irq5_13sts irq4_12s ts irq3_11sts irq2_10sts irq1_9sts irq0_8sts pic_irr bit descriptions bit name description 7 irq7_15sts irq7 / irq15 status (pending). 0: yes; 1: no. 6 irq6_14sts irq6 / irq14 status (pending). 0: yes; 1: no. 5 irq5_13sts irq5 / irq13 status (pending). 0: yes; 1: no. 4 irq4_12sts irq4 / irq12 status (pending). 0: yes; 1: no. 3 irq3_11sts irq3 / irq11 status (pending). 0: yes; 1: no. 2 irq2_10sts irq2 / irq10 status (pending). 0: yes; 1: no. 1 irq1_9sts irq1 / irq9 status (pending). 0: yes; 1: no. 0 irq0_8sts irq0 / irq8 status (pending). 0: yes; 1: no. i/o port master: 020h slave: 0a0h ty p e r o reset value 00h pic_isr register map 76543210 irq7_15is irq6_14is irq5_13is irq4_12is irq3_11is irq2_10is irq1_9is irq0_8is pic_isr bit descriptions bit name description 7 irq7_15is irq7 / irq15 in-service. 0: no; 1: yes. 6 irq6_14is irq6 / irq14 in-service. 0: no; 1: yes. 5 irq5_13is irq5 / irq13 in-service. 0: no; 1: yes. 4 irq4_12is irq4 / irq12 in-service. 0: no; 1: yes. 3 irq3_11is irq3 / irq11 in-service. 0: no; 1: yes. 2 irq2_10is irq2 / irq10 in-service. 0: no; 1: yes. 1 irq1_9is irq1 / irq9 in-service. 0: no; 1: yes. 0 irq0_8is irq0 / irq8 in-service. 0: no; 1: yes. 362 amd geode? cs5535 companion device data book programmable interrupt controller register descriptions 31506b 6.9.2.11 interrupt edge/level select 1 (pic_int_sel1) i/o port 4d0h ty p e r / w reset value 00h pic_int_sel1 register map 76543210 irq7_sel irq6_sel irq5_sel irq4_sel irq3_sel rsvd irq1_sel rsvd pic_int_sel1 bit descriptions bit name description 7 irq7_sel irq7 edge or level select. selects pic irq7 sens itivity configuration. 0: edge; 1: level. (note 1) note 1. if icw1 bit 3 in the pic is set as level, it overrides th e settings of this bit. this bit is provided to configure a pci interrupt mapped to irq[x] on the pic as level-sensitive (shared). 6 irq6_sel irq6 edge or level select. selects pic irq6 sens itivity configuration. 0: edge; 1: level. (note 1) 5 irq5_sel irq5 edge or level select. selects pic irq5 sens itivity configuration. 0: edge; 1: level. (note 1) 4 irq4_sel irq4 edge or level select. selects pic irq4 sens itivity configuration. 0: edge; 1: level. (note 1) 3 irq3_sel irq3 edge or level select. selects pic irq7 sens itivity configuration. 0: edge; 1: level. (note 1) 2 rsvd reserved. write to 0. 1 irq1_sel irq1 edge or level select. selects pic irq1 sens itivity configuration. 0: edge; 1: level. (note 1) 0 rsvd reserved. write to 0. amd geode? cs5535 companion device data book 363 programmable interrupt controller register descriptions 31506b 6.9.2.12 interrupt edge/level select 2 (pic_int_sel2) i/o port 4d1h ty p e r / w reset value 00h pic_int_sel2 register map 76543210 irq7_sel irq6_sel irq5_sel irq4_sel irq3_sel rsvd irq1_sel rsvd pic_int_sel2 bit descriptions bit name description 7 irq15_sel irq15 edge or level select. selects pic irq15 sens itivity configuration. 0: edge; 1: level. (note 1) note 1. if icw1 bit 3 in the pic is set as level, it overrides the settings of this bit. this bit is provided to configure a pci interrupt mapped to irq[x] on the pic as level-sensitive (shared). 6 irq14_sel irq14 edge or level select. selects pic irq14 sens itivity configuration. 0: edge; 1: level. (note 1) 5 rsvd reserved. write to 0. 4 irq12_sel irq12 edge or level select. selects pic irq12 sens itivity configuration. 0: edge; 1: level. (note 1) 3 irq11_sel irq11 edge or level select. selects pic irq11 sens itivity configuration. 0: edge; 1: level. (note 1) 2 irq10_sel irq10 edge or level select. selects pic irq10 sens itivity configuration. 0: edge; 1: level. (note 1) 1 irq9_sel irq9 edge or level select. selects pic irq9 sens itivity configuration. 0: edge; 1: level. (note 1) 0 rsvd reserved. write to 0. 364 amd geode? cs5535 companion device data book keyboard emulation logic register descriptions 31506b 6.10 keyboard emulation log ic register descriptions the registers for the keyboard emulation logic (kel) are divided into three sets: standard geodelink device (gld) msrs (shared with divil, see secti on 6.6.1 on page 317.) kel specific msrs kel native registers the msrs are accessed via the rdmsr and wrmsr pro- cessor instructions. the msr address is derived from the perspective of the cpu core. see section 4.2 "msr addressing" on page 59 for more details. all msrs are 64 bits, however, the kel specific msrs are called out as 32 bits. the kel treats writes to the upper 32 bits (i.e., bits [63:32]) of t he 64-bit msrs as don?t cares and always returns 0 on these bits. the kel specific msrs are summarized in table 6-24. four native registers are used to provide the keyboard emulation support, summarized in table 6-25: kel hce control register: used to enable and control the emulation hardwar e and report various status information. kel hce input register: emulation side of the legacy 8048 controller input buffer register. writes to i/o port 060h and 064h are read here. kel hce output register: emulation side of the legacy 8048 controller output buffer register where keyboard and mouse data is to be written by software. reads from i/o port 060h are setup here. kel hce status register: emulation side of the legacy 8048 controller status register. reads from i/o port 60h are setup here. each of the native register s is located on a 32-bit bound- ary. the offset of these registers is relative to the base address. (see section 6.6.2.2 "local bar - kel from usb host controller 1 (divil_lbar_kel1)" on page 326 and section 6.6.2.3 "local bar - kel from usb host control- ler 2 (divil_lbar_kel2)" on page 326.) any writes to locations outside these offsets are a ?don?t care?. any reads to locations outside these offsets return zero. three of the operationa l registers (hce_status, hce_input, hce_output), summarized in table 6-25, are accessible at i/o port 060h and 064h when emulation is enabled. port a is at i/o port 092h. reads and writes to the registers using i/o addresses have side effects as outlined in table 6-26. table 6-24. kel specific msrs summary msr address type register name reset value reference 5140001fh r/w keyboard emulation logic control register (kelx_ctl) 00000010h page 365 table 6-25. kel native registers summary kel memory offset type width (bits) register name reset value reference 100h r/w 32 kel hce control register (kel_hce_ctrl) 00000000h page 366 104h r/w 32 kel hce input (kel_hce_in) 000000xxh page 367 108h r/w 32 kel hce output (kel_hce_out) 000000xxh page 367 10ch r/w 32 kel hce status (kel_hce_sts) 00000000h page 368 092h r/w 8 port a (kel_porta) 00h page 369 table 6-26. kel legacy registers emulated summary i/o port i/o cycle register contents accessed/modified side effects in emulation mode 060h read hce_output read from port 060h clears outputfull in hce_status to 0. 060h write hce_input write to port 060h sets inputfull to 1 and cmddata to 0 in hce_status. 064h read hce_status read from port 064h returns current value of hce_status with no side effects. 064h write hce_input write to port 064h will set inputfull to 0 and cmddata in hce_status to 1. amd geode? cs5535 companion device data book 365 keyboard emulation logic register descriptions 31506b 6.10.1 kel specific msrs 6.10.1.1 keyboard emulat ion logic control register (kelx_ctl) port a operation is not effected by snoop or emulationenable settings in kelx_ctl. bits [31:5] are reserved. writes are ?don?t care? and reads always return zero. msr address 5140001fh ty p e r / w reset value 00000010h kelx_ctl register map 313029282726252423222120191817161514131211109876543210 rsvd prta_en sofevent eer snoop kelx_ctl bit descriptions bit name description 31:5 rsvd reserved. writes have no effect; reads return 0. 4 prta_en port a enable. defaults high. if high, port a is enabled and accesses to i/o port 092h are processed by the geode cs5535 companion device. if low, accesses to i/o port 092h are passed on to the lpc bus (where port a may exist inside a superi/o). 3:2 sofevent start-of-frame (sof) event (sofevent) selection. 00: test mode (no delays). 01: usb1 (default). 10: usb2. 11: 1 ms from pit. 1 eer emulation event (ee) routing. 0: emulation interrupt and asmi. 1: asmi only. the eer bit controls keyboard emulation interrupt generation associated with ees: character pending - clear ee by setting the outputfull bit in the hce_status register or clearing the characterpending bit in hce_control. input full - clear ee by clearing the inputfull bit in hce_status. external irq - clear ee by clearing irq1active or irq12active as appropriate in hce_control. 0snoop snoop. only applies when emulationenable in hce_control is low. when high, indi- cates a20 and init keyboard sequences are to be detected on i/o port 060h/064h transactions to the lpc keyboard. kel must generate asmi upon detection of a20 and init even though emulationenable in hce_control is low. emulation enable snoop 0 1 porta_a20_asmi or kel_init_asm i is generated when sequence is detected. status of asmi flag and enable bits are in divil msr 51400002h. 1 x porta_a20_asmi or kel_init_asm i is generated when sequence is detected. kel_asmi is generated on inputfull, external iq, or character pending. status of asmi flag and enable bits are in divil msr 51400002h for the a20 keyboard sequence, both kel_asmi and porta_a20_asmi are signaled. 00off. 366 amd geode? cs5535 companion device data book keyboard emulation logic register descriptions 31506b 6.10.2 kel native registers 6.10.2.1 kel hce control re gister (kel_hce_ctrl) kel memory offset 100h ty p e r / w reset value 00000000h kel_hce_ctrl register map 313029282726252423222120191817161514131211109876543210 rsvd a20state irq12active irq1active a20sequence externalirqen irqen characterpending emulationinterrupt emulationenable kel_hce_ctrl bit descriptions bit name description 31:9 rsvd reserved. writes have no effect; reads return 0. 8 a20state a20 state. indicates current state of a20 on the lpc keyboard controller. used to com- pare against value written to i/o port 060h when a20sequence is active. a20state is set and cleared only by software. 7irq12active irq12 active. indicates that a positive transition on irq12 from the lpc keyboard controller has occurred. software may write 1 to this bit to clear (0) it. a software write of 0 to this bit has no effect. 6 irq1active irq1 active. indicates that a positive transition on irq1 from the lpc keyboard con- troller has occurred. software may write 1 to th is bit to clear (0) it. a software write of a 0 to this bit has no effect. 5 a20sequence a20 sequence. set by kel when a data value of d1h is written to i/o port 064h. cleared by kel on write to i/o port 064h of any value other than d1h. 4 externalirqen external interrupt request enable. when set to 1, irq1 and irq12 from the lpc keyboard controller causes an emulation event. the function controlled by this bit is independent of the setting of the emulationenable bit (bit 0). 3irqen interrupt request enable. when set, the kel generates irq1 or irq12 as long as the outputfull bit in hce_status is set to 1. if the auxoutputfull bit of hcestatus is 0, then irq1 is generated; if it is 1, then an irq12 is generated. 2 characterpending character pending, when set, an ee is generated when the outputfull bit of the hce_status register is cleared to 0. 1emulation interrupt (ro) emulation interrupt (read only). this bit is a static decode of the emulation enable state. returns 1 if: characterpending = 1 or inputfull = 1 or externalirqen = 1 and (irq 1active or irq12active = 1). 0 emulationenable emulation enable. when set to 1, the kel is enabled for legacy emulation. the kel decodes accesses to i/o port 060h and 064h and generates irq1 and/or irq12 when appropriate. additionally, the kel generates an asmi at appropriate times to invoke the emulation software. amd geode? cs5535 companion device data book 367 keyboard emulation logic register descriptions 31506b 6.10.2.2 kel hce input (kel_hce_in) i/o data that is written to i/o port 060h and 064h is capt ured in the hce_input register w hen emulation is enabled. this register may be read or written directly by accessing it wit h its memory address in the kel?s operational register space. when accessed directly via the kel?s operational address space, reads and writes of this register have no side effects. 6.10.2.3 kel hce output (kel_hce_out) the data placed in the hce_output register by the emulation software is returned when i/o port 060h is read and emula- tion is enabled. on a read of this location, th e outputfull bit in hce_status is cleared to 0. kel memory offset 104h ty p e r / w reset value 000000xxh kel_hce_in register map 313029282726252423222120191817161514131211109876543210 rsvd input_data kel_hce_in bit descriptions bit name description 31:8 rsvd reserved. writes have no effect; reads return 0. 7:0 input_data input data. this register holds data normally read by ssm software. the register value is normally established by a write to i/o port 060h or 064h. however, the value can also be established by a direct write. such direct writes have no side effects. kel memory offset 108h ty p e r / w reset value 000000xxh kel_hce_out register map 313029282726252423222120191817161514131211109876543210 rsvd output_data kel_hce_out bit descriptions bit name description 31:8 rsvd reserved. writes have no effect; reads return 0. 7:0 output_data output data. this register holds data normally written by ssm software. it is returned when an i/o read of i/o port 060h is performed. writes to this register have no side effects. after writing this register, ssm software normally sets outputfull in hce_status. 368 amd geode? cs5535 companion device data book keyboard emulation logic register descriptions 31506b 6.10.2.4 kel hce status (kel_hce_sts) the contents of the hce_status register are returned on an i/o read of i/o port 064h when emulation is enabled. reads and writes of i/o port 060h and writes to i/o port 064h can cause changes in this register . emulation software can directly access this register through its memory address in the kel?s operational register space. accessing this register through its memory address produces no side effects. kel memory offset 10ch ty p e r / w reset value 00000000h kel_hce_sts register map 313029282726252423222120191817161514131211109876543210 rsvd parity timeout auxoutputfull inhibitswitch cmddata flag inputfull outputfull kel_hce_sts bit descriptions bit name description 31:8 rsvd reserved. writes have no effect; reads return 0. 7parity parity. indicates parity error on keyboard/mous e data. the value of this bit is only changed by a direct write to this register. 6 timeout timeout. used to indicate a timeout. the value of this bit is only changed by a direct write to this register. 5 auxoutputfull auxiliary output full. irq12 is asserted whenever this bit is set, outputfull is set, and irqen is set. the value of this bit is not affected by any hardw are action, therefore, it can only be changed by a direct write to this register. 4 inhibitswitch inhibit switch. this bit reflects the state of the keyb oard inhibit switch and is set if the keyboard is not inhibited. 3cmddata command data. the kel clears this bit on an i/o write to i/o port 60h and sets it on an i/o write to i/o port 064h. 2flag flag. nominally used as a system flag by softwa re to indicate a warm or cold boot. 1 inputfull input full. except for the case of a a20 sequence, this bit is set on an i/o write to i/o port 060h or 064h. while this bit is set and emulation is enabled, an emulation interrupt occurs. this bit can only be cleared by a direct write of 0. 0 outputfull output full. the kel clears this bit on a read of i/o port 060h. if irqen is set and auxoutputfull is clear, then an irq1 is generated as long as this bit is set. if irqen is set and auxoutputfull is set, then an irq12 is generated as long as this bit is set. if this bit is clear and characterpending in hce_control is set, an emulation interrupt occurs. this bit can only be set by a direct write of this register. amd geode? cs5535 companion device data book 369 keyboard emulation logic register descriptions 31506b 6.10.2.5 port a (kel_porta) bit 4 of kelx_ctl (msr 5140001fh[4]) is the port a enable bit. it must be set to 1 to enable access to this register; other- wise, port a accesses are directed to the lpc bus where a port a register may exist in a superi/o device. : i/o port 092h ty p e r / w reset value 00h kel_porta register map 76543210 rsvd a20_mask sysr kel_porta bit descriptions bit name description 7:2 rsvd reserved. writes have no effect; reads return 0. 1 a20_mask a20 mask. this bit is necessary for older progra ms that require port a address bit 20 emulation. it requires asmis to be enabled in order for software to recognize the chang- ing of this bit, and subsequent proper emulation of the a20 address bit (see porta_a20_asmi_en bit in divil gl d_msr_smi, msr 51400002h[6], for asmi enabling details). anytime this bit is changed an asmi is generated. if this bit is 1 and a 0 is written, and asm i generation is enabled, then proper vsa oper- ation causes a rollover of address from a[19:0 ] = all 1s, to a[19:0] = all 0s. address bit a20 is 0. if this bit is 0 and a 1 is written, and asmi generation is enabled, then no legacy rollover occurs from address [19:0] = all 1s. the next incremental address is a20 = 1 and a[19:0] = all 0. 0 sysr legacy system reset. writing a 1 to this bit causes a system soft reset (init) that will only happen if asmis are enabled (see porta_init_asmi_en bit in divil gld_msr_smi, msr 51400002h[7], for asmi enab ling details). writing a 0 to this bit has no effect. this bit always reads as 0. 370 amd geode? cs5535 companion device data book system management bus register descriptions 31506b 6.11 system management bus register descriptions the registers for the system management bus (smb) are divided into two sets: standard geodelink device (gld) msrs (shared with divil, see section 6.6.1 on page 317.) smb native registers the msrs are accessed via the rdmsr and wrmsr pro- cessor instructions. the msr address is derived from the perspective of the cpu core. see section 4.2 "msr addressing" on page 59 for more details. the native registers (summarized in table 6-27) are accessed via base addre ss register msr_lbar_smb (msr 5140000bh) as i/o offsets. (see section 6.6.2.4 on page 327 for bit descriptions of the base address regis- ter.) the reference column in the summary table points to the page where the register maps and bit descriptions are listed. table 6-27. smb native registers summary smb i/o offset type width (bits) register name reset value reference 00h r/w 8 smb serial data (smb_sda) 00h page 371 01h r/w 8 smb status (smb_sts) 00h page 371 02h r/w 8 smb control status (smb_ctrl_sts) 10h page 373 03h r/w 8 smb control 1 (smb_ctrl1) 00h page 374 04h r/w 8 smb address (smb_addr) 00h page 375 05h r/w 8 smb control 2 (smb_ctrl2) 00h page 376 06h r/w 8 smb control 3 (smb_ctrl3) 00h page 376 07h r/w 8 smb reserved register (smbrsvd). writes are ?don't ca re? and reads return undefined value. xxh --- amd geode? cs5535 companion device data book 371 system management bus register descriptions 31506b 6.11.1 smb native registers 6.11.1.1 smb serial data (smb_sda) 6.11.1.2 smb status (smb_sts) this is a read/write regi ster with a special clear. some of its bits may be cleared by software, as described in the table below. this register maintains the current smb status. on re set, and when the smb is disabled, smbst is cleared (00h). smb i/o offset 00h ty p e r / w reset value 00h smb_sda register map 76543210 smbsda smb_sda bit descriptions bit name description 7:0 smbsda smb serial data. this shift register is used to transmit and receive data. the most sig- nificant bit is transmitted (received) first, an d the least significant bit is transmitted last. reading or writing to the smbsda register is allowed only when the sdast bit (smb i/o offset 01h[6]) is set, or for repeated star ts after setting the start bit (smb i/o off- set 03h[0]). any attempt to access the regi ster in other cases may produce unpredict- able results. smb i/o offset 01h ty p e r / w reset value 00h smb_sts register map 76543210 slvstp sdast ber negack stastr nmatch master xmit smb_sts bit d escriptions bit name description 7 slvstp (r/w1c) slave stop (read/write 1 to clear). writing 0 to slvstp is ignored. 0: writing 1 or smb disabled. 1: stop condition detected after a slave transfer in which match (smb i/o offset 02h[2]) or gcmatch (smb i/o offset 02h[3]) was set. 6 sdast (ro) smb_data status (read only). 0: reading from smbsda (smb i/o offset 00h) during a receive, or when writing to it during a transmit. when start (smb i/o offset 03h[0]) is set, reading smbsda does not clear sdast; enabling the smb to send a repeated start in master receive mode. 1: smbsda awaiting data (transmit - master or slave) or holds data that should be read (receive - master or slave). 372 amd geode? cs5535 companion device data book system management bus register descriptions 31506b 5 ber (r/w1c) bus error (read/write 1 to clear). writing 0 to ber is ignored. 0: writing 1 or smb disabled. 1: invalid start or stop condition detected during data transfer (i.e., start or stop condi- tion during the transfer of bits [8:2] and acknowledge cycle), or when an arbitration problem detected. if the smbus loses an arbitration this bit is set. 4 negack (r/w1c) neg acknowledge (read/write 1 to clear). writing 0 to negack is ignored. 0: writing 1 or smb disabled. 1: transmission not acknowledged on the ninth clock. (in this case, sdast (bit 6) is not set.) 3 stastr (r/w1c) stall after start (read/write 1 to clear). writing 0 to stastr is ignored. when stastr is set, it stalls the smbus by pulling down the smb_clk line, and suspends any further action on the bus (e.g., receive of first byte in master receive mode). 0: writing 1 or smb disabled. 1: this bit is not set in the slave mode and is only set in the master transmit mode. when set, this bit indicates that the addr ess was sent successfully and the bus is now stalled. note that this mode of op eration must be enabled with the stastre bit (smb i/o offset 03h[7]) in order for this bit to function this way. also, if enabled with inten (smb i/o offset 03h[2]), an interrupt is sent when this bit is set. this bit is cleared by writing a 1 to it; writing a 0 has no effect. 2nmatch (r/w1c) new match (read/write 1 to clear). writing 0 to nmatch is ignored. if inten (smb i/o offset 03h[2]) is set, an interrupt is sent when this bit is set. 0: software writes 1 to this bit. 1: address byte follows a start condition or a repeated start, causing a match or a global-call match. 1master (ro) master (read only). 0: arbitration loss (ber, bit 5, is set) or recognition of a stop condition. 1: bus master request succeeded and master mode active. 0 xmit (ro) transmit (read only). direction bit. 0: master/slave transmit mode not active. 1: master/slave transmit mode active. smb_sts bit descripti ons (continued) bit name description amd geode? cs5535 companion device data book 373 system management bus register descriptions 31506b 6.11.1.3 smb control status (smb_ctrl_sts) this register configures and controls the smb functional bl ock. it maintains the current smb status and controls several smb functions. on reset and when the smb is disabl ed, the non-reserved bits of smbcst are cleared. smb i/o offset 02h ty p e r / w reset value 10h smb_ctrl_sts register map 76543210 rsvd tgscl tsda gcmtch match bb busy smb_ctrl_sts bit descriptions bit name description 7:6 rsvd reserved. reads return 0; writes have no effect. 5tgscl toggle smb_clk line. enables toggling the smb_clk line during error recovery. 0: clock toggle completed. 1: when the smb_data line is low, writing 1 to this bit toggles the smb_clk line for one cycle. writing 1 to tgscl while smb_data is high is ignored. 4 tsda (ro) test smb_data line (read only). this bit reads the current value of the smb_data line. it can be used while recovering from an error condition in which the smb_data line is constantly pulled low by an out-of-sync sl ave. data written to this bit is ignored. 3 gcmtch (ro) global call match (read only). 0: start condition or repeated start and a st op condition (including illegal start or stop condition). 1: in slave mode, gcmen (smb i/o offset 03h[ 5]) is set and the address byte (the first byte transferred after a start condition) is 00h. 2 match (ro) address match (read only). 0: start condition or repeated start and a st op condition (including illegal start or stop condition). 1: saen (smb i/o offset 04h[7]) is set and the first 7 bits of the address byte (the first byte transferred after a start condition) match the 7-bit address in the smbadr (smb i/o offset 04h[6:0]). 1 bb (r/w1c) bus busy (read/write 1 to clear). 0: writing 1, smb disabled, or stop condition detected. 1: bus active (a low level on either smb_data or smb_clk), or start condition. 0 busy (ro) busy (read only). this bit indicates the smb is either in slave transmit/receive or master transmit/receive mode, or if there is an arbitration going on the bus. 0: smb disabled or smbus in idle mode 1: smb is in one of the following states: -generating a start condition. -detects a start condition. -master mode (master (smb i/o offset 01h[1]) is set). -slave mode (match (bit 2) or gcmtch (bit 3) are set). 374 amd geode? cs5535 companion device data book system management bus register descriptions 31506b 6.11.1.4 smb control 1 (smb_ctrl1) this register configures and controls the smb functional bl ock. it maintains the current smb status and controls several smb functions. on reset and when the smb is disabl ed, the non-reserved bits of smb_ctrl1 are cleared. smb i/o offset 03h ty p e r / w reset value 00h smb_ctrl1 register map 76543210 stastre nminte gcmen ack rsvd inten stop start smb_ctrl1 bit descriptions bit name description 7 stastre stall after start enable. 0: when cleared, stastr (smb i/o offset 01h[3]) can not be set. however, if stastr is set, clearing stast re will not clear stastr. 1: stall after start mechanism enabled, and smb stalls the bus after the address byte. 6nminte new match interrupt enable. 0: no interrupt issued on a new match. 1: interrupt issued on a new match only if inten (bit 2) is set. 5gcmen global call match enable. 0: smb not responding to global call. 1: global call match enabled. 4ack receive acknowledge. this bit is ignored in transmit mode. when the device acts as a receiver (slave or master), this bit holds th e transmitting instruction that is transmitted during the next acknowledge cycle. 0: cleared after acknowledge cycle. 1: negative acknowledge issued on next received byte. 3 rsvd reserved. reads return 0; writes have no effect. 2inten interrupt enable. 0: smb interrupt disabled. 1: smb interrupt enabled. an interrupt is generated in response to one of the following events: -detection of an address match (nmatch, smb i/o offset 01h[2] = 1) and nminte (bit 6) = 1. -receipt of bus error (ber, smb i/o offset 01h[5] = 1). -receipt of negative acknowledge after sending a byte (negack, smb i/o offset 01h[4] = 1). -acknowledge of each transaction (same as the hardware set of the sdast bit, smb i/o offset 01h[6]) when dma not enabled. -in master mode if stastre = 1 (smb i/o offset 03h[7]), after a successful start (stastr = 1, smb i/o offset 01h[3]). -detection of a stop condition while in slave mode (slvstp = 1, smb i/o offset 01h[7]). 1stop stop. 0: automatically cleared after stop issued. 1: setting this bit in master mode generates a stop condition to complete or abort cur- rent message transfer. amd geode? cs5535 companion device data book 375 system management bus register descriptions 31506b 6.11.1.5 smb address (smb_addr) 0start start. set this bit only when in master mode or when requesting master mode. 0: cleared after start condition sent or bus error (ber (smb i/o offset 01h[5]) = 1) detected. 1: single or repeated start condition generat ed on the smb. if the device is not the active master of the bus (master (smb i/o offset 01h[1]) = 0), setting start gen- erates a start condition when the smb becom es free (bb (smb i/o offset 02h[1]) = 0). an address transmission sequence should then be performed. if the device is the active master of the bus (master = 1), setting start and then writing to smbsda generates a start condition. if a transmission is already in progress, a repeated start condition is gen erated. this condition can be used to switch the direction of the data flow between the master and the slave, or to choose another slave device without separa ting them with a stop condition. smb i/o offset 04h ty p e r / w reset value 00h smb_addr register map 76543210 saen smbaddr smb_addr bit descriptions bit name description 7 saen slave enable. 0: smb does not check for an address match with address field. 1: address field holds a valid address and enables the match of addr to an incoming address byte. 6:0 smbaddr device address (smb own address). these bits hold the 7-bit device address. when in slave mode, the first 7 bits received af ter a start condition are compared with this field (first bit received is compared with bit 6, and the last bit with bit 0). if the address field matches the received data and saen (b it 7) is 1, a match is declared. smb_ctrl1 bit descriptions bit name description 376 amd geode? cs5535 companion device data book system management bus register descriptions 31506b 6.11.1.6 smb control 2 (smb_ctrl2) this register enables/disables the functiona l block and determines the smb clock rate. 6.11.1.7 smb control 3 (smb_ctrl3) this register enables/disables the functiona l block and determines the smb clock rate. smb i/o offset 05h ty p e r / w reset value 00h smb_ctrl2 register map 76543210 sclfrq[6:0] en smb_ctrl2 bit descriptions bit name description 7:1 sclfrq[6:0] smb_clk frequency. this field combined with sclfrq[14:7] in smb_ctrl3 defines the smb_clk period (low and high time) when the device serves as a bus master. the clock low and high times are defined as follows: t scll = t sclh = 2*sclfrq*t clk where t clk is the module input clock cycle. sclfrq can be programmed to values in the range of 0008h through 7fffh. using any other value has unpredictable results. the low and high time are generally equal unless two or more devices are driving the scl line. 0en enable. 0: smb is disabled, all registers are clear ed, and clocks are halted. in the smbcst register all bits are cleared except the tsda bit, it reflects the value of smb_data. 1: smb is enabled. smb i/o offset 06h ty p e r / w reset value 00h smb_ctrl3 register map 76543210 sclfrq[14:7] smb_ctrl3 bit descriptions bit name description 7:0 sclfrq[14:7] smb_clk frequency. this field combined with sclfrq[6:0] in smb_ctrl2 defines the smb_clk period (low and high time) when the device serves as a bus master. see smb_ctrl2 for use of this register. amd geode? cs5535 companion device data book 377 uart and ir port register descriptions 31506b 6.12 uart and ir port register descriptions the registers for the uart/ir controller are divided into three sets: standard geodelink device (gld) msrs (shared with divil, see section 6.6.1 on page 317.) uart/ir controller specific msrs uart/ir controller native registers the msrs are accessed via the rdmsr and wrmsr pro- cessor instructions. the msr address is derived from the perspective of the cpu core. see section 4.2 "msr addressing" on page 59 for more details. all msrs are 64 bits, however, the uart/ir controller specific msrs (summarized in table 6-28) are called out as 8 bits. the uart/ir controll er treats writes to the upper 56 bits (i.e., bits [63:8]) of the 64-bit msrs as don?t cares and always returns 0 on these bits. the uart/ir controller native register set consists of eight register banks, each co ntaining eight registers, to control uart operation. all registers use the same 8-byte address space to indicate i/o offsets 00h-07h. the native registers are accessed via banks 0 through 7 as i/o off- sets. see msr_leg_io (msr 51400014h) bits [22:20] and bits [18:16] for setting base address. each bank and its offsets are summarized in table 6-29. the register summary tables include reset values and page references where the bit de scriptions are provided. table 6-28. uart/ir controller specific msrs summary msr address type register name reset value reference 51400038h r/w uart1 primary dongle and modem interface (uart[1]_mod) 0xh page 380 51400039h r/w uart1 secondary dongle and status (uart[1]_dong) xxh page 381 5140003ah r/w uart1 interface configuration (uart[1]_conf) 42h page 382 5140003bh r/w uart1 reserved msr (uart[1]_rsvd_msr) - reads return 0; writes have no effect. 00h --- 5140003ch r/w uart2 primary dongle and modem interface (uart[2]_mod) 0xh page 380 5140003dh r/w uart2 secondary dongle and status (uart[2]_dong) xxh page 381 5140003eh r/w uart2 interface configuration (uart[2]_conf) 42h page 382 5140003fh r/w uart2 reserved msr (uart[2]_rsvd_msr) - reads return 0; writes have no effect. 00h --- table 6-29. uart/ir controller native registers summary i/o offset type register name reset value reference bank 0 00h ro receive data port (rxd) xxh page 384 wo transmit data port (txd) xxh page 384 01h r/w interrupt enable register (ier) 00h page 385 02h ro event identification register (eir) extended mode: 22h page 386 non-extended mode: 01h page 388 wo fifo control register (fcr) 00h page 389 03h wo link control register (lcr) 00h page 390 r/w bank select register (bsr) 00h page 392 04h r/w modem/mode control register (mcr) 00h page 393 05h ro link status register (lsr) 60h page 394 378 amd geode? cs5535 companion device data book uart and ir port register descriptions 31506b 06h ro modem status register (msr) x0h page 396 07h r/w scratchpad register (spr) 00h page 397 r/w auxiliary status and control register (ascr) 00h page 397 bank 1 00h r/w legacy baud generator divisor low byte (lbgd_l) xxh page 398 01h r/w legacy baud generator divisor high byte (lbgd_h) xxh page 398 02h --- reserved register (rsvd) --- --- 03h rw link control register (lcr) 00h page 399 r/w bank selection encoding register (bsr) 00h page 399 04h-07h --- reserved (rsvd) --- --- bank 2 00h r/w baud generator divisor low byte (bgd_l) xxh page 400 01h r/w baud generator divisor high byte (bgd_h) xxh page 400 02h r/w extended control register 1 (excr1) 00h page 400 03h r/w bank select register (bsr) 00h page 403 04h r/w extended control register 2 (excr2) 00h page 403 05h --- reserved register (rsvd) --- --- 06h ro tx_fifo current level register (txflv) 00h page 404 07h ro rx_fifo current level register (rxflv) 00h page 404 bank 3 00h ro module identification and revision id register (mrid) 0xh page 405 01h ro shadow of link control register (sh_lcr) 00h page 405 02h ro shadow of fifo control register (sh_fcr) 00h page 406 03h r/w bank select register (bsr) 00h page 406 04h-07h --- reserved register (rsvd) --- --- bank 4 00h-01h --- reserved register (rsvd) --- --- 02h r/w ir control register 1 (ircr1) 00h page 406 03h r/w bank select register (bsr) 00h page 407 04h-07h --- reserved register (rsvd) --- --- bank 5 00h-02h --- reserved register (rsvd) --- --- 03h r/w bank select register (bsr) 00h page 407 04h r/w ir control register 2 (ircr2) 02h page 407 05h-07h --- reserved register (rsvd) --- --- table 6-29. uart/ir controller native registers summary (continued) i/o offset type register name reset value reference amd geode? cs5535 companion device data book 379 uart and ir port register descriptions 31506b bank 6 00h r/w ir control register 3 (ircr3) 20h page 408 01h --- reserved register (rsvd) --- --- 02h r/w sir pulse width register (sir_pw) 00h page 409 03h r/w bank select register (bsr) 00h page 409 04h-07h --- reserved register (rsvd) --- --- bank 7 00h r/w ir receiver demodulator control register (irrxdc) 29h page 410 01h r/w ir transmitter modulator control register (irtxmc) 69h page 412 02h r/w ceir configuration r egister (rccfg) 00h page 414 03h r/w bank select register (bsr) 00h page 415 04h r/w ir interface configuratio n register 1 (ircfg1) xxh page 415 05h-06h --- reserved register (rsvd) --- --- 07h r/w ir interface configuratio n 4 register (ircfg4) 00h page 416 table 6-29. uart/ir controller native registers summary (continued) i/o offset type register name reset value reference 380 amd geode? cs5535 companion device data book uart and ir port register descriptions 31506b 6.12.1 uart/ir controller specific msrs 6.12.1.1 uart[x] primar y dongle and modem interface (uart[x]_mod) uart1 primary dongle and modem interface (uart[1]_mod) uart2 primary dongle and modem interface (uart[2]_mod) msr_uart[x]_mod is used for primary ident ification of the dongle interface and also provides the device with a virtual modem interface. to run legacy software, the modem control bits are set such that the software sees the modem always ready for data transfer. msr address 51400038h ty p e r / w reset value 0xh msr address 5140003ch ty p e r / w reset value 0xh uart[x]_mod register map 76543210 mod7 mod6 mod5 mod4 id0 id1 id2 id3 uart[x]_mod bit descriptions bit name description 7mod7 modem 7. this bit directly sets the value of the ring indicator (ri) bit of the modem status register (bank 0, i/o offset 06h[6]). 6mod6 modem 6. this bit directly sets the value of the data set ready (dsr) bit of the modem status register (bank 0, i/o offset 06h[5]). 5mod5 modem 5. this bit directly sets the value of the data carrier detect (dcd) bit of the modem status register (bank 0, i/o offset 06h[7]). 4mod4 modem 4. this bit directly sets the value of the clear to send (cts) bit of the modem status register (bank 0, i/o offset 06h[4]). 3:0 id0-id3 primary dongle control signals. this field selects the type of ir dongle allowing software to imitate the functionality of a real dongle. these bits are unused in uart mode. x000: infrared transceiver with serial interface and differential signalling. x100: reserved. 0010: irda-data transceiver is: sharp ry5hd01 or sharp ry5kd01. 1010: reserved. 0110: infrared transceiver with serial interface and single-ended signalling. 1110: infrared transceiver supports consumer ir modes only. 0001: irda-data transceiver is: hp hsdl-2300 or hp hsdl-3600 1001: irda-data transceiver is: ibm 31t1100, vishay-telefunken tfds6000 or siemens irms/t6400. 0101: reserved. 1101: irda-data transceiver is: vishay-telefunken tfds6500. x011: irda-data transceiver is: hp hsdl-11 00, hp hsdl-2100, ti tsml 1100 or sharp ry6fd11e. 0111: irda-data transceiver supports sir mode only. 1111: no dongle connected. amd geode? cs5535 companion device data book 381 uart and ir port register descriptions 31506b 6.12.1.2 uart[x] secondary dong le and status (uart[x]_dong) uart1 secondary dongle and status (uart[1]_dong) uart2 secondary dongle and status (uart[2]_dong) uart[x]_dong is used for secondary id entification of the dongle interface, a nd along with uart[x]_mod, constitutes a vdi (virtual dongle interface). the transceivers can also be configured for available mode by driving irsl[2:0]. this support is not provided in the current design, but the values of thes e signals are written in vdi uart[x]_mod in case there is a need to know what legacy software writes on irsl[2:0] bits (via ircfg1 at i/o offset 04h in bank 7). the msr is readable by the software so the status of irsl[2:0] can be known. note: nch: no change; inv: invert. msr address 51400039h ty p e r / w reset value xxh msr address 5140003dh ty p e r / w reset value xxh uart[x]_dong register map 76543210 rsvd irsl2 irsl1 irsl0 id3_sec id0_sec uart[x]_dong bit descriptions bit name description 7:5 rsvd reserved. write as 0. 4:2 irsl2-irsl0 (ro) irsl[2:0] (read only). these bits are reflections of se ttings in the transceiver identifi- cation and control (iric) bits (bank 7, i/o o ffset 04h[2:0]). software may read this field to determine the settings of the virtual ir interface (dongle). see section 6.12.10.5 "ir interface configuration register 1 (ircfg1)" on page 415 for decode. 1 id3_sec secondary dongle control signal. secondary virtual dongle configuration bit. see table 6-30. refer to section 5.12.3 "dongle interface" on page 144 for additional infor- mation. 0 id0_sec secondary dongle control signal. secondary virtual dongle configuration bit. see table 6-30. refer to section 5.12.3 "dongle interface" on page 144 for additional infor- mation. table 6-30. secondary id encoding irsl2 irsl1 id3 id0 nch inv nch: no support inv: 36 khz demodulation support (rc-5 and rc-6 protocols) reserved inv nch nch: no support inv: 38 khz demodulation support (nec protocol) nch: no support inv: 40 khz demodulation support (jvc, panasonic protocols) inv inv nch: no support inv: 56.9 khz demodulation support (rca protocol) reserved 382 amd geode? cs5535 companion device data book uart and ir port register descriptions 31506b 6.12.1.3 uart[x] interface co nfiguration (uart[x]_conf) uart1 interface configuration (uart[1]_conf) uart2 interface configuration (uart[2]_conf) uart[x]_conf derives the control signals for mode and reset control. msr address 5140003ah ty p e r / w reset value 42h msr address 5140003eh ty p e r / w reset value 42h uart[x]_conf register map 76543210 rsvd busy reset2sir en_ banks test pwdn deven msr_soft_ reset uart[x]_conf bit descriptions bit name description 7 rsvd reserved. write as 0. 6 busy (ro) busy (read only). when high, this bit indicates that the uart busy signal is active. 5 reset2sir ir transmitter and receiver reset. set to 1 to enable reset to the ir transmitter and receiver. (default = 0.) write 0 to bring it out of reset. 4 en_banks banks enable. when set to 1, enables access to upper banks (i.e., banks 2 through 7). (default = 0; that is, the uart boots in basic mode [16550 mode where access to upper banks is not needed]). 3 test test. when set to 1, the uart goes into test mode and generates a baud clock on the serial output pin uart[x]_tx (default = 0.) 2pwdn power-down. when set to 1, the uart clocks (24 mhz clock) are frozen, but interrupt remains enabled. (default = 0.) 1 deven device enable. set to 1 to enable the uart. resetting this bit disables uart functional- ity and masks the inte rrupt. (default = 1.) 0msr_soft_ reset msr software reset. writing a 1 resets the uart. (default = 0.) amd geode? cs5535 companion device data book 383 uart and ir port register descriptions 31506b 6.12.2 uart/ir controller native registers eight register banks, each containing eight registers, con- trol uart/ir operation. all registers use the same 8-byte address space to indicate i/o offsets 00h-07h. the active bank must be selected by the software. the register bank organization enables access to the banks, as required for activation of all module modes, while maintaining transparent compatibility with 16450 or 16550 software. this activates only the registers and specific bits used in those devices. the bank select register (bsr) selects the active bank and is common to all banks. therefore, each bank defines seven new registers. see figure 6-1. the default bank selection after the system reset is 0, plac- ing the module in uart 16550 mode. additionally, setting the baud in bank 1 (as required to initialize the 16550 uart) switches the module to non-extended uart mode. this ensures that running existing 16550 software switches the system to the 16550 configuration without software modification. table 6-31 shows the main functions of the registers in each bank. banks 0 to 3 control uart and ir modes of operation; banks 4 to 7 control and configure the ir modes only. banks 4 to 7 are reserved in uart2. figure 6-1. uart register bank architecture bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 i/o offset 07h i/o offset 06h i/o offset 05h i/o offset 04h lcr/bsr i/o offset 02h i/o offset 01h i/o offset 00h common register throughout all banks 16550 banks table 6-31. register bank summary bank uart ir mode main functions 0 x x global control and status 1 x x legacy bank 2 x x alternative baud generator divisor, extended control, and status 3 x x module revision id and shadow registers 4 x ir mode setup 5 x ir control 6 x ir physical layer configuration 7 x ceir and optical transceiver configuration 384 amd geode? cs5535 companion device data book uart and ir port register descriptions 31506b 6.12.3 bank 0 register descriptions in non-extended modes of operation, bank 0 is compatible with both the 16450 and 16550. upon reset, this functional block defaults to the 16450 mode. in extended mode, all the register s (except rxd and txd) offer additional features. the bit formats for the registers in bank 0 are summarized in ta ble 6-32. detailed descriptions of each register follow. 6.12.3.1 receive/transmit data ports receive data port (rxd) transmit data port (txd) the rxd (ro) and txd (wo) ports share the same address. rxd is accessed during cpu read cycles. it is used to receiv e incoming data when the fifos are disabled, or from the bot- tom of the rx_fifo when the fifos are enabled. txd is accessed during cpu write cycles. it is used to write data directly to the tr ansmitter when the fifos are disabled, or to the tx_fifo when the fifos are enabled. dma cycles always access the txd and rxd po rts, regardless of the selected bank. table 6-32. bank 0 register bit map i/o offsetname76543210 00h rxd rxd7 rxd6 rxd5 rxd4 rxd3 rxd2 rxd1 rxd0 00h txd txd7 txd6 txd5 txd4 txd3 txd2 txd1 txd0 01h ier (note 1) note 1. non-extended mode. rsvd ms_ie ls_ie txldl_ie rxhdl_ie ier (note 2) note 2. extended mode. rsvd txemp_ie dma_ie ms_ie ls_ie txldl_ie rxhdl_ie 02h eir (note 1) fen[1:0] rsvd rxft ipr[1:0] ipf eir (note 2) rsvd txemp_ev dma_ev ms_ev ls_ev/ txhlt_ev txldl_ev rxhdl_ie fcr rxfth[1:0] txfth[1:0] rsvd txsr rxsr fifo_en 03h lcr bkse sbrk stkp eps pen stb wls[1:0] bsr bkse bsr[6:0] 04h mcr (note 1) rsvd loop isen or dcdlp rilp rts dtr mcr (note 2) mdsl[2:0] ir_pls tx_dfr dma_en rts dtr 05h lsr er_inf txemp txrdy brk fe pe oe rxda 06h msr dcd ri dsr cts ddcd teri ddsr dcts 07h spr (note 1) scratch data ascr (note 2) cte txur rxact rxwdg rsvd s_oet rsvd rxf_tout i/o offset 00h ty p e r o reset value xxh i/o offset 00h ty p e wo reset value xxh amd geode? cs5535 companion device data book 385 uart and ir port register descriptions 31506b 6.12.3.2 interrupt enable register (ier) ier controls the enabling of various interrupts. some interrup ts are common to all operating modes of the functional block, while others are mode-specific. bits [7:4] can be set in extended mode only. they are cleared in non-extended mode. when a bit is set to 1, an interrupt is generated when th e corresponding event occurs. in non-extended mode, most events can be identified by reading the lsr and msr. the receiver hi gh-data-level event can only be identified by reading the eir register after the corresponding interrupt has been generated. in extended mode, events are identified by event flags in the eir register. the bitmap of the ier varies depending on the operating mode of the functional block. the modes can be divided into the two groups and is selected via the ext_sl bit in the excr1 register (bank 2, i/o offset 02h[0]): uart, sharp-ir, sir and ceir in extended mode (ext_sl = 1) uart, sharp-ir and sir in non-extended mode (ext_sl = 0) ier, extended mode: uart, sir, sh arp-ir and ceir (excr1.ext_sl = 1) notes (extended mode only): 1) if the interrupt signal drives an edge-sens itive interrupt controller input, it is adv isable to disable all interrupts by cle ar- ing all the ier bits upon entering the interrupt routine, and re -enable them just before exiting it. this guarantees proper interrupt triggering in the interrupt controller should one or more interrupt events occur during execution of the interrupt routine. 2) if an interrupt source must be disabled, the cpu can do so by clearing the corresponding bit of the ier register. how- ever, if an interrupt event occurs just before the correspondi ng enable bit of the ier register is cleared, a spurious interrupt may be generated. to avoid this problem, clearing of any ier bit should be done during execution of the inter- rupt service routine. if the interrupt controller is programmed for level-sensitive interrupts, clearing ier bits can be per- formed outside the interrupt service routine, but with the cpu interrupt disabled. 3) if the lsr, msr, or eir registers are to be polled, the interrupt sources (identified via self-clearing bits) should have their corresponding ier bits set to 0. this prev ents spurious pulses on the interrupt output pin. i/o offset 01h ty p e r / w reset value 00h ier extended mode register map 76543210 rsvd txemp_ie dma_ie ms_ie ls_ie/ txhlt_ie txldl_ie rxhdl_ie ier extended mode bit descriptions bit name description 7:6 rsvd reserved. write as 0. 5 txemp_ie transmitter empty interrupt enable. setting this bit to 1 enables transmitter empty interrupts (in all modes). 4dma_ie dma interrupt enable. setting this bit to 1 enables the interrupt on terminal count when the dma is enabled. 3ms_ie modem status interrupt enable. setting this bit to 1 enables the interrupts on modem status events. 2 ls_ie/txhlt_ie link status interrupt enable/tra nsmitter halted interrupt enable. setting this bit enables link status interrupts and transmitter halted interrupts in ceir. 1 txldl_ie transmitter low-data-le vel interrupt enable. setting this bit to 1 enables interrupts when the tx_fifo is below the threshold level or the transmitter holding register is empty. 0 rxhdl_ie receiver high-data-le vel interrupt enable. setting this bit to 1 enables interrupts when the rxd is full, or the rx_fifo is equa l to or above the rx_fifo threshold level, or an rx_fifo timeout occurs. 386 amd geode? cs5535 companion device data book uart and ir port register descriptions 31506b ier, non-extended mode: uart, si r or sharp-ir (excr1.ext_sl = 0) upon reset, the ier supports uart, sir and sharp-ir in non-extended modes. 6.12.3.3 event identification (eir )/fifo control registers (fcr) the event identification register (eir) is a read-only register and shares the same address as the write-only fifo control register (fcr). event identification register (eir) the eir indicates the interrupt source, and operates in two modes, non-extended mode (ext_sl of the excr1 register = 0), and extended mode (ext_sl of the excr1 register = 1) (b ank 2, i/o offset 02h[0]). in non-extended mode (default), this register functions the same as in the 16550 mode. eir, extended mode (excr1.ext_sl = 1) in extended mode, each of the previously prioritized and encoded interrupt sources is broken down into individual bits. each bit in this register acts as an inte rrupt pending flag, and is set to 1 when the corresponding event has occurred or is pending, regardless of the ier register bit setting. when this register is read, the dma event (bit 4) is cleared if an 8237 type dma is used. all other bits are cl eared when the corresponding interrupts are acknowledged, by reading the relevant register (e.g., reading the ms r register clears ms_ev). ier non-extended mode register map 76543210 rsvd ms_ie ls_ie txldl_ie rxhdl_ie ier non-extended mode bit descriptions bit name description 7:4 rsvd reserved. write as 0. 3ms_ie modem status interrupt enable. setting this bit to 1 enables the interrupts on modem status events. (eir bits [3:0] are 0000.) 2ls_ie link status interrupt enable. setting this bit to 1 enables interrupts on link status events. (eir bits [3:0] are 0110) 1 txldl_ie transmitter low data level interrupt enable. setting this bit to 1 enables interrupts on transmitter low data level events. (eir bits [3:0] are 0010.) 0 rxhdl_ie receiver high data level interrupt enable. setting this bit to 1 enables interrupts on receiver high data level, or rx_fifo timeout events. (eir bits [3:0] are 0100 or 1100.) i/o offset 02h ty p e r o reset value extended mode: 22h non-extended mode: 01h eir extended mode register map 76543210 rsvd txemp_ev dma_ev ms_ev ls_ev/txhlt_ ev txldl_ev rxhdl_ev amd geode? cs5535 companion device data book 387 uart and ir port register descriptions 31506b eir extended mode bit descriptions bit name description 7:6 rsvd reserved. read as 0. 5 txemp_ev transmitter empty event. this bit is the same as bi t 6 of the lsr (length status register). it is set to 1 when the tr ansmitter is empty. (default = 1.) 4dma_ev dma event. this bit is set to 1 when a dma termi nal count (tc) is activated. it is cleared upon read. 3 ms_ev modem status event. in uart mode: ? this bit is set to 1 when any of the 0 to 3 bits in the msr is set to 1. in any ir mode: ? the function of this bit depends on the setting of irmssl of the ircr2 register (see section 6.12.8.2 "ir c ontrol register 2 (ircr2)" on page 407). when irmssl is 0, the bit functions as a modem status interrupt event; when irmssl is set to 1, the bit is forced to 0. 2 ls_ev/txhlt_ev link status event in uart, sharp-ir and sir: ? this bit is set to 1 when a receiver error or break condition is reported. when fifos are enabled, the parity error, fr ame error and break conditions are reported only when the associated character reaches the bottom of the rx_fifo. an overrun error is reported as soon as it occurs. link status event or transmitter halted event in ceir: ? set to 1 when the receiver is overrun or the transmitter underrun. note: a high-speed cpu can service the inte rrupt generated by the last frame byte reaching the rx_fifo bottom before that byte is transferred to mem- ory by the dma controller. this can happen when the cpu interrupt latency is shorter than the rx_fif o timeout. a dma request is generated only when the rx_fifo level reaches the dma threshold or when a fifo timeout occurs, in order to minimize the performance degradation due to dma signal handshake sequences. if the dma controller must be set up before receiving each frame, the software in the interrupt routine should make sure that the last byte of the frame received has been transferred to memory before reinitializing the dma c ontroller, otherwise that byte could appear as the first byte of the next frame received. 1 txldl_ev transmitter low-data-level event. (default = 1.) fifos disabled: ? set to 1 when the transmitte r holding register is empty. fifos enabled: ? set to 1 when the tx_fifo level is below the threshold level. 0 rxhdl_ev receiver high-data-level event. fifos disabled: ? set to 1 when a character is in the receiver holding register. fifos enabled: ? set to 1 when the rx_fifo is equal to or above threshold or an rx_fifo timeout has occurred. 388 amd geode? cs5535 companion device data book uart and ir port register descriptions 31506b eir, non-extend ed mode (exc r1.ext_sl = 0) in non-extended uart mode, the functional block prioritizes interrupts into four levels. the eir indicates the highest level of interrupt that is pending. see table 6-33 for the encoding of these interrupts. eir non-extended mode register map 76543210 fen1 fen0 rsvd rxft ipr1 ipr0 ipf eir non-extended mode bit descriptions bit name description 7:6 fen[1:0] fifos enabled. 00: no fifo enabled (default). 11: fifos enabled (bit 0 of fcr = 1). 01, 10: reserved. 5:4 rsvd reserved. write to 0. 3rxft rx_fifo timeout. in the 16450 mode, this bit is al ways 0. in the 16550 mode (fifos enabled), this bit is set to 1 when an rx_fifo read timeout has occurred and the associ- ated interrupt is currently the highest priority pending interrupt. 2:1 ipr[1:0] interrupt priority. when bit 0 (ipf) is 0, these bits i ndicate the pending interrupt with the highest priority. (default = 00). see table 6-33. 0ipf interrupt pending flag. 0: interrupt pending. 1: no interrupt pending (default). table 6-33. eir non-extended mode interrupt priorities eir bits[3:0] priority level interrupt type interrupt source interrupt reset control 0001 n/a none none n/a 0110 highest link status parity error, framing error, data over- run or break event. read link status register (lsr). 0100 second receiver high data level event receiver holding register (rxd) is full, or rx_fifo level is equal to or above the threshold. reading the rxd or rx_fifo level drops below threshold. 1100 second rx_fifo timeout at least one character is in the rx_fifo, and no character has been input to or read from the rx_fifo for four character times. reading the rxd port. 0010 third transmitter low data level event transmitter holding register or tx_fifo empty. reading the event identification register (eir) if this interrupt is currently the highest priority pending interrupt, or writing into the txd port. 0000 fourth modem status any transition on cts, dsr or dcd or a high-to-low transition on ri. reading the modem status reg- ister (msr). amd geode? cs5535 companion device data book 389 uart and ir port register descriptions 31506b fifo control register (fcr) the fifo control register (fcr) is used to enable the fifos, clear the fifo s and set the interrupt threshold levels for the rx_fifo and tx_fifo. fcr can be read th rough sh_fcr in bank 3, i/o offset 02h (see section 6.12.6.3 on page 406). i/o offset 02h ty p e w o reset value 00h fcr register map 76543210 rxfth txfth rsvd txsr rxsr fifo_en fcr bit descriptions bit name description 7:6 rxfth rx_fifo interrupt threshold level. these bits select the rx _fifo interrupt threshold level. an interrupt is generated when the level of data in the rx_fifo is equal to or above the encoded threshold. rx_fifo interrupt threshold level (16-level fifo) (32-level fifo) 00: 1 (default) 1 (default) 01: 4 8 10: 8 16 11: 14 26 5:4 txfth[1:0] tx_fifo interrupt threshold level. in non-extended modes, these bits have no effect. in extended modes, these bits se lect the tx_fifo interrupt threshold level. an interrupt is generated when the level of data in the tx_fifo drops below the encoded threshold. tx_fifo interrupt threshold level (16-level fifo) (32-level fifo) 00: 1 (default) 1 (default) 01: 3 7 10: 9 17 11: 13 25 3 rsvd reserved. write to 0. 2 txsr transmitter soft reset. writing a 1 to this bit generates a transmitter soft reset that clears the tx_fifo and the transmitter logic. this bi t is automatically clear ed by the hardware. 1 rxsr receiver soft reset. writing a 1 to this bit generates a receiver soft reset that clears the rx_fifo and the receiver logic. this bit is automatically cleared by the hardware. 0fifo_en fifo_en (fifo enable). when set to 1, this bit enables both the tx_fifo and rx_fifos. resetting this bit clears both fifo s. in ceir mode, the fifos are always enabled and the setting of this bit is ignored. 390 amd geode? cs5535 companion device data book uart and ir port register descriptions 31506b 6.12.3.4 link control/ban k select registers these registers share the same address. the link control register (lcr) selects the communication fo rmat for data transfers in uart, sir and sharp-ir modes. the bank select register (bsr) is used to select the register bank to be accessed next. reading the register at this address lo cation returns the content of the bsr. the content of lcr can be read from the shadow of link control register (sh_lcr) in bank 3, i/o offset 01h (see section 6.12.6.2 on page 405). during a write operation to this register at this address location, setting of bank select enable (bkse, bit 7) determines the register to be accessed, as follows: if bit 7 is 0, both lcr and bsr are written into. if bit 7 is 1, only bsr is written into and lcr remains unc hanged. this prevents the co mmunication format from being spuriously affected when a bank othe r than bank 0 or 1 is accessed. link control register (lcr) bits 6 to 0 are only effective in uart, sharp-ir and sir modes. they are ignored in ceir mode. i/o offset 03h ty p e w o reset value 00h lcr register map 76543210 bkse sbrk stkp eps pen stb wls[1:0] lcr bit descriptions bit name description 7 bkse bank select enable. 0: register functions as the link control register (lcr). 1: register functions as the bank select register (bsr). 6 sbrk set break. enables or disables a break. during the break, the transmitter can be used as a character timer to accurately establish the brea k duration. this bit acts only on the trans- mitter front end and has no effect on the rest of the transmitter logic. when set to 1, the fol- lowing occurs: ? if uart mode is selected, the uart[x]_tx pin is forced to a logic 0 state. ? if sir mode is selected, pulses are issu ed continuously on the uart[x]_ir_tx pin. ? if sharp-ir mode is selected and internal modulation is enabled, pulses are issued continuously on the uart[x]_ir_tx pin. ? if sharp-ir mode is selected and internal modulation is disabled, the uart[x]_ir_tx pin is forced to a logic 1 state. to avoid transmission of erroneous characters as a result of the break, use the following procedure: ? wait for the transmitter to be empty (txemp = 1). ? set sbrk to 1. ? wait for the transmitter to be empty, and clear sbrk to restore normal transmission. 5stkp stick parity. when parity is enabled (pen is 1), this bit and eps (bit 4) control the parity bit (see table 6-34). this bit has no effect when parity is not enabled. 4 eps even parity select. when parity is enabled (pen is 1), this bit and stkp (bit 5) control the parity bit (see table 6-34). this bit has no effect when parity is not enabled. 3 pen parity enable. this bit enables the parity bit. the parity enable bit is used to produce an even or odd number of 1s when the data bits and parity bit are summed, as an error detec- tion device. 0: no parity bit is used (default). 1: a parity bit is generated by the transmitter and checked by the receiver. amd geode? cs5535 companion device data book 391 uart and ir port register descriptions 31506b 2stb stop bits. this bit specifies the number of stop bits transmitted with each serial character. 0: one stop is bit generated (default). 1: if the data length is set to 5 bits via bits [1:0] (wls[1:0]), 1.5 stop bits are generated. for 6-, 7- or 8-bit word lengths, 2 stop bits are tr ansmitted. the receiver checks for 1 stop bit only, regardless of the number of stop bits selected. 1:0 wls[1:0] character length select [1:0]. these bits specify the number of data bits in each trans- mitted or received serial character. 00: 5 (default) 01: 6 10: 7 11: 8 table 6-34. bit settings for parity control pen eps stkp selected parity bit 0x x none 100 odd 110 even 1 0 1 logic 1 1 1 1 logic 0 lcr bit descriptions (continued) bit name description 392 amd geode? cs5535 companion device data book uart and ir port register descriptions 31506b bank select register (bsr) bsr selects the next register bank to be accessed. for details on how to a ccess this register, see the description of bkse (bit 7) of lcr (section 6.12.3.4 on page 390). the r egister map and bit descriptions are applicable for all banks. i/o offset 03h ty p e r / w reset value 00h bsr register map 76543210 bkse bsr[6:0] bsr bit descriptions bit name description 7 bkse bank select enable 0: bank 0 selected. 1: bits 6 to 0 specify the selected bank (see table 6-35). 6:0 bsr[6:0] bank select [6:0]. when bkse (bit 7) is set to 1, these bits select the bank (see table 6- 35). table 6-35. bank select encoding bsr bits bank selected 76543210 0xxxxxxx 0 10xxxxxx 1 11xxxx1x 1 11xxxxx1 1 11100000 2 11100100 3 11101000 4 11101100 5 11110000 6 11110100 7 11111x00 reserved 110xxx00 reserved amd geode? cs5535 companion device data book 393 uart and ir port register descriptions 31506b 6.12.3.5 modem/mode control register (mcr) mcr controls the virtual interface with the modem or data communications set in loopback mode, and the device opera- tional mode when the device is in the extended mode. this register function differs for extended and non-extended modes. modem control pins are not available and are replaced with th e virtual interface (except rts and dtr signals) controlled by software only through msr_uart[x]_mod (see section 6.12.1.1 on page 380). mcr, extended mode (excr1.ext_sl = 1) in extended mode, this register is used to select the operati on mode (irda, sharp, etc.) of the device and enable the dma interface. in these modes, the interrupt output signal is always enabled, and loopback can be enabled by setting bit 4 of excr1. bits 2 to 7 should always be initialized when t he operation mode is changed from non-extended to extended. i/o offset 04h ty p e r / w reset value 00h mcr extended mode register map 76543210 mdsl[2:0] rsvd tx_dfr dma_en rts dtr mcr extended mode bit descriptions bit name description 7:5 mdsl[2:0] mode select [2:0]. these bits select the operation mode of the functional block when in extended mode. when the mode is changed, the tx_fifo and rx_f ifos are flushed, link status and modem status interrupts are cl eared, and all of the bits in the auxiliary status and control register are cleared. 000: uart (default) 001: reserved 010: sharp-ir 011: sir 100: reserved 101: reserved 110: ceir 111: reserved 4 rsvd reserved. write as 0. 3tx_dfr transmit deferral. for a detailed description of the trans mit deferral see section 5.12.1.6 "transmit deferral" on page 142. this bit is effective only if the tx_fifo is enabled (fcr bit 0 = 1). 0: no transmit deferral enabled. (default.) 1: transmit deferral enabled. 2dma_en dma enable. when set to1, dma mode of operation is enabled. when dma is selected, transmit and/or receive interrupts should be disabled to avoid spurious interrupts. dma cycles always address the data holding regist ers or fifos, regardless of the selected bank. 0: dma mode disabled. (default.) 1: dma mode enabled. 1rts request to send. when loopback is enabled (bit 4 of ex cr1 = 1, bank 2, i/o offset 02h), this bit internally drives both cts and dcd. otherwise it is unused. 0dtr data terminal ready. when loopback is enabled (bit 4 of excr1 = 1, bank 2, i/o offset 02h), this bit internally drives both dsr and ri. otherwise it is unused. 394 amd geode? cs5535 companion device data book uart and ir port register descriptions 31506b mcr, non-extended mode (excr1.ext_sl = 0) 6.12.3.6 link status register (lsr) lsr provides status information concerning data transfer. upon reset, this register assumes the value of 60h. the bit defi- nitions change depending upon the operation mode of the functional block. bits 1 to 4 of the lsr indicate link st atus events. these bits are sticky (accumula te any conditions occurred since the last time the register was read). they are cl eared when one of the following events occur: hardware reset receiver soft reset (via the fifo control register) lsr register read the lsr is intended for read operations on ly. writing to the lsr is not permitted. mcr non-extended mode register map 76543210 rsvd loop isen or dcdlp rilp rts dtr mcr non-extended mode bit descriptions bit name description 7:5 rsvd reserved. must written as 0. 4loop loopback enable. this bit accesses the same internal register as loop (bit 4) of the excr1 register. (see section 6.12.5.2 on page 400 for more information on loopback mode). 0: loopback disabled. (default.) 1: loopback enabled. 3 isen or dcdlp interrupt signal enable or dcd loopback. in normal operation (standard 16450 or 16550) mode, this bit controls the interrupt signal and must be set to 1 in order to enable the inter- rupt request signal. in loopback mode, this bit internally drives dcd, and the interrupt signal is always enabled. 2rilp ring indicator in loopback. when loopback is enabled, this bit internally drives ri. other- wise, it is unused. 1rts request to send. when loopback is enabled, this bit drives cts internally. otherwise, it is unused. 0dtr data terminal ready. when loopback is enabled, this bit internally drives dsr. otherwise, it is unused. i/o offset 05h ty p e r o reset value 60h lsr register map 76543210 er_inf txemp txrdy brk fe pe oe rxda amd geode? cs5535 companion device data book 395 uart and ir port register descriptions 31506b lsr bit descriptions bit name description 7er_inf error in rx_fifo. in uart, sharp-ir, and sir modes, this bit is set to 1 if there is at least one framing error, parity error, or break indication in the rx_fifo. this bit is always 0 in 16450 mode. it is cleared upon read or upon rese t if there is no faulted byte in rx_fifo. 6 txemp transmitter empty. this bit is set to 1 when the transmitter holding register or the tx_fifo is empty, and the transmitter front end is idle. 5txrdy transmitter ready. this bit is set to 1 when the transmitter holding register or the tx_fifo is empty. it is cleared when a data character is written to the txd register. 4brk break event detected. in uart, sharp-ir, and sir modes, this bit is set to 1 when a break event is detected (i.e., when a sequence of logic 0 bits, equal or longer than a full character transmission, is received). if the fifos are enabled, the break condition is asso- ciated with the particular character in the rx _fifo to which it applie s. in this case, the brk bit is set when the character reaches the bottom of the rx_fifo. when a break event occurs, only one 0 character is transferred to th e receiver holding register or the rx_fifo. the next character transfer takes place after at least one logic 1 bit is received, followed by a valid start bit. this bit is cleared upon read. 3fe framing error. in uart, sharp-ir and sir modes, this bit is set to 1 when the received data character does not have a valid stop bit (i.e., the stop bit following the last data bit or parity bit is a 0). if the fifos are enabled, th is framing error is associated with the particu- lar character in the fifo it applies to. this erro r is revealed to the cpu when its associated character is at the bottom of the rx_fifo. a fter a framing error is detected, the receiver will try to resynchronize. the receiver assumes that framing error (the erroneous stop bit) is the next start bit (the erroneous stop bit) and sh ifts in the new character. this bit is cleared upon a read. 2pe parity error. in uart, sharp-ir, and sir modes, this bit is set to 1 if the received data character does not have the correct parity, ev en or odd, as selected by the parity control bits of the lcr. if t he fifos are enabled, this error is as sociated with the particular charac- ter in the fifo that it applies to. this error is revealed to the cpu when its associated char- acter is at the bottom of the rx_f ifo. this bit is cleared upon read. 1oe overrun error. in uart, sharp-ir, and sir modes, this bit is set to 1 as soon as an over- run condition is detected by the receiver. it is cleared upon read. fifos disabled: an overrun occurs when a ne w character is completely received into the receiver front end section and the cpu has not yet read the previous character in the receiver holding register. the new character overwrites the previous character in the receiver holding register. fifos enabled: an overrun occurs when a new character is completely received into the receiver front end section and the rx_fifo is full. the new character is discarded, and the rx_fifo is not affected. 0rxda receiver data available. this bit is set to 1 when the receiver holding register is full. if the fifos are enabled, this bit is set when at le ast one character is in the rx_fifo. it is cleared when the cpu reads all the data in the holding register or the rx_fifo. 396 amd geode? cs5535 companion device data book uart and ir port register descriptions 31506b 6.12.3.7 modem stat us register (msr) the function of this register depends on t he selected operational mode. when a uart mode is selected, this register pro- vides the current state as well as state- change information of the status lines fr om the modem or data transmission module. when any of the ir modes is se lected, the register func tion is controlled by the setting of the irmssl bit of the ircr2 (see section 6.12.8.2 on page 407). if irmssl is 0, the msr register works as in uart mode. if irmssl is 1, the msr returns the value 30h, regardless of the state of the modem input lines. when loopback is enabled, the msr works similarly except that its status input signals are internally driven by appropriate bits in the mcr since the modem input lines are internally disco nnected. refer to bits 1 to 0 in mcr extended mode or bits 3 to 0 in mcr non-extended mode (see section 6.12.3.5 on page 393) and to the loop and etdlbk bits at the excr1 (see section 6.12.5.2 on page 400). a modem status event (ms_ev) is generated if the ms_ie bit in ier is enabled and any of bits 0, 1, 2, or 3 in this register are set to 1. bits 0 to 3 are cleared to 0 as a re sult of any of the following events: a hardware reset occurs. the operational mode is changed and the irmssl bit is 0. ? the msr register is read. in the reset state, bits 4 to 7 are indeterminate as they reflect their corresponding signal levels at msr_uart[x]_mod. i/o offset 06h ty p e r o reset value x0h msr (modem status register) register map 76543210 dcd ri dsr cts ddcd teri ddsr dcts msr (modem status register) bit descriptions bit name description 7 dcd data carrier detect. this is the status of the mod5 bit in msr_uart[x]_mod (see sec- tion 6.12.1.1 on page 380). 6ri ring indicator. this is the status of the mod7 bit in msr_uart[x]_mod (see section 6.12.1.1 on page 380). 5dsr data set ready. this is the status of the mod6 bit in msr_uart[x]_mod (see section 6.12.1.1 on page 380). 4cts clear to send. this is the status of the mod4 bit in msr_uart[x]_mod (see section 6.12.1.1 on page 380). 3 ddcd delta data carrier detect. this bit is the delta data carrier detect (ddcd) indicator. when high, this bit indicates that the dcd input has changed state. reading this register causes this bit to be cleared. 2teri trailing edge ring indicator. this bit is the trailing edge ring indicator (teri) detector. when high, this bit indicates that the ri i nput has changed from a high to low state. read- ing this register causes this bit to be cleared. 1 ddsr delta data set ready. this bit is the delta data set ready (ddsr) indicator. when high, this bit indicates that the dsr input has changed state since the last time it was read by the cpu. reading this register causes this bit to be cleared. 0 dcts delta clear to send. this bit is the delta clear to send (dcts) indicator. when high, this bit indicates that the cts input has changed state since the last time it was read by the cpu. reading this register causes this bit to be cleared. amd geode? cs5535 companion device data book 397 uart and ir port register descriptions 31506b 6.12.3.8 scratchpad/auxiliary status and control registers the scratchpad register (spr) and au xiliary status and control register (ascr) share the same address. scratchpad register (spr) this register is accessed when the device is in non-extende d mode (excr1.ext_sl = 0). this is a scratchpad register for temporary data storage. auxiliary status and co ntrol register (ascr) ascr is accessed when the extended mode (excr1.ext_sl = 1) of operation is selected. the def inition of the bits in this case is dependent upon the mode selected in the mcr, bits 7 to 5. th is register is cleared upon hardware reset. bit 2 is also cleared when the transmitter is ?soft reset? (via the fifo control register) or after the s_eot byte is transmitted. bit 6 is also cleared when the transmitter is ?soft reset? or by writing 1 into it. bits 0, 1, 4, and 5 are also cleared when the receiver is ?soft reset? (via the fifo control register). i/o offset 07h ty p e r / w reset value 00h i/o offset 07h ty p e r / w reset value 00h ascr extended mode register map 7654321 0 rsvd txur rxact rxwdg rsvd s_eot rsvd rxf_tout ascr extended mode bit descriptions bit name description 7 rsvd reserved. write as 0. 6txur ir transmitter underrun. for ceir mode only. this bit is set to 1 when a transmitter underrun occurs. it is always cleared when a m ode other than ceir is selected. this bit must be cleared, by writing a 1 into it to re-enable transmission. 5rxact receiver active. for ceir mode only. this bit is set to 1 when an ir pulse or pulse-train is received. if a 1 is written into this bit position, the bit is cleared and the receiver deactivated. when this bit is set, the receiver samples the ir input continuously at the programmed baud and transfers the data to the rx_fifo. 4rxwdg reception watchdog. for ceir mode only. this bit is set to 1 each time a pulse or pulse-train (modulated pulse) is detected by t he receiver. it can be used by the software to detect a receiver idle condition. it is cleared upon read. 3 rsvd reserved. write as 0. 2s_eot set end of transmission. for ceir mode only. when a 1 is written into this bit position before writing the last character into the tx_f ifo, data transmission is properly completed. if the cpu simply stops writing data into th e tx_fifo at the end of the data stream, a transmitter underrun is generated and the transmitte r stops. in this case this is not an error, but the software must clear the underrun before the next transmission can occur. this bit is automatically cleared by hardware when a character is written to the tx_fifo. 1 rsvd reserved. write as 0. 0rxf_tout (ro) rx_fifo timeout (read only). this bit is set to 1 if the rx_fifo is below threshold and an rx_fifo timeout occurs. it is cleared w hen a character is read from the rx_fifo. 398 amd geode? cs5535 companion device data book uart and ir port register descriptions 31506b 6.12.4 bank 1 register descriptions the bit formats of the registers in bank 1 are summarized in table 6-36. detailed descriptions of each register follow. 6.12.4.1 legacy baud ge nerator divisor port legacy baud generator divisor low byte (lbgd_l) le gacy baud generator divisor high byte (lbgd_h) the legacy baud generator divisor (lbgd) port provides an alternate data path to the ba ud divisor generator register. lbgd is a 16-bit wide port split into two bytes, lbgd_l an lbgd_h, occupying consecutive address locations. this port is implemented to maintain compatibility with 16550 standard and to support existing legacy software packages. new soft- ware should use the bgd port in bank 2 to access the baud generator divisor register. the programmable baud rates in the non-extended mode are achieved by dividing a 24 mhz clock by a prescale value of 13, 1.625 or 1. this prescale value is selected by th e presl field of excr2 (sec tion 6.12.5.4 on page 403). divisor values between 1 and 2 16 -1 can be used (0 cannot be used, see table 6-38 "baud generator divisor settings" on page 399). the baud generator divisor must be loaded during in itialization to ensure proper operation of the baud genera- tor. upon loading either part of it, the baud generator counter is immediately loaded. table 6-38 shows typical baud divi- sors. after reset, the divisor register contents are indeterminate. if the uart is in extended mode, any access to the lbgd_l or lbgd_h causes a reset to the default non-extended mode (i.e., 16550 mode). to access a baud generator divisor when in extended mode, use the port pair in bank 2 (see section 6.12.5.1 "baud generator divisor port" on page 400). table 6-37 shows the bits that are cleared when fallback o ccurs during extended or non-extended modes. if the uart is in non-extended mode and the lock bit is 1, the content of the divisor (bgd) port is not be effected and no other action is taken. table 6-36. bank 1 bit map register bits i/o offsetname 76543210 00h lbgd_l lbgd[7:0] 01h lbgd_h lbgd[15:8] 02h rsvd rsvd 03h lcr bkse sbrk stkp eps pen stb wls1 wls0 bsr bkse bsr[6:0] 04-07h rsvd rsvd i/o offset 00h ty p e r / w reset value xxh i/o offset 01h ty p e r / w reset value xxh table 6-37. bits cleared on fallback register name uart mode and lock bit before fallback extended mode lock = x non-extended mode lock = 0 non-extended mode lock = 1 mcr 2 to 7 none none excr1 0, 5 and 7 5 and 7 none excr2 0 to 5 0 to 5 none ircr1 2 and 3 none none amd geode? cs5535 companion device data book 399 uart and ir port register descriptions 31506b 6.12.4.2 link control/bank se lect register (lcr/bsr) these registers share the same address and are the sa me as the registers at i/o offset 03h in bank 0. link control register (lcr) see section 6.12.3.4 "link control/bank sele ct registers" on page 390 for bit descriptions. bank selection encoding register (bsr) see section 6.12.3.4 "link control/bank sele ct registers" on page 390 for bit descriptions. table 6-38. baud generator divisor settings prescaler value 13 1.625 1 baud divisor % error divisor % error divisor % error 50 2304 0.16% 18461 0.00% 30000 0.00% 75 1536 0.16% 12307 0.01% 20000 0.00% 110 1047 0.19% 8391 0.01% 13636 0.00% 134.5 857 0.10% 6863 0.00% 11150 0.02% 150 768 0.16% 6153 0.01% 10000 0.00% 300 384 0.16% 3076 0.03% 5000 0.00% 600 192 0.16% 1538 0.03% 2500 0.00% 1200 96 0.16% 769 0.03% 1250 0.00% 1800 64 0.16% 512 0.16% 833 0.04% 2000 58 0.53% 461 0.12% 750 0.00% 2400 48 0.16% 384 0.16% 625 0.00% 3600 32 0.16% 256 0.16% 416 0.16% 4800 24 0.16% 192 0.16% 312 0.16% 7200 16 0.16% 128 0.16% 208 0.16% 9600 12 0.16% 96 0.16% 156 0.16% 14400 8 0.16% 64 0.16% 104 0.16% 19200 6 0.16% 48 0.16% 78 0.16% 28800 4 0.16% 32 0.16% 52 0.16% 38400 3 0.16% 24 0.16% 39 0.16% 57600 2 0.16% 16 0.16% 26 0.16% 115200 1 0.16% 8 0.16% 13 0.16% 230400 --- --- 4 0.16% --- --- 460800 --- --- 2 0.16% --- --- 750000 --- --- --- --- 2 0.00% 921600 --- --- 1 0.16% --- --- 1500000 --- --- --- --- 1 0.00% i/o offset 03h ty p e rw reset value 00h i/o offset 03h ty p e r / w reset value 00h 400 amd geode? cs5535 companion device data book uart and ir port register descriptions 31506b 6.12.5 bank 2 register descriptions the bit formats for the registers in bank 2 are summarized in table 6-39. detailed descriptions of each register follow. 6.12.5.1 baud genera tor divisor port baud generator divisor low byte (bgd_l) baud generator divisor high byte (bgd_h) this port performs the same function as the legacy baud div isor port in bank 1 and is accessed identically, but does not change the operation mode of the functional block when acce ssed. see section 6.12.4.1 "l egacy baud generator divisor port" on page 398 for more details. use this port to set the baud when operating in extended mode to avoid fallback to a non-extended operation mode (i.e., 16550 compatible). when programming the baud, writing to bgd_h causes the baud to change immediately. 6.12.5.2 extended contro l register 1 (excr1) use this register to control operation in the extended mode. upon reset, all bits are set to 0. table 6-39. bank 2 bit map register bits i/o offsetname76543210 00h bgd_l bgd[7:0] 01h bgd_h bgd[15:8] 02h excr1 rsvd edtlbk loop dmaswp dmath dmanf ext_sl 03h bsr bkse bsr[6:0] 04h excr2 lock rsvd presl[1:0] rf_siz[1:0] tf_siz1[1:0] 05h rsvd rsvd 06h txflv rsvd tfl[5:0] 07h rxflv rsvd rfl[5:0] i/o offset 00h ty p e r / w reset value xxh i/o offset 01h ty p e r / w reset value xxh i/o offset 02h ty p e r / w reset value 00h excr1 register map 76543210 rsvd edtlbk loop dmaswp dmath dmanf ext_sl excr1 bit descriptions bit name description 7:6 rsvd reserved. write as 0. 5edtlbk enable transmitter during loopback. when this bit is set to 1, the transmitter serial output is enabled and functions normally when loopback is enabled. amd geode? cs5535 companion device data book 401 uart and ir port register descriptions 31506b 4loop loopback enable. during loopback, the transmitter out put is connected internally to the receiver input, to enab le system self-test of serial commun ication. in additi on to the data signal, all additional signals within the uart are interconnected to enable real transmis- sion and reception using the uart mechanisms. when this bit is set to 1, loopback is selected. this bit accesses the same internal register as bit 4 in the mcr, when the uart is in a non-extended mode. loopback behaves similarly in both non-extended and extended modes. when extended mode is sele cted, the dtr bit of the mcr internally drives both dsr and ri, and the rts bit drives cts and dcd. during loopback, the following occurs: the transmitter and receiver interrupts are fully operational. the modem status inter- rupts are also fully operational, but the interrupt sources are now the lower bits of the mcr. modem interrupts in ir modes are di sabled unless the irmssl bit of the ircr2 is 0. individual interrupts are still controlled by the ier bits. the dma control signals are fully operational. uart and ir receiver serial input signals ar e disconnected. the internal receiver input signals are connected to the corresponding internal transmitter output signals. the uart transmitter serial output is forced high and the ir transmitter serial output is forced low, unless the etdlbk bit is set to 1, in which case they function normally. the virtual modem signals of msr_uart[x]_mod register (dsr, cts, ri and dcd) are disconnected. the internal modem status signals are driven by the lower bits of the mcr. 3 dmaswp dma swap. this bit selects the routing of the dma control signals between the internal dma logic and configuration module of the chip. when this bit is 0, the transmitter and receiver dma control signals are not swapped . when it is 1, they are swapped. a block diagram illustrating the control signals routing is shown in figure 6-2 "dma control sig- nals routing" on page 402. the swap featur e is particularly useful when only one 8237 dma channel is used to serve both transmitter and receiver. in this case, only one exter- nal dma request/dma acknowledge pair is interconnected to the swap logic by the con- figuration module. routing the external dma c hannel to either the transmitter or receiver dma logic is then controlled by the dmaswp bit. this way, the ir device drivers do not need to know the details of the configuration module. 2dmath dma fifo threshold. this bit selects the tx_fifo and rx_fifo threshold levels used by the dma request logic to support dema nd transfer mode. a transmission dma request is generated when the tx_fifo level is below the threshold. a reception dma request is generated when the rx_fifo level reaches t he threshold or when an rx_fifo timeout occurs. table 6-40 lists the threshold levels for each fifo. 1dmanf dma fairness control. this bit controls the maximum duration of dma burst transfers. 0: dma requests forced inactive after approxim ately 10.5 s of continuous transmitter and/or receiver dma operation (default). 1: tx-dma request is deactivated when th e tx_fifo is full. an rx dma request is deactivated when the rx_fifo is empty. 0 ext_sl extended mode select. when set to 1, extended mode is selected. excr1 bit descriptions (continued) bit name description 402 amd geode? cs5535 companion device data book uart and ir port register descriptions 31506b . figure 6-2. dma control signals routing table 6-40. dma threshold levels bit value dma threshold for fifo type rx_fifo tx_fifo 16 levels 32 levels 0 4 13 29 110 7 23 routing logic rx_dma rx-channel tx_dma dma handshake signals dmaswp dma swap logic configuration module dma logic tx-channel dma logic routing logic amd geode? cs5535 companion device data book 403 uart and ir port register descriptions 31506b 6.12.5.3 bank select register (bsr) bsr is the same as the bsr register at i/o offset 03h in bank 0. see section 6. 12.3.4 "link control/bank select regis- ters" on page 390 for bit descriptions. 6.12.5.4 extended contro l register 2 (excr2) excr2 configures the rx_fifo and tx_fifo sizes and the valu e of the prescaler, and controls the baud divisor register lock. upon reset, all bits are set to 0. i/o offset 03h ty p e r / w reset value 00h i/o offset 04h ty p e r / w reset value 00h excr2 register map 76543210 lock rsvd presl[1:0] rf_siz[1:0] tf_siz[1:0] excr2 bit descriptions bit name description 7 lock baud divisor register lock. when set to 1, any access to the baud generator divisor register through lbgd_l and lbgd_h, as well as fallback are disabled from non- extended mode. in this case, two scratchpad registers overlaid with lbgd_l and lbgd_h are enabled, and any attempted cpu access of the baud generator divisor reg- ister through lbgd_l and lbgd_h access the scratchpad registers instead. this bit must be set to 0 when extended mode is selected. 6 rsvd reserved. write as 0. 5:4 presl[1:0] prescaler select. the prescaler divides the 24 mhz input clock frequency to provide the clock for the baud generator. 00: 13 (default) 01: 1.625 10: reserved 11: 1.0 3:2 rf_siz[1:0] rx_fifo levels select. these bits select the number of levels for the rx_fifo. they are effective only when the fifo s are enabled. (fcr bit 0 = 1.) 00: 16 (default) 01: 32 1x: reserved 1:0 tf_siz[1:0] tx_fifo levels select. these bits select the number of levels for the tx_fifo. they are effective only when the fifo s are enabled. (fcr bit 0 = 1.) 00: 16 (default) 01: 32 1x: reserved 404 amd geode? cs5535 companion device data book uart and ir port register descriptions 31506b 6.12.5.5 tx_fifo current level register (txflv) txflv returns the number of bytes in the tx_fifo. 6.12.5.6 rx_fifo current level register (rxflv) rxflv returns the number of by tes in the rx_fifo. it can be used for software debugging. i/o offset 06h ty p e r o reset value 00h txflv register map 76543210 rsvd tfl[5:0] txflv bit descriptions bit name description 7:6 rsvd reserved. returns 0. 5:0 tfl[5:0] number of bytes in tx_fifo. these bits specify the num ber of bytes in the tx_fifo. note: the contents of txflv and rxflv are no t frozen during cpu reads. therefore, invalid data could be returned if the cpu reads these registers during normal transmitter and receiver operation. to obtain correct data, the software should perform three consecutive reads and then take the data from the second read if the first and second reads yield the same result. it can also be taken from the third read if the first and second reads yield different results. i/o offset 07h ty p e r o reset value 00h rxflv register map 76543210 rsvd rfl[5:0] rxflv bit descriptions bit name description 7:6 rsvd reserved. return 0s. 5:0 rfl[5:0] number of bytes in rx_fifo. these bits specify the number of bytes in the rx_fifo. note: the contents of txflv and rxflv are not frozen during cpu reads. therefore, invalid data could be returned if the cpu reads these registers during normal transmitter and receiver operation. to obtain correct data, the software should perform three consecutive reads and then take the data from the second read if the first and second reads yield the same result. it can also be taken from the third read if the first and second reads yield different results. amd geode? cs5535 companion device data book 405 uart and ir port register descriptions 31506b 6.12.6 bank 3 register descriptions the bit formats for the registers in bank 3 are summarized in table 6-41. detailed descriptions of each register follow. 6.12.6.1 module id entification and revision id register (mrid) mrid identifies the revision of the module. when read, it return s the module id and revision level in the format 0xh, where x indicates the revision number. 6.12.6.2 shadow of link control register (sh_lcr) sh_lcr returns the value of the lcr. the lcr is written into when a byte value, with bit 7 set to 0, is written to the lcr/bsr registers location (at i/o offset 03h) from any bank. table 6-41. bank 3 bit map register bits i/o offsetname 76543210 00h mrid mid[3:0] rid[3:0] 01h sh_lcr rsvd sbrk stkp eps pen stb wls1 wls0 02h sh_fcr rxfth[1:0] txfth[1:0] rsvd txsr rxsr fifo_en 03h bsr bkse bsr[6:0] 04h-07h rsvd rsvd i/o offset 00h ty p e r o reset value 0xh mrid register map 76543210 mid[3:0] rid[3:0] mrid bit descriptions bit name description 7:4 mid[3:0] module id. identifies the module type. 3:0 rid[3:0] revision id. identifies the module revision level. for example, 0h = revision 0, 1h = revi- sion 1, etc. i/o offset 01h ty p e r o reset value 00h sh_lcr register map 76543210 rsvd sbrk stkp eps pen stb wls1 wls0 406 amd geode? cs5535 companion device data book uart and ir port register descriptions 31506b 6.12.6.3 shadow of fifo control register (sh_fcr) this register returns the cont ents of the fcr in bank 0. 6.12.6.4 bank select register (bsr) bsr is the same as the bsr register at i/o offset 03h in bank 0. see section 6. 12.3.4 "link control/bank select regis- ters" on page 390 for bit descriptions. 6.12.7 bank 4 register descriptions the bit formats for the registers in bank 4 are summarized in table 6-42. detailed descriptions of each register follow. 6.12.7.1 ir control register 1 (ircr1) ircr1 enables the sharp-ir or sir ir mode in non-extende d mode of operation. upon reset, all bits are set to 0. i/o offset 02h ty p e r o reset value 00h fcr register map 76543210 rxfth[1:0] txfth[1:0] rsvd txsr rxsr fifo_en i/o offset 03h ty p e r / w reset value 00h table 6-42. bank 4 bit map register bits i/o offsetname 76543210 00h-01h rsvd rsvd 02h ircr1 rsvd ir_sl[1:0] rsvd 03h bsr bkse bsr[6:0] 04h-07h rsvd rsvd i/o offset 02h ty p e r / w reset value 00h ircr1 register map 76543210 rsvd ir_sl[1:0] rsvd ircr1 bit descriptions bit name description 7:4 rsvd reserved. write as 0. 3:2 ir_sl[1:0] sharp-ir or sir mode select. these bits enable sharp-ir and sir modes in non- extended mode. they allow selection of the appropriate ir interface when extended mode is not selected. these bits are ig nored when extended mode is selected. 00: uart (default). 01: reserved. 10: sharp-ir. 11: sir. 1:0 rsvd reserved. write as 0. amd geode? cs5535 companion device data book 407 uart and ir port register descriptions 31506b 6.12.7.2 bank select register (bsr) bsr is the same as the bsr register at i/o offset 03h in bank 0. see section 6. 12.3.4 "link control/bank select regis- ters" on page 390 for bit descriptions. 6.12.8 bank 5 register descriptions the bit formats for the registers in bank 5 are summarized in table 6-43. detailed descriptions of each register follow. 6.12.8.1 bank select register (bsr) bsr is the same as the bsr register at i/o offset 03h in bank 0. see section 6. 12.3.4 "link control/bank select regis- ters" on page 390 for bit descriptions. 6.12.8.2 ir control register 2 (ircr2) ircr2 controls the basic settings of the ir modes. upon reset, the content of this register is 02h. i/o offset 03h ty p e r / w reset value 00h table 6-43. bank 5 bit map register bits i/o offsetname 76543210 00h-02h rsvd rsvd 03h bsr bkse bsr[6:0] 04h ircr2 rsvd rsvd rsvd aux_irrx rsvd rsvd irmssl ir_fdplx 05h-07h rsvd rsvd i/o offset 03h ty p e r / w reset value 00h i/o offset 04h ty p e r / w reset value 02h ircr2 register map 76543210 rsvd rsvd rsvd aux_irrx rsvd rsvd irmssl ir_fdplx ircr2 bit descriptions bit name description 7:5 rsvd reserved. write to 0. 4 aux_irrx auxiliary ir input select. when set to 1, the ir signal is received from the auxiliary input. see table 6-51 "ir receive input selection" on page 416. 3:2 rsvd reserved. write to 0. 1 irmssl msr register function select in ir mode. this bit selects the behavior of the msr and modem status interrupt (ms_ev) when an ir mode is selected. when a uart mode is selected, the msr and the ms_ev f unction normally and this bit is ignored. 0: msr and ms_ev work in the ir modes as in the uart mode. 1: msr returns 30h, and ms_ev is disabled (default). 0ir_fdplx enable ir full duplex mode. when set to 1, the ir receiver is not masked during trans- mission. 408 amd geode? cs5535 companion device data book uart and ir port register descriptions 31506b 6.12.9 bank 6 register descriptions the bit formats for the registers in bank 6 are summarized in table 6-44. detailed descriptions of each register follow. 6.12.9.1 ir control register 3 (ircr3) ircr3 is used to select the operati ng mode of the sharp-ir interface. table 6-44. bank 6 bit map register bits i/o offsetname 7 6 5 43210 00h ircr3 shdm_ds shmd_ds rsvd 01h rsvd rsvd 02h sir_pw rsvd spw3 spw2 spw1 spw0 03h bsr bkse bsr[6:0] 04h-07h rsvd rsvd i/o offset 00h ty p e r / w reset value 20h ircr3 register map 76543210 shdm_ds shmd_ds rsvd ircr3 bit descriptions bit name description 7 shdm_ds sharp-ir demodulation disable. 0: internal 500 khz receiver demodulation enabled (default). 1: internal demodulation disabled. 6 shmd_ds sharp-ir modulation disable. 0: internal 500 khz transmitter modulation enabled (default). 1: internal modulation disabled. 5:0 rsvd reserved. read as written. amd geode? cs5535 companion device data book 409 uart and ir port register descriptions 31506b 6.12.9.2 sir pulse widt h register (sir_pw) sir_pw sets the pulse width fo r transmitted pulses in sir operation mode. thes e settings do not affect the receiver. upon reset, the content of this register is 00h, which defaults to a pulse width of 3/16 of the baud rate. 6.12.9.3 bank select register (bsr) bsr is the same as the bsr register at i/o offset 03h in bank 0. see section 6. 12.3.4 "link control/bank select regis- ters" on page 390 for bit descriptions. i/o offset 02h ty p e r / w reset value 00h sir_pw register map 76543210 rsvd spw[3:0] sir_pw bit descriptions bit name description 7:4 rsvd reserved. write to 0. 3:0 spw[3:0] sir pulse width. two codes for setting the pulse width are available. all other values for this field are reserved. 0000: pulse width = 3/16 of bit period (default). 1101: pulse width = 1.6 s. i/o offset 03h ty p e r / w reset value 00h 410 amd geode? cs5535 companion device data book uart and ir port register descriptions 31506b 6.12.10 bank 7 register descriptions the bit formats for the registers in bank 7 are summarized in table 6-44. detailed descriptions of each register follow. the ceir utilizes two carrier frequency ranges (see table 6-50 on page 413): low range - spans from 30 khz to 56 khz, in 1 khz increments. high range - includes three frequencies: 400 khz, 450 khz or 480 khz. high and low frequencies are specified independently to allow separate transmission and reception modulation settings. the transmitter uses the carrier frequency settings in table 6-50 "ceir carrier frequency encoding" on page 413. the two registers at i/o offsets 04h and 07 h (ir transceiver configuration registers) are provided to configure the virtual ir dongle interface via irsl[2:0] bits (to allo w legacy software writes on these bits). 6.12.10.1 ir receiver demodulator contro l register (irrxdc) irrxdc controls settings for sharp-ir and ceir reception. afte r reset, the content of this re gister is 29h. this setting selects a subcarrier frequency in a range between 34.61 khz and 38.26 khz for the ceir mode, and from 480.0 khz to 533.3 khz for the sharp-ir mode. the value of this register is ignored if the receiver demodulation for both modes is dis- abled (see bit 7 (shdm_ds) in sectio n 6.12.9.1 "ir control register 3 (ir cr3)" on page 408 and bit 4 (rcdm_ds) in section 6.12.10.3 "ceir configur ation register (rccfg)" on page 414). the available frequency ranges for ceir and sharp-ir modes are given in tables 6-46 through 6-48. table 6-45. bank 7 bit map register bits i/o offsetname 76543210 00h irrxdc dbw[2:0] dfr[4:0] 01h irtxmc mcpw[2:0] mcfr[4:0] 02h rccfg r_len t_ov rxhsc rcdm_ds rsvd txhsc rc_mmd[1:0] 03h bsr bkse bsr[6:0] 04h ircfg1 strv_ms rsvd set_irtx irrx1_lv rsvd iric[2:0] 05h-06h rsvd rsvd 07h ircfg4 rsvd irsl0_ds rxinv irsl21_ds rsvd i/o offset 00h ty p e r / w reset value 29h irrxdc register map 76543210 dbw[2:0] dfr[4:0] irrxdc bit descriptions bit name description 7:5 dbw[2:0] demodulator bandwidth. these bits set the demodulator bandwidth for the selected frequency range. the subcarrier signal fr equency must fall within the specified frequency range in order to be accepted. used for both sharp-ir and ceir modes. (default = 001.) 4:0 dfr[4:0] demodulator frequency. these bits select the subcarrier?s center frequency for the ceir mode. (default = 01001.) amd geode? cs5535 companion device data book 411 uart and ir port register descriptions 31506b table 6-46. ceir, low speed demodulator (rxhsc = 0) (frequency ranges in khz) dfr[4:0] dbw[2:0] bits (bits [7:5] of irrxdc) 001 010 011 100 101 110 min max min max min max min max min max min max 00011 28.6 31.6 27.3 33.3 26.1 35.3 25.0 37.5 24.0 40.0 23.1 42.9 00100 29.3 32.4 28.0 34.2 26.7 36.2 25.6 38.4 24.6 41.0 23.7 43.9 00101 30.1 33.2 28.7 35.1 27.4 37.1 26.3 39.4 25.2 42.1 24.3 45.1 00110 31.7 35.1 30.3 37.0 29.0 39.2 27.8 41.7 26.7 44.4 25.6 47.6 00111 32.6 36.0 31.1 38.1 29.8 40.3 28.5 42.8 27.4 45.7 26.3 48.9 01000 33.6 37.1 32.0 39.2 30.7 41.5 29.4 44.1 28.2 47.0 27.1 50.4 01001 34.6 38.3 33.0 40.4 31.6 42.8 30.3 45.4 29.1 48.5 28.0 51.9 01011 35.7 39.5 34.1 41.7 32.6 44.1 31.3 46.9 30.0 50.0 28.8 53.6 01100 36.9 40.7 35.2 43.0 33.7 45.5 32.3 48.4 31.0 51.6 29.8 55.3 01101 38.1 42.1 36.4 44.4 34.8 47.1 33.3 50.0 32.0 53.3 30.8 57.1 01111 39.4 43.6 37.6 45.9 36.0 48.6 34.5 51.7 33.1 55.1 31.8 59.1 10000 40.8 45.1 39.0 47.6 37.3 50.4 35.7 53.6 34.3 57.1 33.0 61.2 10010 42.3 46.8 40.4 49.4 38.6 52.3 37.0 55.6 35.6 59.3 34.2 63.5 10011 44.0 48.6 42.0 51.3 40.1 54.3 38.5 57.7 36.9 61.5 35.5 65.9 10101 45.7 50.5 43.6 53.3 41.7 56.5 40.0 60.0 38.4 64.0 36.9 68.6 10111 47.6 52.6 45.5 55.6 43.5 58.8 41.7 62.5 40.0 66.7 38.5 71.4 11010 49.7 54.9 47.4 57.9 45.3 61.4 43.5 65.2 41.7 69.5 40.1 74.5 11011 51.9 57.4 49.5 60.6 47.4 64.1 45.4 68.1 43.6 72.7 41.9 77.9 11101 54.4 60.1 51.9 63.4 49.7 67.2 47.6 71.4 45.7 76.1 43.9 81.6 table 6-47. consumer ir high speed demodulator (rxhsc = 1) (frequency ranges in khz) dfr[4:0] dbw[2:0] bits (bits [7:5] of irrxdc) 001 010 011 100 101 110 min max min max min max min max min max min max 00011 381.0 421.1 363.6 444.4 347.8 470.6 333.3 500.0 320.0 533.3 307.7 571.4 01000 436.4 480.0 417.4 505.3 400.0 533.3 384.0 564.7 369.2 600.0 355.6 640.0 01011 457.7 505.3 436.4 533.3 417.4 564.7 400.0 600.0 384.0 640.0 369.9 685.6 table 6-48. sharp-ir demodulator (frequency ranges in khz) dfr[4:0] dbw[2:0] bits (bits [7:5] of irrxdc) 001 010 011 100 101 110 min max min max min max min max min max min max xxxxx 480.0 533.3 457.1 564.7 436.4 600.0 417.4 640.0 400.0 685.6 384.0 738.5 412 amd geode? cs5535 companion device data book uart and ir port register descriptions 31506b 6.12.10.2 ir transmitter modulato r control register (irtxmc) irtxmc selects the modulation subcarrier parameters for ceir and sharp-ir mode transmission. for sharp-ir, only the subcarrier pulse width is controlled by this regist er; the subcarrier frequency is fixed at 500 khz. after reset, the value of this register is 69h, selecting a carrie r frequency of 36 khz and an ir pulse width of 7 s for ceir, or a pulse width of 0.8 s for sharp-ir. i/o offset 01h ty p e r / w reset value 69h irtxmc bit map 76543210 mcpw[2:0] mcfr[4:0] irtxmc bit descriptions bit name description 7:5 mcpw[2:0] modulation subcarrier pulse width. specifies the pulse width of the subcarrier clock, as shown in table 6-49. (default = 011.) 4:0 mcfr[4:0] modulation subcarrier frequency. these bits set the frequency for the ceir modula- tion subcarrier. the encoding is defined in table 6-50. (default = 01001.) table 6-49. modulation carrier pulse width mcpw[2:0] low frequency (txhsc = 0) (ceir only) high frequency (txhsc = 1) (ceir or sharp-ir) 0 0 0 reserved reserved 0 0 1 reserved reserved 0 1 0 6.0 s 0.7 s 0 1 1 7.0 s 0.8 s 1 0 0 9.0 s 0.9 s 1 0 1 10.6 s reserved 1 1 0 reserved reserved 1 1 1 reserved reserved amd geode? cs5535 companion device data book 413 uart and ir port register descriptions 31506b table 6-50. ceir carrier frequency encoding mcfr[4:0] low frequency (txhsc = 0) high frequency (txhsc = 1) 00000 reserved reserved 00001 reserved reserved 00010 reserved reserved 00011 30 khz 400 khz 00100 31 khz reserved 00101 32 khz reserved 00110 33 khz reserved 00111 34 khz reserved 01000 35 khz 450 khz 01001 36 khz reserved 01010 37 khz reserved 01011 38 khz 480 khz 01100 39 khz reserved 01101 40 khz reserved 01110 41 khz reserved 01111 42 khz reserved 10000 43 khz reserved 10001 44 khz reserved 10010 45 khz reserved 10011 46 khz reserved 10100 47 khz reserved 10101 48 khz reserved 10110 49 khz reserved 10111 50 khz reserved 11000 51 khz reserved 11001 52 khz reserved 11010 53 khz reserved 11011 54 khz reserved 11100 55 khz reserved 11101 56 khz reserved 11110 56.9 khz reserved 11111 reserved reserved 414 amd geode? cs5535 companion device data book uart and ir port register descriptions 31506b 6.12.10.3 ceir configur ation register (rccfg) rccfg controls the basic operation of the ceir mode. i/o offset 02h ty p e r / w reset value 00h rccfg register map 76543210 r_len t_ov rxhsc rcdm_ds rsvd txhsc rc_mmd[1:0] rccfg bit descriptions bit name description 7r_len run length control. when set to 1, this bit enables run length encoding/decoding. the format of a run length code is: yxxxxxxx, where y is the bit value and xxxxxxx is the number of bits minus 1 (selects from 1 to 128 bits). 6t_ov receiver sampling mode. 0: programmed t period sampling. 1: oversampling mode. 5 rxhsc receiver carrier frequency select. this bit selects the receiver demodulator fre- quency range. 0: low frequency: 30.0-56.9 khz. 1: high frequency: 400-480 khz. 4 rcdm_ds receiver demodulation disable. when this bit is 1, the internal demodulator is dis- abled. the internal demodulator, when enabled, performs carrier frequency checking and envelope generation. this bit must be set to 1 (disabled) when the demodulation is per- formed externally, or when oversampling mode is selected to determine the carrier fre- quency. 3 rsvd reserved. write as 0. 2 txhsc transmitter subcarrier frequency select. this bit selects the modulation carrier fre- quency range. 0: low frequency: 30.0-56.9 khz. 1: high frequency: 400-480 khz. 1:0 rc_mmd[1:0] transmitter modulator mode. determines how ir pulses are generated from the trans- mitted bit string. 00: c_pls modulation mode. pulses are generated continuously for the entire logic 0 bit time. 01: 8_pls modulation mode. 8 pulses are generat ed each time one or more logic 0 bits are transmitted following a logic 1 bit. 10: 6_pls modulation mode. 6 pulses are generat ed each time one or more logic 0 bits are transmitted following a logic 1 bit. 11: reserved. result is indeterminate. amd geode? cs5535 companion device data book 415 uart and ir port register descriptions 31506b 6.12.10.4 bank select register (bsr) bsr is the same as the bsr register at i/o offset 03h in bank 0. see section 6. 12.3.4 "link control/bank select regis- ters" on page 390 for bit descriptions. 6.12.10.5 ir interface configuration register 1 (ircfg1) ircfg1 holds the transceiver configuration data for sharp-ir and sir modes. it is also used to directly control the trans- ceiver operation mode when automatic configuration is not enable d. the two next-to-least significant bits are used to read the identification data of a plug -and-play ir interface adapter. i/o offset 03h ty p e r / w reset value 00h i/o offset 04h ty p e r / w reset value xxh ircfg1 register map 76543210 strv_ms rsvd set_rtx irrx1_lv rsvd iric[2:0] ircfg1 bit descriptions bit name description 7strv_ms special transceiver mode selection. when this r/w bit is set to 1, the uart[x]_ir_tx output signal is forced to active high and a timer is started. the timer times out after 64 micro-seconds, at which time the bit is reset and the uart[x]_ir_tx output signal becomes low again. the timer is restarted every time a 1 is written to this bit. although it is possible to extend the period during which uart[x]_ir_tx remains high beyond 64 micro-seconds, this should be avoided to prevent damage to the transmitter led. writing a 0 to this bit has no effect. 6 rsvd reserved. write as 0. 5 set_irtx set irtx. when this bit is set to 1, it forces the uart[x]_ir_tx signal high. caution: indefinite high output should be avoided as this condition can damage the transmitter led. 4 irrx1_lv irrx1 level (read only). this bit reflects the value of the uart[x]_ir_rx input signal. 3 rsvd reserved. write as 0. 2:0 iric[2:0] transceiver identification and control bits 2 through 0. the function of iric0 depends on whether the uart[x]_irsl0/irrx2 signal is programmed as an input or an output. if programmed as an input (irsl0_d s = 0, bit 5 of ircfg4) then upon a read, this bit returns the logic level of the signal. da ta written to this bit position is ignored. the other two signals (irsl1, irsl2) must be programmed as output s only (irsl21_ds = 1, bit 3 of ircfg4). if the uart[x]_irsl0/irrx2 signal is prog rammed as an output, iric[2:0] drives the irsl[2:0] signals to select the operation mode of an infrared dongle. (these bits are reflected in bits [4:2] of msr_uart[x]_dong ). when read, these bits return the values previously written. below is the operation mode encoding for non-serial transceivers. 00x: irda-data modes. 010: reserved. 011: 36 khz consumer ir. 100: 40 khz consumer ir. 101: 38 khz consumer ir 110: reserved. 111: 56.9 khz consumer ir. 416 amd geode? cs5535 companion device data book uart and ir port register descriptions 31506b 6.12.10.6 ir interface config uration 4 register (ircfg4) ircfg4 configures the receiver data path. i/o offset 07h ty p e r / w reset value 00h ircfg4 register map 76543210 rsvd irsl0_ds rxinv irsl21_ds rsvd ircfg4 bit descriptions bit name description 7:6 rsvd reserved. must be written 0. 5 irsl0_ds irsl0/irrx2 pin direction select. this bit determines the direction of the uart[x]_irsl0/irrx2 pin. see table 6-51. 0: pin direction is input (uart[x]_irrx2). 1: pin direction is output (uart[x]_irsl0). 4rxinv irrx signal invert. this bit supports optical transceivers with receive signals of oppo- site polarity (active high instead of active low) . when set to 1, an inverter is placed in the receiver input signal path. 3 irsl21_ds reserved. must be written 1. 2:0 rsvd reserved. must be written 0. table 6-51. ir receive input selection irsl0_ds (ircfg4, bit 5) aux_i rrx (ircr2, bit 4) selected irrx 0 0 irrx1 0 1 irrx2 1 0 irrx1 1 1 none selected amd geode? cs5535 companion device data book 417 direct memory access register descriptions 31506b 6.13 direct memory acce ss register descriptions the registers for the direct memory access (dma) are divided into three sets: standard geodelink device (gld) msrs (shared with divil, see secti on 6.6.1 on page 317.) dma specific msrs dma native registers the msrs are accessed via the rdmsr and wrmsr pro- cessor instructions. the msr address is derived from the perspective of the cpu core. see section 4.2 "msr addressing" on page 59 for more details. all msrs are 64 bits, however, the dma specific msrs (summarized in table 6-52) are called out as 16 bits. the dma module treats writes to t he upper 48 bits (i.e., bits [63:16]) of the 64-bit msrs as don?t cares and always returns 0 on these bits. the native registers associated with the dma module are summarized in table 6-53 and accessed as i/o addresses. the reference column in the summary tables point to the page where the register maps and bit descriptions are listed. table 6-52. dma specific msrs summary msr address type register name reset value reference 51400040h r/w dma mapper (dma_map) 0000h page 420 51400041h ro dma shadow channel 0 mode (dma_shdw_ch0) 00xxh page 421 51400042 ro dma shadow channel 1 mode (dma_shdw_ch1) 00xxh page 421 51400043 ro dma shadow channel 2 mode (dma_shdw_ch2) 00xxh page 421 51400044 ro dma shadow channel 3 mode (dma_shdw_ch3) 00xxh page 421 51400045h ro dma shadow channel 4 mode (dma_shdw_ch4] 00xxh page 421 51400046h ro dma shadow channel 5 mode (dma_shdw_ch5) 00xxh page 421 51400047h ro dma shadow channel 6 mode (dma_shdw_ch6) 00xxh page 421 51400048h ro dma shadow channel 7 mode (dma_shdw_ch7) 00xxh page 421 51400049h ro dma shadow mask (dma_msk_shdw) 00ffh page 422 table 6-53. dma native registers summary i/o address type width (bits) register name reset value reference 000h r/w 8 slave dma channel 0 memory address (dma_ch0_addr_byte) xxh page 422 001h r/w 8 slave dma channel 0 transfer count (dma_ch0_cnt_byte) xxh page 423 002h r/w 8 slave dma channel 1 memory address (dma_ch1_addr_byte) xxh page 422 003h r/w 8 slave dma channel 1 transfer count (dma_ch1_cnt_byte) xxh page 423 004h r/w 8 slave dma channel 2 memory address (dma_ch2_addr_byte) xxh page 422 418 amd geode? cs5535 companion device data book direct memory access register descriptions 31506b 005h r/w 8 slave dma channel 2 transfer count (dma_ch2_cnt_byte) xxh page 423 006h r/w 8 slave dma channel 3 memory address (dma_ch3_addr_byte) xxh page 422 007h r/w 8 slave dma channel 3 transfer count (dma_ch3_cnt_byte) xxh page 423 008h r 8 slave dma channel [3:0] status (dma_ch3:0_sts) 00h page 423 w 8 slave dma channel [3:0] command (dma_ch3:0_cmd) xxh page 424 009h wo 8 slave dma channel [3:0] software request (dma_ch3:0_sft_req) xxh page 424 00ah wo 8 slave dma channel [3:0] channel mask (dma_ch3:0_chmsk) xxh page 425 00bh wo 8 slave dma channel [3:0] mode (dma_ch3:0_mode) xxh page 425 00ch wo 8 slave dma channel [3:0] clear byte pointer (dma_ch3:0_clr_pntr) xxh page 426 00dh wo 8 slave dma channel [3:0] master clear (dma_ch3:0_mstr_clr) xxh page 426 00eh wo 8 slave dma channel [3:0] clear mask register (dma_ch3:0_clr_msk) xxh page 426 00fh wo 8 slave dma channel [3:0] write mask register (dma_ch3:0_wr_msk) 0fh page 427 0c0h r/w 8 master dma channel 4 memory address (dma_ch4_addr_byte) xxh page 427 0c2h r/w 8 master dma channel 4 transfer count (dma_ch4_cnt_byte) xxh page 428 0c4h r/w 8 master dma channel 5 memory address (dma_ch5_addr_byte) xxh page 427 0c6h r/w 8 master dma channel 5 transfer count (dma_ch5_cnt_byte) xxh page 428 0c8h r/w 8 master dma channel 6 memory address (dma_ch6_addr_byte) xxh page 427 0cah r/w 8 master dma channel 6 transfer count (dma_ch6_cnt_byte) xxh page 428 0cch r/w 8 master dma channel 7 memory address (dma_ch7_addr_byte) xxh page 427 0ceh r/w 8 master dma channel 7 transfer count (dma_ch7_cnt_byte) xxh page 428 0d0h r 8 master dma channel [7:4] status (dma_ch7:4_sts) 00h page 428 w 8 master dma channel [7:4] command (dma_ch7:4_cmd) xxh page 429 0d2h wo 8 master dma channel [7:4] software request (dma_ch7:4_sft_req) xxh page 429 table 6-53. dma native registers summary (continued) i/o address type width (bits) register name reset value reference amd geode? cs5535 companion device data book 419 direct memory access register descriptions 31506b 0d4h wo 8 master dma channel [7:4] channel mask (dma_ch7:4_chmsk) xxh page 430 0d6h wo 8 master dma channel [7:4] mode (dma_ch7:4_mode) xxh page 430 0d8h wo 8 master dma channel [7:4] clear byte pointer (dma_ch7:4_clr_pntr) xxh page 431 0dah wo 8 master dma channel [7:4] master clear (dma_ch7:4_mstr_clr) xxh page 431 0dch wo 8 master dma channel [7:4] clear mask (dma_ch7:4_clr_msk) xxh page 431 0deh wo 8 master dma channel [7:4] write mask (dma_ch7:4_wr_msk) 0fh page 432 080h r/w 8 post code display register (post_display) 00h page 432 081h r/w 8 dma channel 2 low page (dma_ch2_lo_page) 00h page 433 082h r/w 8 dma channel 3 low page (dma_ch3_lo_page) 00h page 433 083h r/w 8 dma channel 1 low page (dma_ch1_lo_page) 00h page 433 087h r/w 8 dma channel 0 low page (dma_ch0_lo_page) 00h page 433 089h r/w 8 dma channel 6 low page (dma_ch6_lo_page) 00h page 433 08ah r/w 8 dma channel 7 low page (dma_ch7_lo_page) 00h page 433 08bh r/w 8 dma channel 5 low page (dma_ch5_lo_page) 00h page 433 08fh r/w 8 dma channel 4 low page (dma_ch4_lo_page) 00h page 433 481h r/w 8 dma channel 2 high page (dma_ch2_hi_page) 00h page 434 482h r/w 8 dma channel 3 high page (dma_ch3_hi_page) 00h page 434 483h r/w 8 dma channel 1 high page (dma_ch1_hi_page) 00h page 434 487h r/w 8 dma channel 0 high page (dma_ch0_hi_page) 00h page 434 489h r/w 8 dma channel 6 high page (dma_ch6_hi_page) 00h page 434 48ah r/w 8 dma channel 7 high page (dma_ch7_hi_page) 00h page 434 48bh r/w 8 dma channel 5 high page (dma_ch5_hi_page) 00h page 434 48fh r/w 8 dma channel 4 high page (dma_ch4_hi_page) 00h page 434 table 6-53. dma native registers summary (continued) i/o address type width (bits) register name reset value reference 420 amd geode? cs5535 companion device data book direct memory access register descriptions 31506b 6.13.1 dma specific msrs 6.13.1.1 dma mapper (dma_map) msr address 51400040h ty p e r / w reset value 0000h dma_map register map 1514131211109876543210 rsvd dma_ch3_map rsvd dma_ch2_map rsvd dma_ch1_map rsvd dma_ch0_map dma_map bit descriptions bit name description 15 rsvd reserved. no effect on dma mapper functionality; reads return value written. 14:12 dma_ch3_map dma channel 3 source select. 000: dma channel 3 off. 100: uart2 receive. 001: uart1 transmit. 101: reserved; not active. 010: uart1 receive. 110: reserved; not active. 011: uart2 transmit. 111: lpc dma channel 3. 11 rsvd reserved. no effect on dma mapper functionality; reads return value written. 10:8 dma_ch2_map dma channel 2 source select. 000: dma channel 2 off. 100: uart2 receive. 001: uart1 transmit. 101: reserved; not active. 010: uart1 receive. 110: reserved; not active. 011: uart2 transmit. 111: lpc dma channel 2. 7 rsvd reserved. no effect on dma mapper functionality; reads return value written. 6:4 dma_ch1_map dma channel 1 source select. 000: dma channel 1 off. 100: uart2 receive. 001: uart1 transmit. 101: reserved; not active. 010: uart1 receive. 110: reserved; not active. 011: uart2 transmit. 111: lpc dma channel 1. 3 rsvd reserved. no effect on dma mapper functionality; reads return value written. 2:0 dma_ch0_map dma channel 0 source select. 000: dma channel 0 off. 100: uart2 receive. 001: uart1 transmit. 101: reserved; not active. 010: uart1 receive. 110: reserved; not active. 011: uart2 transmit. 111: lpc dma channel 0. amd geode? cs5535 companion device data book 421 direct memory access register descriptions 31506b 6.13.1.2 dma shadow channel [7:0] mode (dma_shdw_ch[x]) dma shadow channel 0 mode (dma_shdw_ch0) dma shadow channel 1 mode (dma_shdw_ch1) dma shadow channel 2 mode (dma_shdw_ch2) dma shadow channel 3 mode (dma_shdw_ch3) dma shadow channel 4 mode (dma_shdw_ch4] dma shadow channel 5 mode (dma_shdw_ch5) dma shadow channel 6 mode (dma_shdw_ch6) dma shadow channel 7 mode (dma_shdw_ch7) msr address 51400041h ty p e r o reset value 00xxh msr address 51400042 ty p e r o reset value 00xxh msr address 51400043 ty p e r o reset value 00xxh msr address 51400044 ty p e r o reset value 00xxh msr address 51400045h ty p e ro reset value 00xxh msr address 51400046h ty p e ro reset value 00xxh msr address 51400047h ty p e ro reset value 00xxh msr address 51400048h ty p e ro reset value 00xxh dma_shdw_ch[x] register map 1514131211109876543210 rsvd trans_mode addr_dir auto_init trans_type ch_num dma_shdw_ch[x] bit descriptions bit name description 15:8 rsvd reserved. reads as 00h. 7:6 trans_mode data transfer mode. 00: demand. 10: block. 01: single. 11: cascade 5 addr_dir address direction. 0: increment; 1: decrement. 4 auto_init auto-initialization enable. 0: disabled; 1: enabled. 3:2 trans_type transfer type. 00: verify. 10: memory read. 01: memory write. 11: reserved. 1:0 ch_num channel number [3:0]. 00: channel 0. 10: channel 2. 01: channel 1. 11: channel 3. channel number [7:4]. 00: channel 4. 10: channel 6. 01: channel 5. 11: channel 7. 422 amd geode? cs5535 companion device data book direct memory access register descriptions 31506b 6.13.1.3 dma shadow mask (dma_msk_shdw) 6.13.2 dma native registers these registers reside in the i/o address space. 6.13.2.1 slave dma channel [3:0] me mory address (dma_ch[x]_addr_byte) slave dma channel 0 memory address (dma_ch0_addr_byte) slave dma channel 1 memory address (dma_ch1_addr_byte) slave dma channel 2 memory address (dma_ch2_addr_byte) slave dma channel 3 memory address (dma_ch3_addr_byte) msr address 51400049h ty p e r o reset value 00ffh dma__msk_shdw register map 1514131211109876543210 rsvd ch7mask ch6mask ch5mask ch4mask ch3mask ch2mask ch1mask ch0mask dma__msk_shdw bit descriptions bit name description 15:8 reserved reserved. reads as 00h. 7 ch7mask channel 7 mask reflects value of channel 7 mask bit. 0: not masked; 1: masked. 6 ch6mask channel 6 mask. reflects value of channel 6 mask bit. 0: not masked; 1: masked. 5 ch5mask channel 5 mask. reflects value of channel 5 mask bit. 0: not masked; 1: masked. 4 ch4mask channel 4 mask. reflects value of channel 4 mask bit. 0: not masked; 1: masked. 3 ch3mask channel 3 mask. reflects value of channel 3 mask bit. 0: not masked; 1: masked. 2 ch2mask channel 2 mask. reflects value of channel 2 mask bit. 0: not masked; 1: masked. 1 ch1mask channel 1 mask. reflects value of channel 1 mask bit. 0: not masked; 1: masked. 0 ch0mask channel 0 mask. reflects value of channel 0 mask bit. 0: not masked; 1: masked. i/o address 000h ty p e r / w reset value xxh i/o address 002h ty p e r / w reset value xxh i/o address 004h ty p e r / w reset value xxh i/o address 006h ty p e r / w reset value xxh dma_ch[x]_addr_byte register map 76543210 dma_ch_addr_byte dma_ch[x]_addr_byte bit descriptions bit name description 7:0 dma_ch_addr_byte dma channel address. read/write in two successive bus cycles, low byte first. amd geode? cs5535 companion device data book 423 direct memory access register descriptions 31506b 6.13.2.2 slave dma channel [3:0] tr ansfer count (dma_ch[x]_cnt_byte) slave dma channel 0 transfer count (dma_ch0_cnt_byte) slave dma channel 1 transfer count (dma_ch1_cnt_byte) slave dma channel 2 transfer count (dma_ch2_cnt_byte) slave dma channel 3 transfer count (dma_ch3_cnt_byte) 6.13.2.3 dma channel [3:0] status / command slave dma channel [3:0] status (dma_ch3:0_sts) i/o address 001h ty p e r / w reset value xxh i/o address 003h ty p e r / w reset value xxh i/o address 005h ty p e r / w reset value xxh i/o address 007h ty p e r / w reset value xxh dma_ch[x]_cnt_byte register map 76543210 dma_ch_cnt_byte dma_ch[x]_cnt_byte bit descriptions bit name description 7:0 dma_ch_cnt_byte dma channel transfer count. read/write in two successive bus cycles, low byte first. i/o address 008h ty p e r reset value 00h dma_ch3:0_sts register map 76543210 dma_ch3_rq dma_ch2_rq dma_ch1_rq dma_ch0_rq dma_ch3_tc dma_ch2_tc dma_ch1_tc dma_ch0_tc dma_ch3:0_status bit descriptions bit name description 7 dma_ch3_rq channel 3 dma request. 0: not pending; 1: pending. 6 dma_ch2_rq channel 2 dma request. 0: not pending; 1: pending. 5 dma_ch1_rq channel 1 dma request. 0: not pending; 1: pending. 4 dma_ch0_rq channel 0 dma request. 0: not pending; 1: pending. 3 dma_ch3_tc channel 3 terminal count. 0: count not reached; 1: count reached. 2 dma_ch2_tc channel 2 terminal count. 0: count not reached; 1: count reached. 1 dma_ch1_tc channel 1 terminal count. 0: count not reached; 1: count reached. 0 dma_ch0_tc channel 0 terminal count. 0: count not reached; 1: count reached. 424 amd geode? cs5535 companion device data book direct memory access register descriptions 31506b slave dma channel [3:0] command (dma_ch3:0_cmd) 6.13.2.4 slave dma channel [3:0] so ftware request (dma_ch3:0_sft_req) i/o address 008h ty p e w reset value xxh dma_ch3:0_cmd register map 76543210 dack_sense dreq_sense wr_timing pr_mode tm_mode dma_dis rsvd dma_ch3:0_cmd bi t descriptions bit name description 7 dack_sense dack sense. 0: active low; 1: active high. 6 dreq_sense dreq sense. 0: active high; 1: active low. 5 wr_timing write timing. 0: late write; 1: extended write. 4 pr_mode priority mode. 0: fixed priority; 1: rotating priority. 3 tm_mode timing mode. 0: normal timing; 1: compressed timing. 2dma_dis dma disable. 0: dma enable for channels [3:0]; 1: dma disable for channels [3:0]. 1:0 rsvd reserved. bit 0 must be written with value 0; bit 1 value is don?t care. i/o address 009h ty p e w o reset value xxh dma_ch3:0_sft_req register map 76543210 rsvd dma_rq dma_ch_sel dma_ch3:0_sft_req bit descriptions bit name description 7:3 rsvd reserved. write value is don?t care. 2dma_rq dma request. set to 1 to enable dma request. 1:0 dma_ch_sel dma channel select. 00: channel 0. 10: channel 2. 01: channel 1. 11: channel 3. amd geode? cs5535 companion device data book 425 direct memory access register descriptions 31506b 6.13.2.5 slave dma channel [3:0] channel mask (dma_ch3:0_chmsk) 6.13.2.6 slave dma channel [3:0] mode (dma_ch3:0_mode) i/o address 00ah ty p e w o reset value xxh dma_ch3:0_chmsk register map 76543210 rsvd ch_mask dma_ch_sel dma_ch3:0_chmsk bit descriptions bit name description 7:3 rsvd reserved. write value is don?t care. 2 ch_mask channel mask. set to 1 to mask out dma for selected channel. 1:0 dma_ch_sel dma channel select. 00: channel 0. 10: channel 2. 01: channel 1. 11: channel 3. i/o address 00bh ty p e w o reset value xxh dma_ch3:0_mode register map 76543210 trans_mode addr_dir auto_init trans_type dma_ch_sel dma_ch3:0_mode bit descriptions bit name description 7:6 trans_mode data transfer mode. 00: demand. 10: block. 01: single. 11: cascade. 5 addr_dir address direction. 0: increment; 1: decrement. 4 auto_init auto-initialization enable. 0: disabled; 1: enabled. 3:2 trans_type transfer type. 00: verify. 10: memory read. 01: memory write. 11: reserved 1:0 dma_ch_sel dma channel select. 00: channel 0. 10: channel 2. 01: channel 1. 11: channel 3. 426 amd geode? cs5535 companion device data book direct memory access register descriptions 31506b 6.13.2.7 slave dma channe l [3:0] clear byte poin ter (dma_ch3:0_clr_pntr) 6.13.2.8 slave dma channel [3:0] m aster clear (dma_ch3:0_mstr_clr) 6.13.2.9 slave dma channel [3:0] clear mask register (dma_ch3:0_clr_msk) i/o address offset 00ch ty p e w o reset value xxh dma_ch3:0_clr_pntr register map 76543210 clr_pntr (dummy_val) dma_ch3:0_clr_pntr bit descriptions bit name description 7:0 clr_pntr clear pointer. a write with any data (dummy value) resets high/low byte pointer for channels 3:0 memory address and terminal count registers. i/o address 00dh ty p e w o reset value xxh dma_ch3:0_mstr_cl r register map 76543210 mstr_clr (dummy_val) dma_ch3:0_mstr_clr bit descriptions bit name description 7:0 mstr_clr master clear. a write with any data (dummy value) resets the 8237 dma controller for channels [3:0]. i/o address 00eh ty p e w o reset value xxh dma_ch3:0_clr_msk register map 76543210 clr_msk (dummy_val) dma_ch3:0_clr_msk bit descriptions bit name description 7:0 clr_msk clear mask. a write with any data (dummy value) clears the mask bits for channels [3:0]. amd geode? cs5535 companion device data book 427 direct memory access register descriptions 31506b 6.13.2.10 slave dma channel [3:0] writ e mask register (dma_ch3:0_wr_msk) 6.13.2.11 master dma channel [7:4] me mory address (dma_ch[x]_addr_byte) master dma channel 4 memory address (dma_ch4_addr_byte) master dma channel 5 memory address (dma_ch5_addr_byte) master dma channel 6 memory address (dma_ch6_addr_byte) master dma channel 7 memory address (dma_ch7_addr_byte) i/o address 00fh ty p e w o reset value 0fh dma_ch3:0_wr_msk register map 76543210 rsvd ch3_mask ch2_mask ch1_mask ch0_mask dma_ch3:0_wr_msk bit descriptions bit name description 7:4 reserved reserved. write value is don?t care. 3 ch3_mask channel 3 mask value. 0: not masked; 1: masked. 2 ch2_mask channel 2 mask value. 0: not masked; 1: masked. 1 ch1_mask channel 1 mask value. 0: not masked; 1: masked. 0 ch0_mask channel 0 mask value. 0: not masked; 1: masked. i/o address 0c0h ty p e r / w reset value xxh i/o address 0c4h ty p e r / w reset value xxh i/o address 0c8h ty p e r / w reset value xxh i/o address 0cch ty p e r / w reset value xxh dma_ch[x]_addr_byte register map 76543210 dma_ch_addr_byte dma_ch[x]_addr_byte bit descriptions bit name description 7:0 dma_ch_addr_byte dma channel address. read/write in two successive bus cycles, low byte first. 428 amd geode? cs5535 companion device data book direct memory access register descriptions 31506b 6.13.2.12 master dma channel [7:4] tr ansfer count (dma_ch[x]_cnt_byte) master dma channel 4 transfer count (dma_ch4_cnt_byte) master dma channel 5 transfer count (dma_ch5_cnt_byte) master dma channel 6 transfer count (dma_ch6_cnt_byte) master dma channel 7 transfer count (dma_ch7_cnt_byte) 6.13.2.13 dma channel [7:4] status / command master dma channel [7:4] status (dma_ch7:4_sts) i/o address 0c2h ty p e r / w reset value xxh i/o address 0c6h ty p e r / w reset value xxh i/o address 0cah ty p e r / w reset value xxh i/o address 0ceh ty p e r / w reset value xxh dma_ch[x]_cnt_byte register map 76543210 dma_ch_cnt_byte dma_ch[x]_cnt_byte bit descriptions bit name description 7:0 dma_ch_cnt_byte dma channel transfer count. read/write in two successive bus cycles, low byte first. i/o address 0d0h ty p e r reset value 00h dma_ch7:4_sts register map 76543210 dma_ch7_rq dma_ch6_rq dma_ch5_rq dma_ch4_rq dma_ch7_tc dma_ch6_tc dma_ch5_tc dma_ch4_tc dma_ch7:4_sts bit descriptions bit name description 7 dma_ch7_rq channel 7 dma request. 0: not pending; 1: pending. 6 dma_ch6_rq channel 6 dma request. 0: not pending; 1: pending. 5 dma_ch5_rq channel 5 dma request. 0: not pending; 1: pending. 4 dma_ch4_rq channel 4 dma request. 0: not pending; 1: pending. 3 dma_ch7_tc channel 7 terminal count. 0: count not reached; 1: count reached. 2 dma_ch6_tc channel 6 terminal count. 0: count not reached; 1: count reached. 1 dma_ch5_tc channel 5 terminal count. 0: count not reached; 1: count reached. 0 dma_ch4_tc channel 4 terminal count. 0: count not reached; 1: count reached. amd geode? cs5535 companion device data book 429 direct memory access register descriptions 31506b master dma channel [7:4] command (dma_ch7:4_cmd) 6.13.2.14 master dma channel [7:4] so ftware request (dma_ch7:4_sft_req) i/o address 0d0h ty p e w reset value xxh dma_ch7:4_cmd register map 76543210 dack_sense dreq_sense wr_timing pr_mode tm_mode dma_dis rsvd dma_ch7:4_cmd bi t descriptions bit name description 7 dack_sense dack sense. 0: active low; 1: active high. 6 dreq_sense dreq sense. 0: active high; 1: active low. 5 wr_timing write timing. 0: late write; 1: extended write. 4 pr_mode priority mode. 0: fixed priority; 1: rotating priority. 3 tm_mode timing mode. 0: normal timing; 1: compressed timing. 2dma_dis dma disable. 0: dma enable for channels [7:4]; 1: dma disable for channels [7:4]. 1:0 rsvd reserved. bit 0 must be written with value 0; bit 1 value is don?t care. i/o address 0d2h ty p e w o reset value xxh dma_ch7:4_sft_req register map 76543210 rsvd dma_rq dma_ch_sel dma_ch7:4_sft_req bit descriptions bit name description 7:3 rsvd reserved. write value is don?t care. 2dma_rq dma request. set to 1 to enable dma request. 1:0 dma_ch_sel dma channel select. 00: channel 4. 10: channel 6. 01: channel 5. 11: channel 7. 430 amd geode? cs5535 companion device data book direct memory access register descriptions 31506b 6.13.2.15 master dma channel [7:4] channel mask (d ma_ch7:4_chmsk) 6.13.2.16 master dma channel [7:4] mode (dma_ch7:4_mode) i/o address 0d4h ty p e w o reset value xxh dma_ch7:4_chmsk register map 76543210 rsvd ch_mask dma_ch_sel dma_ch7:4_chmsk bit descriptions bit name description 7:3 rsvd reserved. write value is don?t care. 2 ch_mask channel mask. set to 1 to mask out dma for selected channel. 1:0 dma_ch_sel dma channel select. 00: channel 4. 10: channel 6. 01: channel 5. 11: channel 7. i/o address 0d6h ty p e w o reset value xxh dma_ch7:4_mode register map 76543210 trans_mode addr_dir auto_init trans_type dma_ch_sel dma_ch7:4_mode bit descriptions bit name description 7:6 trans_mode data transfer mode. 00: demand. 10: block. 01: single. 11: cascade. 5 addr_dir address direction. 0: increment; 1: decrement. 5 auto_init auto-initialization enable. 0: disabled; 1: enabled. 3:2 trans_type transfer type. 00: verify. 10: memory read. 01: memory write. 11: reserved 1:0 dma_ch_sel dma channel select. 00: channel 4. 10: channel 6. 01: channel 5. 11: channel 7. amd geode? cs5535 companion device data book 431 direct memory access register descriptions 31506b 6.13.2.17 master dma channel [7:4] clea r byte pointer (dma_ch7:4_clr_pntr) 6.13.2.18 master dma channel [7:4] ma ster clear (dma_ch7:4_mstr_clr) 6.13.2.19 master dma channel [7:4 ] clear mask (dma_ch7:4_clr_msk) i/o address 0d8h ty p e w o reset value xxh dma_ch7:4_clr_pntr register map 76543210 clr_pntr (dummy_val) dma_ch7:4_clr_pntr bit descriptions bit name description 7:0 clr_pntr clear pointer. a write with any data (dummy value) resets high/low byte pointer for channels [7:4] memory address and terminal count registers. i/o address offset 0dah ty p e w o reset value xxh dma_ch7:4_mstr_clr re gister descriptions 76543210 mstr_clr (dummy_val) dma_ch7:4_mstr_clr bit descriptions bit name description 7:0 mstr_clr master clear. a write with any data (dummy value) resets the 8237 dma controller for channels [7:4]. i/o address offset 0dch ty p e w o reset value xxh dma clear mask regist er for channels 7:4 76543210 clr_msk (dummy_val) dma_ch7:4_clr_msk bit descriptions bit name description 7:0 clr_msk clear mask. a write with any data (dummy value) clears the mask bits for channels [7:4]. 432 amd geode? cs5535 companion device data book direct memory access register descriptions 31506b 6.13.2.20 master dma channel [7:4 ] write mask (dma_ch7:4_wr_msk) 6.13.2.21 post code display register (post_display) . i/o address 0deh ty p e w o reset value 0fh dma_ch7:4_wr_msk register map 76543210 rsvd ch7_mask ch6_mask ch5_mask ch4_mask dma_ch7:4_wr_msk bit descriptions bit name description 7:4 rsvd reserved. write value is don?t care. 3 ch7_mask channel 7 mask value. 0: not masked; 1: masked. 2 ch6_mask channel 6 mask value. 0: not masked; 1: masked. 1 ch5_mask channel 5 mask value. 0: not masked; 1: masked. 0 ch4_mask channel 4 mask value. 0: not masked; 1: masked. i/o address 080h ty p e r / w reset value 00h post_display register map 76543210 post_code post_display bit descriptions bit name description 7:0 post_code post code display value. this register is the historical port 80 that receives the post (power-on self-test) codes reported during in itialization. typically used by the bios, port 80 may also be written to by any piece of executing software to provide status or other information. the most recent value writte n to port 80 is recorded in this register. amd geode? cs5535 companion device data book 433 direct memory access register descriptions 31506b 6.13.2.22 dma channel [3:0] lo w page (dma_ch[x]_lo_page) dma channel 2 low page (dma_ch2_lo_page) dma channel 3 low page (dma_ch3_lo_page) dma channel 1 low page (dma_ch1_lo_page) dma channel 0 low page (dma_ch0_lo_page) 6.13.2.23 dma channel [7:4] low page (dma_ch[x]_lo_page) dma channel 6 low page (dma_ch6_lo_page) dma channel 7 low page (dma_ch7_lo_page) dma channel 5 low page (dma_ch5_lo_page) dma channel 4 low page (dma_ch4_lo_page) i/o address 081h ty p e r / w reset value 00h i/o address 082h ty p e r / w reset value 00h i/o address 083h ty p e r / w reset value 00h i/o address offset 087h ty p e r / w reset value 00h dma_ch[x]_lo_page register map 76543210 dma_ch_lo_page dma_ch[x]_lo_page bit descriptions bit name description 7:0 dma_ch_lo_page dma channel low page value. address bits [23:16]. i/o address 089h ty p e r / w reset value 00h i/o address 08ah ty p e r / w reset value 00h i/o address 08bh ty p e r / w reset value 00h i/o address 08fh ty p e r / w reset value 00h dma_ch[x]_lo_page register map 76543210 dma_ch_lo_page rsvd dma_ch[x]_lo_page bit descriptions bit name description 7:1 dma_ch_lo_page dma channel low page value. address bits [23:17]. 0 rsvd reserved. not used to generate dma address. write value is don?t care; reads return value written. 434 amd geode? cs5535 companion device data book direct memory access register descriptions 31506b 6.13.2.24 dma channel [7:0] high page (dma_ch[x]_hi_page) dma channel 2 high page (dma_ch2_hi_page) this register is also cleared on any access to i/o port 81h. dma channel 3 high page (dma_ch3_hi_page) this register is also cleared on any access to i/o port 82h. dma channel 1 high page (dma_ch1_hi_page) this register is also cleared on any access to i/o port 83h. dma channel 0 high page (dma_ch0_hi_page) this register is also cleared on any access to i/o port 87h. dma channel 6 high page (dma_ch6_hi_page) this register is also cleared on any access to i/o port 89h. dma channel 7 high page (dma_ch7_hi_page) this register is also cleared on any access to i/o port 8ah. dma channel 5 high page (dma_ch5_hi_page) this register is also cleared on any access to i/o port 8bh. dma channel 4 high page (dma_ch4_hi_page) this register is also cleared on any access to i/o port 8fh. i/o address 481h ty p e r / w reset value 00h i/o address 482h ty p e r / w reset value 00h i/o address 483h ty p e r / w reset value 00h i/o address 487h ty p e r / w reset value 00h i/o address 489h ty p e r / w reset value 00h i/o address offset 48ah ty p e r / w reset value 00h i/o address 48bh ty p e r / w reset value 00h i/o address 48fh ty p e r / w reset value 00h dma_ch[x]_hi_pag e register map 76543210 dma_ch_hi_page dma_ch[x]_hi_page bit descriptions bit name description 7:0 dma_ch_hi_page dma channel high page value. address bits [31:24]. amd geode? cs5535 companion device data book 435 low pin count register descriptions 31506b 6.14 low pin count r egister descriptions the registers for the low pin count (lpc) port are divided into two sets: standard geodelink device (gld) msrs (shared with divil, see section 6.6.1 on page 317.) lpc specific msrs the msrs are accessed via the rdmsr and wrmsr pro- cessor instructions. the msr address is derived from the perspective of the cpu core. see section 4.2 "msr addressing" on page 59 for more details. all msrs are 64 bits, however, the lpc specific msrs are called out as 32 bits. the lpc module treats writes to the upper 32 bits (i.e., bits [63:32] ) of the 64-bit msrs as don?t cares and always returns 0 on these bits. the lpc specific msrs are summarized in table 6-54. the reference column in the summary table points to the page where the register maps and bit descriptions are listed. 6.14.1 lpc specific msrs the lpc controller uses the msr_lpc_eaddr and msr_lpc_ estat to record the indicated information associated with any given lpc bus error. the recorded information can not be cleared or modified. simultaneous with this recording, an error event is sent to the divil gld_msr_error (msr 51400003h). if enabled at the divil gld_msr_error, any lpc error event is recorded with a flag. this flag can be cleared. the status of this flag shoul d be used to determine if there is an outstanding error associated with the two msrs below. 6.14.1.1 lpc address error (lpc_eaddr) table 6-54. lpc specific msrs summary msr address type register name reset value reference 5140004ch ro lpc address error (lpc_eaddr) 00000000h page 435 5140004dh ro lpc error status (lpc_estat) 00000000h page 435 5140004eh r/w lpc serial irq control (lpc_sirq) 00000000h page 435 5140004fh r/w lpc reserved (lpc_rsvd) 00000000h page 435 msr address 5140004ch ty p e r o reset value 00000000h lpc_eaddr register map 313029282726252423222120191817161514131211109876543210 lpc_err_addr lpc_eaddr bit descriptions bit name description 31:0 lpc_err_addr lpc error address. when an error occurs, this regist er captures the associated 32-bit address. 436 amd geode? cs5535 companion device data book low pin count register descriptions 31506b 6.14.1.2 lpc error status (lpc_estat) 6.14.1.3 lpc serial irq control (lpc_sirq) msr address 5140004dh ty p e r o reset value 00000000h lpc_estat register map 313029282726252423222120191817161514131211109876543210 rsvd timeout dma write memory estat bit descriptions bit name description 31:4 rsvd reserved. reads as 0. 3timeout timeout. if set, indicates an lpc error was caused by a timeout. 2dma dma. if set, indicates an lpc error occurred during a dma transaction. 1write write. if set, indicates an lpc error occurred during an lpc write transaction. 0memory memory. if set, indicates an lpc error occurred during an lpc memory transaction. msr address 5140004eh ty p e r / w reset value 00000000h lpc_sirq register map 313029282726252423222120191817161514131211109876543210 invert[15:0] rsvd sirq_en sirq_mode irq_frame start _fpw amd geode? cs5535 companion device data book 437 low pin count register descriptions 31506b 6.14.1.4 lpc reserved (lpc_rsvd) lpc_sirq bit descriptions bit name description 31:16 invert[15:0] invert bits 15 through 0. each invert[x] bit corresponds to an irq[x] bit. when a given x bit is 1, the corresponding serial irq input is assumed active low. active low inputs are inverted and presented internally as active high inputs. 15:8 rsvd reserved. write as 0. 7 sirq_en serial irq enable. 0: disable; 1: enable 6 sirq_mode serial irq interface mode. 0: continuous (idle); 1: quiet (active) 5:2 irq_frame irq data frames. number of frames. 0000: 17. 0100: 21. 1000: 25. 1100: 29. 0001: 18. 0101: 22. 1001: 26 . 1101: 30. 0010: 19. 0110: 23. 1010: 27. 1110: 31. 0011: 20. 0111: 24. 1011: 28. 1111: 32. 1:0 start_fpw start frame pulse width . sets the start frame pulse width, specified by the number of clocks. 00: 4 clocks. 10: 8 clocks. 01: 6 clocks. 11: reserved. msr address 5140004fh ty p e r / w reset value 00000000h lpc_rsvd register map 313029282726252423222120191817161514131211109876543210 rsvd lpc_rsvd bit descriptions bit name description 31:0 rsvd reserved. reads return 0. writes have no effect. 438 amd geode? cs5535 companion device data book real-time clock register descriptions 31506b 6.15 real-time clock register descriptions the registers for the real-time clock (rtc) are divided into three sets: standard geodelink device (gld) msrs (shared with divil, see section 6.6.1 on page 317.) rtc specific msrs rtc native registers the msrs are accessed via the rdmsr and wrmsr pro- cessor instructions. the msr address is derived from the perspective of the cpu core. see section 4.2 "msr addressing" on page 59 for more details. all msrs are 64 bits, however, the rtc specific msrs (summarized in table 6-55) are called out as 8 bits. the rtc module treats writes to the upper 56 bits (i.e., bits [63:8]) of the 64-bit msrs as don?t cares and always returns 0 on these bits. the native registers associated with the rtc module are summarized in table 6-56 and are accessed as i/o addresses. the reference column in the summary tables point to the page where the register maps and bit descriptions are listed. table 6-55. rtc specific msrs summary msr address type register name reset value reference 51400054h r/w rtc ram lock (rtc_ram_lock) 00h page 439 51400055h r/w rtc date of month alarm offset (rtc_doma_offset) 00h page 440 51400056h r/w rtc month alarm offset (rtc_mona_offset) 00h page 440 51400057h r/w rtc century offset (rtc_cen_offset) 00h page 441 table 6-56. rtc native registers summary i/o address type width (bits) register name reset value reference 00h r/w 8 seconds (rtc_sec) 00h page 441 01h r/w 8 seconds alarm (rtc_seca) 00h page 442 02h r/w 8 minutes (rtc_min) 00h page 442 03h r/w 8 minutes alarm (rtc_mina) 00h page 442 04h r/w 8 hours (rtc_hr) 00h page 443 05h r/w 8 hours alarm 00h page 443 06h r/w 8 day of week (rtc_dow) 00h page 443 07h r/w 8 day of month (rtc_dom) 00h page 444 08h r/w 8 month (rtc_month) 00h page 444 09h r/w 8 year (rtc_year) 00h page 444 0ah r/w 8 rtc control register a (rtc_cra) 20h page 445 0bh r/w 8 rtc control register b (rtc_crb) 00h page 446 0ch ro 8 rtc control register c (rtc_crc) 00h page 447 0dh ro 8 rtc control register d (rtc_crd) 00h page 448 programmable (note 1) note 1. register location is programmable (through the msr registers) and overlay onto the lower ram space. r/w 8 date of month alarm (rtc_doma) 00h page 448 programmable (note 1) r/w 8 month alarm (rtc_mona) 00h page 449 programmable (note 1) r/w 8 century (rtc_cen) 00h page 449 amd geode? cs5535 companion device data book 439 real-time clock register descriptions 31506b 6.15.1 rtc specific msrs 6.15.1.1 rtc ram lock (rtc_ram_lock) when a non-reserved bit is set to 1, it can only be cleared by hardware reset. msr address 51400054h ty p e r / w reset value 00h rtc_ram_lock register map 76 5 43210 blk_stdram blk_ram_wr blk_xram_wr blk_xram_rd blk_xram rsvd rtc_ram_lock bit descriptions bit name description 7 blk_stdram block standard ram. 0: no effect on standard ram access (default). 1: read and write to locations 38h-3fh of the standard ram are blocked, writes ignored, and reads return ffh. 6 blk_ram_wr block ram write. 0: no effect on ram access (default). 1: write to ram (standard and extended) are ignored. 5 blk_xram_wr block extended ram write. this bit controls write to bytes 00h-1fh of the extended ram. 0: no effect on extended ram access (default). 1: writes to byte 00h-1fh of the extended ram are ignored. 4 blk_xram_rd block extended ram read . this bit controls read from bytes 00h-1fh of the extended ram. 0: no effect on extended ram access (default). 1: reads from byte 00h-1fh of the extended ram are ignored. 3 blk_xram block extended ram. this bit controls access to the extended ram 128 bytes. 0: no effect on extended ram access (default). 1: read and write to the extended ram are blocked; writes are ignored and reads return ffh. 2:0 rsvd reserved. write as 0. 440 amd geode? cs5535 companion device data book real-time clock register descriptions 31506b 6.15.1.2 rtc date of month al arm offset (rtc_doma_offset) 6.15.1.3 rtc month alarm o ffset (rtc_mona_offset) msr address 51400055h ty p e r / w reset value 00h rtc_doma_offset register map 76543210 rsvd doma_ofst rtc_doma_offset bit descriptions bit name description 7 rsvd reserved. write as 0. 6:0 doma_ofst date of month alarm re gister offset value. this register sets the location in ram space of the date of month alarm register. this register must be programmed after a hardware reset, otherwise the day of month alarm register will be on top of other ram data. it is programmed as an offset fr om 0. reset to 00h by hardware reset. msr address 51400056h ty p e r / w reset value 00h rtc_mona_offset register map 76543210 rsvd mona_ofst rtc_mona_offset bit descriptions bit name description 7 rsvd reserved. write as 0. 6:0 mona_ofst month alarm register offset value . this register sets the location in ram space of the month alarm register. this register mu st be programmed after a hardware reset, otherwise the month alarm regi ster will be on top of other ram data. it is programmed as an offset from 0. reset to 00h by hardware reset. amd geode? cs5535 companion device data book 441 real-time clock register descriptions 31506b 6.15.1.4 rtc century o ffset (rtc_cen_offset) 6.15.2 rtc native registers 6.15.2.1 seconds (rtc_sec) msr address 51400057h ty p e r / w reset value 00h rtc_cen_offset register map 76543210 rsvd cen_ofst rtc_cen_offset bit descriptions bit name description 7 rsvd reserved. write as 0. 6:0 cen_osft century register offset value . this register sets the location in ram space of the century register. this register must be programmed after a hardware reset, otherwise the century register will be on top of other ram data. it is programmed as an offset from 0. reset to 00h by hardware reset. i/o address 00h ty p e r / w reset value 00h rtc_sec register map 76543210 sec_data rtc_sec bit descriptions bit name description 7:0 sec_data seconds data. values may be 00 to 59 in bcd format or 00 to 3b in binary format. reset by v pp power-up. 442 amd geode? cs5535 companion device data book real-time clock register descriptions 31506b 6.15.2.2 seconds alarm (rtc_seca) 6.15.2.3 minutes (rtc_min) 6.15.2.4 minutes alarm (rtc_mina) i/o address 01h ty p e r / w reset value 00h rtc_seca register map 76543210 seca_data rtc_seca bit descriptions bit name description 7:0 seca_data seconds alarm data. values may be 00 to 59 in bcd format or 00 to 3b in binary for- mat. when bits 7 and 6 are both set to one, an unconditional match is selected. reset by v pp power-up. i/o address 02h ty p e r / w reset value 00h rtc_min register map 76543210 min_data rtc_min bit descriptions bit name description 7:0 min_data minutes data. values may be 00 to 59 in bcd format or 00 to 3b in binary format. reset by v pp power-up. i/o address 03h ty p e r / w reset value 00h rtc_mina register map 76543210 mina_data rtc_mina bit descriptions bit name description 7:0 mina_data minutes alarm data. values may be 00 to 59 in bcd format or 00 to 3b in binary for- mat. when bits 7 and 6 are both set to one, an unconditional match is selected. reset by v pp power-up. amd geode? cs5535 companion device data book 443 real-time clock register descriptions 31506b 6.15.2.5 hours (rtc_hr) 6.15.2.6 hours alarm 6.15.2.7 day of week (rtc_dow) i/o address 04h ty p e r / w reset value 00h rtc_hr register map 76543210 hr_data rtc_hr bit descriptions bit name description 7:0 hr_data hours data. for 12-hour mode, values can be 01 to 12 (am) and 81 to 92 (pm) in bcd format, or 01 to 0c (am) and 81 to 8c (pm) in binary format. for 24-hour mode, values can be 0 to 23 in bcd format or 00 to 17 in binary format. reset by v pp power-up. i/o address 05h ty p e r / w reset value 00h rtc_hra register map 76543210 hra_data rtc_hra bit descriptions bit name description 7:0 hra_data hours alarm data. for 12-hour mode, values can be 01 to 12 (am) and 81 to 92 (pm) in bcd format, or 01 to 0c (am) and 81 to 8c (pm) in binary format. for 24-hour mode, values can be 0 to 23 in bcd format or 00 to 17 in binary format. when bits 7 and 6 are both set to one, unconditional match is selected. reset by v pp power-up. i/o address 06h ty p e r / w reset value 00h rtc_dow register map 76543210 dow_data rtc_dow bit descriptions bit name description 7:0 dow_data day of week data. values may be 01 to 07 in bcd format or 01 to 07 in binary format. reset by v pp power-up. 444 amd geode? cs5535 companion device data book real-time clock register descriptions 31506b 6.15.2.8 day of month (rtc_dom) 6.15.2.9 month (rtc_month) 6.15.2.10 year (rtc_year) i/o address 07h ty p e r / w reset value 00h rtc_dom register map 76543210 dom_data rtc_dom bit descriptions bit name description 7:0 dow_data day of month data. values may be 01 to 31 in bcd format or 01 to 0f in binary for- mat. reset by v pp power-up. i/o address 08h ty p e r / w reset value 00h rtc_mon register map 76543210 mon_data rtc_mon bit descriptions bit name description 7:0 mon_data month data. values may be 01 to 12 in bcd format or 01 to 0c in binary format. reset by v pp power-up. i/o address 09h ty p e r / w reset value 00h rtc_yr register map 76543210 yr_data rtc_yr bit descriptions bit name description 7:0 yr_data year data. this register holds the two least significant digits of a four-digit year. for example, if the year is 2007, this register would contain the equivalent of ?07?. values may be 00 to 99 in bcd format or 00 to 63 in binary format. reset by v pp power-up. amd geode? cs5535 companion device data book 445 real-time clock register descriptions 31506b 6.15.2.11 rtc control register a (rtc_cra) this register controls test selection among other functi ons. this register cannot be written before reading bit 7 of rtc_crd (vrt bit). i/o address 0ah ty p e r / w reset value 20h rtc_cra register map 76543210 uip div_chn_ctl pir_sel rtc_cra bit descriptions bit name description 7 uip (ro) update in progress (read only). this ro bit is not affected by reset. this bit reads 0 when bit 7 of rtc_crb is 1. 0: timing registers not updated within 244 s. 1: timing registers updated within 244 s. 6:4 div_chn_ctl divider chain control. these r/w bits control the confi guration of the divider chain for timing generation and register bank selection. they are cleared to 010 as long as bit 7 of rtc_crd (vrt bit) is 0. 00x: oscillator disabled. 10x: test. 010: normal operation. 11x: divider chain reset. 011: test. 3:0 pir_sel periodic interrupt rate select : these r/w bits select one of fifteen output taps from the clock divider chain to control the rate of the periodic interrupt. they are cleared to 000 as long as bit 7 of rtc_crd (vrt bit) is 0. 0000: no interrupts 1000: 3.906250 ms 0001: 3.906250 ms 1001: 7.812500 ms 0010: 7.812500 ms 1010: 15.625000 ms 0011: 0.122070 ms 1011: 31.250000 ms 0100: 0.244141 ms 1100: 62.500000 ms 0101: 0.488281 ms 1101: 125.000000 ms 0110: 0.976562 ms 1110: 250.000000 ms 0111: 1.953125 ms 1111: 500.000000 ms 446 amd geode? cs5535 companion device data book real-time clock register descriptions 31506b 6.15.2.12 rtc control register b (rtc_crb) i/o address 0bh ty p e r / w reset value 00h rtc_crb register map 76543210 set_mode pi_en ai_en uei_en rsvd data_mode hr_mode day_save rtc_crb bit descriptions bit name description 7 set_mode set mode. this bit is reset at v pp power-up reset only. 0: timing updates occur normally 1: user copy of time is ?frozen?, allowing the time registers to be accessed whether or not an update occurs. 6pi_en periodic interrupts enable. bits [3:0] of rtc_cra (pir_sel ) determine the rate at which this interrupt is generated. it is cl eared to 0 on an rtc reset (i.e., hardware reset) or when the rtc is disable. 0: disable. 1: enable. 5ai_en alarm interrupt enable. this interrupt is generated immediately after a time update in which the seconds, minutes, hours, date and month time equal their respective alarm counterparts. it is cleared to 0 as long as bit 7 of rtc_crd (vrt bit) reads 0. 0: disable. 1: enable. 4uei_en update ended interrupts enable. this interrupt is generated when an update occurs. it is cleared to 0 on an rtc reset (i.e., hardware reset) or when the rtc is disabled. 0: disable. 1: enable. 3 rsvd reserved. this bit is defined as ?square wave enable? by the mc146818 and is not supported by the rtc. this bit is always read as 0. 2data_mode data mode. selects data mode. this bit is reset at v pp power-up reset only. 0: bcd format. 1: binary format. 1 hr_mode hour mode. selects hour mode. this bit is reset at v pp power-up reset only. 0: 12-hour format. 1: 24-hour format. 0day_save daylight saving . enables/disables daylight savings mode. this bit is reset at v pp power-up reset only. 0: disable. 1: enable. in the spring, time advances from 1:59:59 am to 3:00:00 am on the first sunday in april. in the fall, time returns from 1:59:59 am to 1:00:00 am on the last sunday in october. amd geode? cs5535 companion device data book 447 real-time clock register descriptions 31506b 6.15.2.13 rtc control register c (rtc_crc) i/o address 0ch ty p e r o reset value 00h rtc_crc register map 76543210 irqf pf af uf rsvd rtc_crc bit descriptions bit name description 7irqf (ro) irq flag (read only). this ro bit mirrors the value on the interrupt output signal. when interrupt is active, irqf is 1. reading th is register clears this bit (and deactivates the interrupt pin) and clears the flag bits uf, af, and pf. 0: irq inactive. 1: logic equation is true: ((uie and uf ) or (aie and af) or (pie and pf)). 6pf (ro) periodic interrupts flag (read only). this ro bit is cleared to 0 on an rtc reset (i.e., hardware reset) or when the rtc is disabled. in addition, this bit is cleared to 0 when this register is read. 0: no transition occurred on the selected tap since the last read. 1: transition occurred on the selected tap of the divider chain. 5af (ro) alarm interrupt flag (read only). this ro bit is cleared to 0 as long as bit 7 of rtc_crd (vrt bit) is 0. in addition, this bit is cleared to 0 when this register is read. 0: no alarm detected since the last read. 1: alarm condition detected. 4uf (ro) update ended interrupt s flag (read only). this ro bit is cleared to 0 on an rtc reset (i.e., hardware reset) or when the rtc is disabled. in addition, this bit is cleared to 0 when this register is read. 0: no update occurred since the last read. 1: time registers updated. 3:0 rsvd (ro) reserved (read only). reads as 0. 448 amd geode? cs5535 companion device data book real-time clock register descriptions 31506b 6.15.2.14 rtc control register d (rtc_crd) 6.15.2.15 date of month alarm (rtc_doma) i/o address 0dh ty p e r o reset value 00h rtc_crd register map 76543210 vrt rsvd rtc_crd bit descriptions bit name description 7vrt (ro) valid ram and time (read only). this bit senses the voltage that feeds the rtc (vsb or vbat) and indicates whether or not it was too low since the last time this bit was read. if it was too low, the rtc conten ts (time/calendar regi sters and cmos ram) is not valid. it is clear on v pp power-up. 0: the voltage that feeds the rtc was too low. 1: rtc contents (time/calendar registers and cmos ram) valid. 6:0 rsvd (ro) reserved (read only). reads as 0. i/o address programmable ty p e r / w reset value 00h rtc_doma register map 76543210 doma_data rtc_doma bit descriptions bit name description 7:0 doma_data date of month alarm data. values may be 01 to 31 in bcd format or 01 to 1f in binary format. when bits 7 and 6 are both set to one, an unconditional match is selected (default ). reset by v pp power-up. amd geode? cs5535 companion device data book 449 real-time clock register descriptions 31506b 6.15.2.16 month alarm (rtc_mona) 6.15.2.17 century (rtc_cen) i/o address programmable ty p e r / w reset value 00h rtc_mona register map 76543210 mona_data rtc_mona bit descriptions bit name description 7:0 mona_data month alarm data. values may be 01 to 12 in bcd format or 01 to 0c in binary format. when bits 7 and 6 are both set to one, an unconditional match is selected (default). reset by v pp power-up. i/o address programmable ty p e r / w reset value 00h rtc_cen register map 76543210 cen_data rtc_cen bit descriptions bit name description 7:0 cen_data century data. this register holds the two most significant digits of a four-digit year. for example, if the year is 2008, this register would contain the equivalent of ?20?. values may be 00 to 99 in bcd format or 00 to 63 in binary format. reset by v pp power-up. 450 amd geode? cs5535 companion device data book gpio subsystem register descriptions 31506b 6.16 gpio subsystem r egister descriptions the registers for the general purpose input output (gpio) are divided into two sets: standard geodelink device (gld) msrs (shared with divil, see section 6.6.1 on page 317.) gpio native registers the msrs are accessed via the rdmsr and wrmsr pro- cessor instructions. the msr address is derived from the perspective of the cpu core. see section 4.2 "msr addressing" on page 59 for more details. the gpio native register s are accessed via a base address register, msr_lbar_gpio (msr 5140000ch), as i/o offsets. (see secti on 6.6.2.5 on page 328 for bit descriptions of the base address register.) the native registers associated with gpio configuration are broadly divided into three categories: 1) gpio low/high bank feature bit registers. these registers (summarized in table 6-57) control basic gpio features. the feature bit registers use the atomic programming model except where noted. see section 6.16.1 "atomic bit programming model" on page 454 for details. 2) input conditioning function registers. these registers (summarized in table 6-58 on page 452) are associated with the eight digital filter/event counter pairs that can be shared with the 32 gpios. these registers are not based on the atomic bit pro- gramming model. 3) gpio interrupt and pme mapper registers. these registers (summarized in table 6-59 on page 453) are used for mapping any gpio to one of the eight pic-level interrupts or to one of the eight pme (power management event) inputs. the reference column in the summary tables point to the page where the detailed register maps and bit descriptions are listed. the low bank refers to gpio[15:0] while the high bank refers to gpio[31:16] . note: all register bits dea ling with gpio31, gpio30, gpio29 and gpio23 are reserved. table 6-57. gpio low/high bank feature bit registers summary gpio i/o offset type width (bits) register name reset value reference gpio low bank feature bit registers 00h r/w 32 gpio low bank output value (gpiol_out_val) ffff0000h page 456 04h r/w 32 gpio low bank output enab le (gpiol_out_en) ffff0000h page 456 08h r/w 32 gpio low bank output open-drain enable (gpiol_out_od_en) ffff0000h page 457 0ch r/w 32 gpio low bank output invert enable (gpiol_out_invrt_en) ffff0000h page 457 10h r/w 32 gpio low bank output auxiliary 1 select (gpiol_out_aux1_sel) ffff0000h page 458 14h r/w 32 gpio low bank output auxiliary 2 select (gpiol_out_aux2_sel) ffff0000h page 459 18h r/w 32 gpio low bank pull-up enable (gpiol_pu_en) 1000efffh page 459 1ch r/w 32 gpio low bank pull-down enable (gpiol_pd_en) efff1000h page 460 20h r/w 32 gpio low bank input enable (gpiol_in_en) ffff0000h page 460 24h r/w 32 gpio low bank input invert enable (gpiol_in_invrt_en) ffff0000h page 461 28h r/w 32 gpio low bank input filter enable (gpiol_in_fltr_en) ffff0000h page 461 2ch r/w 32 gpio low bank input event count enable (gpiol_in_evntcnt_en) ffff0000h page 462 30h (note 1) ro 32 gpio low bank read back (gpiol_read_back) 00000000h page 467 34h r/w 32 gpio low bank input auxiliary 1 select (gpiol_in_aux1_sel) ffff0000h page 463 amd geode? cs5535 companion device data book 451 gpio subsystem register descriptions 31506b 38h r/w 32 gpio low bank events enable (gpiol_evnt_en) ffff0000h page 463 3ch (note 1) r/w 32 gpio low bank lock enable (gpiol_lock_en) 00000000h page 469 40h r/w 32 gpio low bank input positive edge enable (gpiol_in_posedge_en) ffff0000h page 464 44h r/w 32 gpio low bank input negative edge enable (gpiol_in_negedge_en) ffff0000h page 464 48h r/w 32 gpio low bank input positive edge status (gpiol_in_posedge_sts) ffff0000h page 465 4ch r/w 32 gpio low bank input negative edge status (gpiol_in_negedge_sts) ffff0000h page 466 gpio high bank feature bit registers 80h r/w 32 gpio high bank output valu e (gpioh_out_val) ffff0000h page 456 84h r/w 32 gpio high bank output enab le (gpioh_out_en) ffff0000h page 456 88h r/w 32 gpio high bank output open-drain enable (gpioh_out_od_en) ffff0000h page 457 8ch r/w 32 gpio high bank output invert enable (gpioh_out_invrt_en) ffff0000h page 457 90h r/w 32 gpio high bank output auxiliary 1 select (gpioh_out_aux1_sel) ffff0000h page 458 94h r/w 32 gpio high bank output auxiliary 2 select (gpioh_out_aux2_sel) ffff0000h page 459 98h r/w 32 gpio high bank pull-up enable (gpioh_pu_en) 0000ffffh page 459 9ch r/w 32 gpio high bank pull-down enable (gpioh_pd_en) ffff0000h page 460 a0h r/w 32 gpio high bank input enab le (gpioh_in_en) efff1000h page 460 a4h r/w 32 gpio high bank input invert enable (gpioh_in_inv_en) ffff0000h page 461 a8h r/w 32 gpio high bank input filter enable (gpioh_in_flter_en) ffff0000h page 461 ach r/w 32 gpio high bank input event count enable (gpioh_in_evntcnt_en) ffff0000h page 462 b0h (note 1) ro 32 gpio high bank read back (gpioh_read_back) 00000000h page 468 b4h r/w 32 gpio high bank input auxiliary 1 select (gpioh_in_aux1_sel) efff1000h page 463 b8h r/w 32 gpio high bank events enable (gpioh_evnt_en) ffff0000h page 463 bch (note 1) r/w 32 gpio high bank lock enable (gpioh_lock_en) 00000000h page 470 c0h r/w 32 gpio high bank input positive edge enable (gpioh_in_posedge_en) ffff0000h page 464 c4h r/w 32 gpio high bank input negative edge enable (gpioh_in_negedge_en) ffff0000h page 464 table 6-57. gpio low/high bank feature bit registers summary (continued) gpio i/o offset type width (bits) register name reset value reference 452 amd geode? cs5535 companion device data book gpio subsystem register descriptions 31506b c8h r/w 32 gpio high bank input positive edge status (gpioh_in_posedge_sts) ffff0000h page 465 cch r/w 32 gpio high bank input negative edge status (gpioh_in_negedge_sts) ffff0000h page 466 note 1. the gpio[x]_read_back and gpio[x]_lock_en regi sters are not based on the atomic programming model (i.e., only one bit for control as opposed to two bits). see section 6.16.1 "atomic bit programming model" on page 454 for more information on atomic programming. table 6-58. gpio input conditioni ng function registers summary gpio i/o offset type width (bits) register name reset value reference 50h r/w 16 gpio filter 0 amount (gpio_fltr0_amnt) 0000h page 471 52h r/w 16 gpio filter 0 count (gpio_fltr0_cnt) 0000h page 472 54h r/w 16 gpio event counter 0 (gpio_evntcnt0) 0000h page 473 56h r/w 16 gpio event counter 0 compare value (gpio_evntcnt0_comp) 0000h page 474 58h r/w 16 gpio filter 1 amount (gpio_fltr1_amnt) 0000h page 471 5ah r/w 16 gpio filter 1 count (gpio_fltr1_cnt) 0000h page 472 5ch r/w 16 gpio event counter 1 (gpio_evntcnt1) 0000h page 473 5eh r/w 16 gpio event counter 1 compare value (gpio_evntcnt1_comp) 0000h page 474 60h r/w 16 gpio filter 2 amount (gpio_fltr2_amnt) 0000h page 471 62h r/w 16 gpio filter 2 count (gpio_fltr2_cnt) 0000h page 472 64h r/w 16 gpio event counter 2 (gpio_evntcnt2) 0000h page 473 66h r/w 16 gpio event counter 2 compare value (gpio_evntcnt2_comp) 0000h page 474 68h r/w 16 gpio filter 3 amount (gpio_fltr3_amnt) 0000h page 471 6ah r/w 16 gpio filter 3 count (gpio_fltr3_cnt) 0000h page 472 6ch r/w 16 gpio event counter 3 (gpio_evntcnt3) 0000h page 473 6eh r/w 16 gpio event counter 3 compare value (gpio_evntcnt3_comp) 0000h page 474 70h r/w 16 gpio filter 4 amount (gpio_fltr4_amnt) 0000h page 471 72h r/w 16 gpio filter 4 count (gpio_fltr4_cnt) 0000h page 472 74h r/w 16 gpio event counter 4 (gpio_evntcnt4) 0000h page 473 76h r/w 16 gpio event counter 4 compare value (gpio_evntcnt4_comp) 0000h page 474 78h r/w 16 gpio filter 5 amount (gpio_fltr5_amnt) 0000h page 471 7ah r/w 16 gpio filter 5 count (gpio_fltr5_cnt) 0000h page 472 7ch r/w 16 gpio event counter 5 (gpio_evntcnt5) 0000h page 473 7eh r/w 16 gpio event counter 5 compare value (gpio_evntcnt5_comp) 0000h page 474 table 6-57. gpio low/high bank feature bit registers summary (continued) gpio i/o offset type width (bits) register name reset value reference amd geode? cs5535 companion device data book 453 gpio subsystem register descriptions 31506b d0h r/w 16 gpio filter 6 amount (gpio_fltr6_amnt) 0000h page 471 d2h r/w 16 gpio filter 6 count (gpio_fltr6_cnt) 0000h page 472 d4h r/w 16 gpio event counter 6 (gpio_evntcnt6) 0000h page 473 d6h r/w 16 gpio event counter 6 compare value (gpio_evntcnt6_comp) 0000h page 474 d8h r/w 16 gpio filter 7 amount (gpio_fltr7_amnt) 0000h page 471 dah r/w 16 gpio filter 7 count (gpio_fltr7_cnt) 0000h page 472 dch r/w 16 gpio event counter 7 (gpio_evntcnt7) 0000h page 473 deh r/w 16 gpio event counter 7 compare value (gpio_evntcnt7_comp) 0000h page 474 f0h r/w 8 gpio filter/event pair 0 selection (gpio_fe0_sel) 00h page 475 f1h r/w 8 gpio filter/event pair 1 selection (gpio_fe1_sel) 00h page 475 f2h r/w 8 gpio filter/event pair 2 selection (gpio_fe2_sel) 00h page 475 f3h r/w 8 gpio filter/event pair 3 selection (gpio_fe3_sel) 00h page 475 f4h r/w 8 gpio filter/event pair 4 selection (gpio_fe4_sel) 00h page 475 f5h r/w 8 gpio filter/event pair 5 selection (gpio_fe5_sel) 00h page 475 f6h r/w 8 gpio filter/event pair 6 selection (gpio_fe6_sel) 00h page 475 f7h r/w 8 gpio filter/event pair 7 selection (gpio_fe7_sel) 00h page 475 f8h r/w 32 gpio low bank event counter decrement (gpiol_evntcnt_dec) 00000000h page 477 fch r/w 32 gpio high bank event counter decrement (gpiol_evntcnt_dec) 00000000h page 478 table 6-59. gpio interrupt and pme mapper registers summary gpio address type width (bits) register name reset value reference e0h r/w 32 gpio mapper x (gpio_map_x) 00000000h page 482 e4h r/w 32 gpio mapper y (gpio_map_y) 00000000h page 481 e8h r/w 32 gpio mapper z (gpio_map_z) 00000000h page 480 ech r/w 32 gpio mapper w (gpio_map_w) 00000000h page 479 table 6-58. gpio input conditioning function registers summary (continued) gpio i/o offset type width (bits) register name reset value reference 454 amd geode? cs5535 companion device data book gpio subsystem register descriptions 31506b 6.16.1 atomic bit programming model the registers in section 6.16.2 "gpio low/ high bank feature bit registers", starti ng on page 456, that are referred to as ?atomic? all follow the same programming m odel (i.e., work exactly the same way) but each controls a different gpio fea- ture. two data bits are used to control each gpio feature bit, each pair of bits operate in an exclusive-or pattern. refer to section 5.15.2 "register strategy" on page 161 for further details. the low bank registers control progra mming of gpio15 through gpio0 and t he high bank registers program gpio31 through gpio16. the tables that follow provide the register/bit fo rmats for the low and high bank gpio feature configura- tion registers. note: all register bits dealing with gpio31, gpio30, gpio29 and gpio23 are reserved . table 6-60. low bank atomic register map 313029282726252423222120191817161514131211109876543210 gpio15 gpio14 gpio13 gpio12 gpio11 gpio10 gpio9 gpio8 gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 gpio15 gpio14 gpio13 gpio12 gpio11 gpio10 gpio9 gpio8 gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 table 6-61. low bank atomic bit descriptions bit name description 31,15 gpio15 gpio15 feature. 00: no change. 01: feature bit = 1. 10: feature bit = 0. 11: no change. 30,14 gpio14 gpio14 feature. see bits [31,15] for decode. 29,13 gpio13 gpio13 feature. see bits [31,15] for decode. 28,12 gpio12 gpio12 feature. see bits [31,15] for decode. 27,11 gpio11 gpio11 feature. see bits [31,15] for decode. 26,10 gpio10 gpio10 feature. see bits [31,15] for decode. 25,9 gpio9 gpio9 feature. see bits [31,15] for decode. 24,8 gpio8 gpio8 feature. see bits [31,15] for decode. 23,7 gpio7 gpio7 feature. see bits [31,15] for decode. 22,6 gpio6 gpio6 feature. see bits [31,15] for decode. 21,5 gpio5 gpio5 feature. see bits [31,15] for decode. 20,4 gpio4 gpio4 feature. see bits [31,15] for decode. 19,3 gpio3 gpio3 feature. see bits [31,15] for decode. 18,2 gpio2 gpio2 feature. see bits [31,15] for decode. 17,1 gpio1 gpio1 feature. see bits [31,15] for decode. 16,0 gpio0 gpio0 feature. see bits [31,15] for decode. amd geode? cs5535 companion device data book 455 gpio subsystem register descriptions 31506b table 6-62. high bank atomic register map format 313029282726252423222120191817161514131211109876543210 rsvd rsvd rsvd gpio28 gpio27 gpio26 gpio25 gpio24 rsvd gpio22 gpio21 gpio20 gpio19 gpio18 gpio17 gpio16 rsvd rsvd rsvd gpio28 gpio27 gpio26 gpio25 gpio24 rsvd gpio22 gpio21 gpio20 gpio19 gpio18 gpio17 gpio16 table 6-63. high bank atomic bit descriptions format bit name description 31,15 rsvd reserved. write as 00. 30,14 rsvd reserved. write as 00. 29,13 rsvd reserved. write as 00. 28,12 gpio28 gpio28 feature. 00: no change. 01: feature bit = 1. 10: feature bit = 0. 11: no change. 27,11 gpio27 gpio27 feature. see bits [28,12] for decode. 26,10 gpio26 gpio26 feature. see bits [28,12] for decode. 25,9 gpio25 gpio25 feature. see bits [28,12] for decode. 24,8 gpio24 gpio24 feature. see bits [28,12] for decode. 23,7 rsvd reserved. write as 00. 22,6 gpio22 gpio22 feature. see bits [28,12] for decode. 21,5 gpio21 gpio21 feature. see bits [28,12] for decode. 20,4 gpio20 gpio20 feature. see bits [28,12] for decode. 19,3 gpio19 gpio19 feature. see bits [28,12] for decode. 18,2 gpio18 gpio18 feature. see bits [28,12] for decode. 17,1 gpio17 gpio17 feature. see bits [28,12] for decode. 16,0 gpio16 gpio16 feature. see bits [28,12] for decode. 456 amd geode? cs5535 companion device data book gpio subsystem register descriptions 31506b 6.16.2 gpio low/high bank feature bit registers 6.16.2.1 gpio output va lue (gpio[x]_out_val) these registers control the output value fo r the low (gpio[15:0]) and high (gpio[31 :16]) banks of gpios. if the feature bit is high, the output value = 1. if the featur e bit is low, the output value = 0. the re set value forces all the output values to be initially set to 0. (these registers use atomic prog ramming, see section 6.16.1 on page 454 for details.) if out_aux1 (gpio i/o offset 10h/90h) and/or out_aux2 (gpio i/o offset 14h/94h) are selected, then their value over- rides the out_val settings. see table 3-8 "gpio options" on page 47 for aux programming details. gpio low bank output value (gpiol_out_val) gpio high bank output value (gpioh_out_val) 6.16.2.2 gpio/out_aux output enable (gpio[x]_out_en) these registers control the output enable for the low (gpio[15:0]) and high (gpio[31:16]) banks of gpios. if the feature bit high, the output is enabled. if the feature bit is low, the outp ut is disabled. the reset value forces all the outputs to be di s- abled. (these registers use atomic programming, see section 6.16.1 on page 454 for details.) gpio low bank output enable (gpiol_out_en) gpio high bank output enable (gpioh_out_en) gpio i/o offset 00h ty p e r / w reset value ffff0000h gpio i/o offset 80h ty p e r / w reset value ffff0000h gpiol_out_val register map 313029282726252423222120191817161514131211109876543210 out_val_15 out_val_14 out_val_13 out_val_12 out_val_11 out_val_10 out_val_9 out_val_8 out_val_7 out_val_6 out_val_5 out_val_4 out_val_3 out_val_2 out_val_1 out_val_0 out_val_15 out_val_14 out_val_13 out_val_12 out_val_11 out_val_10 out_val_9 out_val_8 out_val_7 out_val_6 out_val_5 out_val_4 out_val_3 out_val_2 out_val_1 out_val_0 gpioh_out_val register map 313029282726252423222120191817161514131211109876543210 rsvd rsvd rsvd out_val_28 out_val_27 out_val_26 out_val_25 out_val_24 rsvd out_val_22 out_val_21 out_val_20 out_val_19 out_val_18 out_val_17 out_val_16 rsvd rsvd rsvd out_val_28 out_val_27 out_val_26 out_val_25 out_val_24 rsvd out_val_22 out_val_21 out_val_20 out_val_19 out_val_18 out_val_17 out_val_16 gpio i/o offset 04h ty p e r / w reset value ffff0000h gpio i/o offset 84h ty p e r / w reset value ffff0000h gpiol_out_en register map 313029282726252423222120191817161514131211109876543210 out_en_15 out_en_14 out_en_13 out_en_12 out_en_11 out_en_10 out_en_9 out_en_8 out_en_7 out_en_6 out_en_5 out_en_4 out_en_3 out_en_2 out_en_1 out_en_0 out_en_15 out_en_14 out_en_13 out_en_12 out_en_11 out_en_10 out_en_9 out_en_8 out_en_7 out_en_6 out_en_5 out_en_4 out_en_3 out_en_2 out_en_1 out_en_0 gpioh_out_en register map 313029282726252423222120191817161514131211109876543210 rsvd rsvd rsvd out_en_28 out_en_27 out_en_26 out_en_25 out_en_24 rsvd out_en_22 out_en_21 out_en_20 out_en_19 out_en_18 out_en_17 out_en_16 rsvd rsvd rsvd out_en_28 out_en_27 out_en_26 out_en_25 out_en_24 rsvd out_en_22 out_en_21 out_en_20 out_en_19 out_en_18 out_en_17 out_en_16 amd geode? cs5535 companion device data book 457 gpio subsystem register descriptions 31506b 6.16.2.3 gpio/out_aux output open-d rain enable (gpio[x]_out_od_en) these registers control the op en-drain enable of the output for the low (g pio[15:0]) and high (gpio[31:16]) banks of gpios. the open-drain is enabled if the feature bit is high. the open-drain is disabled if th e feature bit is low.the reset value forces all open-drains on the outputs to be disabled. (these registers use atomic pr ogramming, see section 6.16.1 on page 454 for details.) gpio low bank output open-drain enable (gpiol_out_od_en) gpio high bank output open-drain enable (gpioh_out_od_en) 6.16.2.4 gpio/out_aux output inver t enable (gpio[x]_out_invrt_en) these registers control the output invert enable for the low (gpio[15:0]) and high (gpio[31 :16]) banks of gpios. the out- put is inverted if the feature bit is high. the output is not inverted if the feature bit is lo w. (these registers use atomic p ro- gramming, see section 6.16.1 on page 454 for details.) gpio low bank output invert enable (gpiol_out_invrt_en) gpio high bank output invert enable (gpioh_out_invrt_en) gpio i/o offset 08h ty p e r / w reset value ffff0000h gpio i/o offset 88h ty p e r / w reset value ffff0000h gpiol_out_od_en register map 313029282726252423222120191817161514131211109876543210 out_od_15 out_od_14 out_od_13 out_od_12 out_od_11 out_od_10 out_od_9 out_od_8 out_od_7 out_od_6 out_od_5 out_od_4 out_od_3 out_od_2 out_od_1 out_od_0 out_od_15 out_od_14 out_od_13 out_od_12 out_od_11 out_od_10 out_od_9 out_od_8 out_od_7 out_od_6 out_od_5 out_od_4 out_od_3 out_od_2 out_od_1 out_od_0 gpioh_out_od_en register map 313029282726252423222120191817161514131211109876543210 rsvd rsvd rsvd out_od_28 out_od_27 out_od_26 out_od_25 out_od_24 rsvd out_od_22 out_od_21 out_od_20 out_od_19 out_od_18 out_od_17 out_od_16 rsvd rsvd rsvd out_od_28 out_od_27 out_od_26 out_od_25 out_od_24 rsvd out_od_22 out_od_21 out_od_20 out_od_19 out_od_18 out_od_17 out_od_16 gpio i/o offset 0ch ty p e r / w reset value ffff0000h gpio i/o offset 8ch ty p e r / w reset value ffff0000h gpiol_out_invrt_en register map 313029282726252423222120191817161514131211109876543210 out_invrt_15 out_invrt_14 out_invrt_13 out_invrt_12 out_invrt_11 out_invrt_10 out_invrt_9 out_invrt_8 out_invrt_7 out_invrt_6 out_invrt_5 out_invrt_4 out_invrt_3 out_invrt_2 out_invrt_1 out_invrt_0 out_invrt_15 out_invrt_14 out_invrt_13 out_invrt_12 out_invrt_11 out_invrt_10 out_invrt_9 out_invrt_8 out_invrt_7 out_invrt_6 out_invrt_5 out_invrt_4 out_invrt_3 out_invrt_2 out_invrt_1 out_invrt_0 gpioh_out_invrt_en register map 313029282726252423222120191817161514131211109876543210 rsvd rsvd rsvd out_invrt_28 out_invrt_27 out_invrt_26 out_invrt_25 out_invrt_24 rsvd out_invrt_22 out_invrt_21 out_invrt_20 out_invrt_19 out_invrt_18 out_invrt_17 out_invrt_16 rsvd rsvd rsvd out_invrt_28 out_invrt_27 out_invrt_26 out_invrt_25 out_invrt_24 rsvd out_invrt_22 out_invrt_21 out_invrt_20 out_invrt_19 out_invrt_18 out_invrt_17 out_invrt_16 458 amd geode? cs5535 companion device data book gpio subsystem register descriptions 31506b 6.16.2.5 gpio output au xiliary 1 select (g pio[x]_out_aux1_sel) these registers select the auxiliary 1 output of the low (gpio[ 15:0]) and high (gpio[31:16]) banks of gpios. auxiliary 1 is selected as the output if the feature bit is high. auxiliary 1 is not selected as the output if the feature bit is low. (these regis- ters use atomic programming, see se ction 6.16.1 on page 454 for details.) if out_aux1 and/or out_aux2 are selected, then their value overrides the out_val (gpio i/o offset 00h/80h) set- tings. see table 3-8 "gpio options" on page 47 for aux programming details. gpio low bank output auxiliary 1 select (gpiol_out_aux1_sel) gpio high bank output auxiliary 1 select (gpioh_out_aux1_sel) gpio i/o offset 10h ty p e r / w reset value ffff0000h gpio i/o offset 90h ty p e r / w reset value ffff0000h gpiol_out_aux1_sel register map 313029282726252423222120191817161514131211109876543210 out_aux1_15 out_aux1_14 out_aux1_13 out_aux1_12 out_aux1_11 out_aux1_10 out_aux1_9 out_aux1_8 out_aux1_7 out_aux1_6 out_aux1_5 out_aux1_4 out_aux1_3 out_aux1_2 out_aux1_1 out_aux1_0 out_aux1_15 out_aux1_14 out_aux1_13 out_aux1_12 out_aux1_11 out_aux1_10 out_aux1_9 out_aux1_8 out_aux1_7 out_aux1_6 out_aux1_5 out_aux1_4 out_aux1_3 out_aux1_2 out_aux1_1 out_aux1_0 gpioh_out_aux1_sel register map 313029282726252423222120191817161514131211109876543210 rsvd rsvd rsvd out_aux1_28 out_aux1_27 out_aux1_26 out_aux1_25 out_aux1_24 rsvd out_aux1_22 out_aux1_21 out_aux1_20 out_aux1_19 out_aux1_18 out_aux1_17 out_aux1_16 rsvd rsvd rsvd out_aux1_28 out_aux1_27 out_aux1_26 out_aux1_25 out_aux1_24 rsvd out_aux1_22 out_aux1_21 out_aux1_20 out_aux1_19 out_aux1_18 out_aux1_17 out_aux1_16 amd geode? cs5535 companion device data book 459 gpio subsystem register descriptions 31506b 6.16.2.6 gpio output au xiliary 2 select (g pio[x]_out_aux2_sel) these registers select the auxiliary 2 output of the low (gpio[ 15:0]) and high (gpio[31:16]) banks of gpios. auxiliary 2 is selected as the output if the feature bit is high. auxiliary 2 is not selected as the output if the feature bit is low. (these regis- ters use atomic programming, see se ction 6.16.1 on page 454 for details.) if out_aux1 and/or out_aux2 are selected, then their value overrides the out_val (gpio i/o offset 00h/80h) set- tings. see table 3-8 "gpio options" on page 47 for aux programming details. gpio low bank output auxiliary 2 select (gpiol_out_aux2_sel) gpio high bank output auxiliary 2 select (gpioh_out_aux2_sel) 6.16.2.7 gpio/aux pull-up enable (gpio[x]_pu_en) these registers control enabling of the pul l-up on the low (gpio[15:0]) and high (gpi o[31:16]) banks of gpios. if the fea- ture bit is high, the pull-up is enabled. if the feature bit is low, the pull-up is disabled. the reset value forces all the pu ll-ups to be disabled. (these registers use atomic prog ramming, see section 6.16.1 on page 454 for details.) gpio low bank pull-up enable (gpiol_pu_en) g pio high bank pull-up enable (gpioh_pu_en) gpio i/o offset 14h ty p e r / w reset value ffff0000h gpio i/o offset 94h ty p e r / w reset value ffff0000h gpiol_out_aux2_sel register map 313029282726252423222120191817161514131211109876543210 out_aux2_15 out_aux2_14 out_aux2_13 out_aux2_12 out_aux2_11 out_aux2_10 out_aux2_9 out_aux2_8 out_aux2_7 out_aux2_6 out_aux2_5 out_aux2_4 out_aux2_3 out_aux2_2 out_aux2_1 out_aux2_0 out_aux2_15 out_aux2_14 out_aux2_13 out_aux2_12 out_aux2_11 out_aux2_10 out_aux2_9 out_aux2_8 out_aux2_7 out_aux2_6 out_aux2_5 out_aux2_4 out_aux2_3 out_aux2_2 out_aux2_1 out_aux2_0 gpioh_out_aux2_sel register map 313029282726252423222120191817161514131211109876543210 rsvd rsvd rsvd out_aux2_28 out_aux2_27 out_aux2_26 out_aux2_25 out_aux2_24 rsvd out_aux2_22 out_aux2_21 out_aux2_20 out_aux2_19 out_aux2_18 out_aux2_17 out_aux2_16 rsvd rsvd rsvd out_aux2_28 out_aux2_27 out_aux2_26 out_aux2_25 out_aux2_24 rsvd out_aux2_22 out_aux2_21 out_aux2_20 out_aux2_19 out_aux2_18 out_aux2_17 out_aux2_16 gpio i/o offset 18h ty p e r / w reset value 1000efffh gpio i/o offset 98h ty p e r / w reset value 0000ffffh gpiol_pu_en register map 313029282726252423222120191817161514131211109876543210 pu_15 pu_14 pu_13 pu_12 pu_11 pu_10 pu_9 pu_8 pu_7 pu_6 pu_5 pu_4 pu_3 pu_2 pu_1 pu_0 pu_15 pu_14 pu_13 pu_12 pu_11 pu_10 pu_9 pu_8 pu_7 pu_6 pu_5 pu_4 pu_3 pu_2 pu_1 pu_0 for bits [6:5], see special disabling rules for t he auto-sense gpios in section 5.15.5.6 on page 165. gpioh_pu_en register map 313029282726252423222120191817161514131211109876543210 rsvd rsvd rsvd pu_28 pu_27 pu_26 pu_25 pu_24 rsvd pu_22 pu_21 pu_20 pu_19 pu_18 pu_17 pu_16 rsvd rsvd rsvd pu_28 pu_27 pu_26 pu_25 pu_24 rsvd pu_22 pu_21 pu_20 pu_19 pu_18 pu_17 pu_16 460 amd geode? cs5535 companion device data book gpio subsystem register descriptions 31506b 6.16.2.8 gpio/aux pull-down enable (gpio[x]_pd_en) these registers control enabling of the pull-down on the low (gpio[15:0]) and high (gpio[31: 16]) banks of gpios. if the feature bit is high, the pull-down is enable d. if the feature bit is low, the pull-do wn is disabled.the reset value forces all the pull-downs to be disabled. (these registers use atomic programming, see section 6. 16.1 on page 454 for details.) gpio low bank pull-down enable (gpiol_pd_en) g pio high bank pull-down enable (gpioh_pd_en) 6.16.2.9 gpio/in_aux input enable (gpio[x]_in_en) these registers control the input enable fo r the low (gpio[15:0]) and high (gpio[31: 16]) banks of gpios. if the feature bit is high, the input is enabled. if the feature bit is low, the input is disabled.the reset value forces all the inputs to be dis abled. (these registers use atomic programming, see section 6.16.1 on page 454 for details.) gpio low bank input enable (gpiol_in_en) g pio high bank input enable (gpioh_in_en) gpio i/o offset 1ch ty p e r / w reset value efff1000h gpio i/o offset 9ch ty p e r / w reset value ffff0000h gpiol_pd_en register map 313029282726252423222120191817161514131211109876543210 pd_15 pd_14 pd_13 pd_12 pd_11 pd_10 pd_9 pd_8 pd_7 pd_6 pd_5 pd_4 pd_3 pd_2 pd_1 pd_0 pd_15 pd_14 pd_13 pd_12 pd_11 pd_10 pd_9 pd_8 pd_7 pd_6 pd_5 pd_4 pd_3 pd_2 pd_1 pd_0 for bits [6:5], see special disabling rules for t he auto-sense gpios in section 5.15.5.6 on page 165. gpioh_pd_en register map 313029282726252423222120191817161514131211109876543210 rsvd rsvd rsvd pd_28 pd_27 pd_26 pd_25 pd_24 rsvd pd_22 pd_21 pd_20 pd_19 pd_18 pd_17 pd_16 rsvd rsvd rsvd pd_28 pd_27 pd_26 pd_25 pd_24 rsvd pd_22 pd_21 pd_20 pd_19 pd_18 pd_17 pd_16 gpio i/o offset 20h ty p e r / w reset value ffff0000h gpio i/o offset a0h ty p e r / w reset value efff1000h gpiol_in_en register map 313029282726252423222120191817161514131211109876543210 in_en_15 in_en_14 in_en_13 in_en_12 in_en_11 in_en_10 in_en_9 in_en_8 in_en_7 in_en_6 in_en_5 in_en_4 in_en_3 in_en_2 in_en_1 in_en_0 in_en_15 in_en_14 in_en_13 in_en_12 in_en_11 in_en_10 in_en_9 in_en_8 in_en_7 in_en_6 in_en_5 in_en_4 in_en_3 in_en_2 in_en_1 in_en_0 gpioh_in_en register map 313029282726252423222120191817161514131211109876543210 rsvd rsvd rsvd in_en_28 in_en_27 in_en_26 in_en_25 in_en_24 rsvd in_en_22 in_en_21 in_en_20 in_en_19 in_en_18 in_en_17 in_en_16 rsvd rsvd rsvd in_en_28 in_en_27 in_en_26 in_en_25 in_en_24 rsvd in_en_22 in_en_21 in_en_20 in_en_19 in_en_18 in_en_17 in_en_16 amd geode? cs5535 companion device data book 461 gpio subsystem register descriptions 31506b 6.16.2.10 gpio/in_aux input invert enable (gpio[x]_in_invrt_en) these registers control the input invert enable for the low (g pio[15:0]) and high (gpio[31: 16]) banks of gpios. the input is inverted if the feature bit is high. t he input is not inverted if the feature bit is low. (these registers use atomic progra m- ming, see section 6.16.1 on page 454 for details.) gpio low bank input invert enable (gpiol_in_invrt_en) gpio high bank input invert enable (gpioh_in_inv_en) 6.16.2.11 gpio/in_aux input filter enable (gpio[x]_in_fltr_en) these registers control the input filter function enable for the low (gpio[15:0 ]) and high (gpio[31:16 ]) banks of gpios. if the feature bit is high, the filter function is enabled. if the feature bit is low, the filter function is disabled.the reset v alue forces all the filter functions to be di sabled. (these registers use atomic programm ing, see section 6.16.1 on page 454 for details.) gpio low bank input filter enable (gpiol_in_fltr_en) gpio high bank input filter enable (gpioh_in_flter_en) gpio i/o offset 24h ty p e r / w reset value ffff0000h gpio i/o offset a4h ty p e r / w reset value ffff0000h gpiol_in_invrt_en register map 313029282726252423222120191817161514131211109876543210 in_invrt_15 in_invrt_14 in_invrt_13 in_invrt_12 in_invrt_11 in_invrt_10 in_invrt_9 in_invrt_8 in_invrt_7 in_invrt_6 in_invrt_5 in_invrt_4 in_invrt_3 in_invrt_2 in_invrt_1 in_invrt_0 in_invrt_15 in_invrt_14 in_invrt_13 in_invrt_12 in_invrt_11 in_invrt_10 in_invrt_9 in_invrt_8 in_invrt_7 in_invrt_6 in_invrt_5 in_invrt_4 in_invrt_3 in_invrt_2 in_invrt_1 in_invrt_0 gpioh_in_invrt_en register map 313029282726252423222120191817161514131211109876543210 rsvd rsvd rsvd in_invrt_28 in_invrt_27 in_invrt_26 in_invrt_25 in_invrt_24 rsvd in_invrt_22 in_invrt_21 in_invrt_20 in_invrt_19 in_invrt_18 in_invrt_17 in_invrt_16 rsvd rsvd rsvd in_invrt_28 in_invrt_27 in_invrt_26 in_invrt_25 in_invrt_24 rsvd in_invrt_22 in_invrt_21 in_invrt_20 in_invrt_19 in_invrt_18 in_invrt_17 in_invrt_16 gpio i/o offset 28h ty p e r / w reset value ffff0000h gpio i/o offset a8h ty p e r / w reset value ffff0000h gpiol_in_fltr_en register map 313029282726252423222120191817161514131211109876543210 in_fltr_15 in_fltr_14 in_fltr_13 in_fltr_12 in_fltr_11 in_fltr_10 in_fltr_9 in_fltr_8 in_fltr_7 in_fltr_6 in_fltr_5 in_fltr_4 in_fltr_3 in_fltr_2 in_fltr_1 in_fltr_0 in_fltr_15 in_fltr_14 in_fltr_13 in_fltr_12 in_fltr_11 in_fltr_10 in_fltr_9 in_fltr_8 in_fltr_7 in_fltr_6 in_fltr_5 in_fltr_4 in_fltr_3 in_fltr_2 in_fltr_1 in_fltr_0 gpioh_in_fltr_en register map 313029282726252423222120191817161514131211109876543210 rsvd rsvd rsvd in_fltr_28 in_fltr_27 in_fltr_26 in_fltr_25 in_fltr_24 rsvd in_fltr_22 in_fltr_21 in_fltr_20 in_fltr_19 in_fltr_18 in_fltr_17 in_fltr_16 rsvd rsvd rsvd in_fltr_28 in_fltr_27 in_fltr_26 in_fltr_25 in_fltr_24 rsvd in_fltr_22 in_fltr_21 in_fltr_20 in_fltr_19 in_fltr_18 in_fltr_17 in_fltr_16 462 amd geode? cs5535 companion device data book gpio subsystem register descriptions 31506b 6.16.2.12 gpio/in_aux input event co unt enable (gpio[ x]_in_evntcnt_en) these registers control the enabling of the input event count er function for the low (gpio[ 15:0]) and high (gpio[31:16]) banks of gpios. if the feature bit is high, the event counter func tion is enabled on the input. if the feature bit is low, the event counter function is disabled on the input. the reset value forces all the filter functions to be disabled. (these registe rs use atomic programming, see sect ion 6.16.1 on page 454 for details.) when the event counter is enabl ed, the filter must also be ena bled (gpio i/o offset 28h/a8h). if no filtering is desired, then program the gpio_filter[x]_amount register to 0. gpio low bank input event count enable (gpiol_in_evntcnt_en) gpio high bank input event count enable (gpioh_in_evntcnt_en) gpio i/o offset 2ch ty p e r / w reset value ffff0000h gpio i/o offset ach ty p e r / w reset value ffff0000h gpiol_in_evntcnt_en register map 313029282726252423222120191817161514131211109876543210 in_evntcnt_15 in_evntcnt_14 in_evntcnt_13 in_evntcnt_12 in_evntcnt_11 in_evntcnt_10 in_evntcnt_9 in_evntcnt_8 in_evntcnt_7 in_evntcnt_6 in_evntcnt_5 in_evntcnt_4 in_evntcnt_3 in_evntcnt_2 in_evntcnt_1 in_evntcnt_0 in_evntcnt_15 in_evntcnt_14 in_evntcnt_13 in_evntcnt_12 in_evntcnt_11 in_evntcnt_10 in_evntcnt_9 in_evntcnt_8 in_evntcnt_7 in_evntcnt_6 in_evntcnt_5 in_evntcnt_4 in_evntcnt_3 in_evntcnt_2 in_evntcnt_1 in_evntcnt_0 gpioh_in_evntcnt_en register map 313029282726252423222120191817161514131211109876543210 rsvd rsvd rsvd in_evntcnt_28 in_evntcnt_27 in_evntcnt_26 in_evntcnt_25 in_evntcnt_24 rsvd in_evntcnt_22 in_evntcnt_21 in_evntcnt_20 in_evntcnt_19 in_evntcnt_18 in_evntcnt_17 in_evntcnt_16 rsvd rsvd rsvd in_evntcnt_28 in_evntcnt_27 in_evntcnt_26 in_evntcnt_25 in_evntcnt_24 rsvd in_evntcnt_22 in_evntcnt_21 in_evntcnt_20 in_evntcnt_19 in_evntcnt_18 in_evntcnt_17 in_evntcnt_16 amd geode? cs5535 companion device data book 463 gpio subsystem register descriptions 31506b 6.16.2.13 gpio input auxiliary 1 select (gpio[x]_in_aux1_sel) each gpio has a dedicated internal destination for the conditio ned input from the component ball; these inputs are acti- vated when auxiliary 1 input is selected. table 3-8 "gpio options" on page 47 shows all the dedicated destinations. these registers select the auxiliary 1 input of the low (gpio[15:0]) and high (gpio[31: 16]) banks of gpios. auxiliary 1 input is selected as the input if the feature bit is high. auxiliary 1 is not selected as the input if the feature bit is low. (these re gisters use atomic programming, see sect ion 6.16.1 on page 454 for details.) gpio low bank input auxiliary 1 select (gpiol_in_aux1_sel) gpio high bank input auxiliary 1 select (gpioh_in_aux1_sel) 6.16.2.14 gpio/in_aux event enable (gpio[x]_evnt_en) these registers control the event enab le for int (interrupt) and pme (power management event) mapping of the low (gpio[15:0]) and high (gpio[31:16]) ban ks of gpios. the gpio is enabled for m apping if the feature bit is high. the gpio is disabled from mapping if the feature bit is low. actual m apping is performed by the gpio x, y, z, and w mapping regis- ters, detailed on page 482 through page 479; the event enable registers simply enable/disable the associated gpio for mapping. (these registers use atomic programming, see section 6.16.1 on page 454 for details.) gpio low bank events enable (gpiol_evnt_en) g pio high bank events enable (gpioh_evnt_en) gpio i/o offset 34h ty p e r / w reset value ffff0000h gpio i/o offset b4h ty p e r / w reset value efff1000h gpiol_in_aux1_sel register map 313029282726252423222120191817161514131211109876543210 in_aux1_15 in_aux1_14 in_aux1_13 in_aux1_12 in_aux1_11 in_aux1_10 in_aux1_9 in_aux1_8 in_aux1_7 in_aux1_6 in_aux1_5 in_aux1_4 in_aux1_3 in_aux1_2 in_aux1_1 in_aux1_0 in_aux1_15 in_aux1_14 in_aux1_13 in_aux1_12 in_aux1_11 in_aux1_10 in_aux1_9 in_aux1_8 in_aux1_7 in_aux1_6 in_aux1_5 in_aux1_4 in_aux1_3 in_aux1_2 in_aux1_1 in_aux1_0 gpioh_in_aux1_sel register map 313029282726252423222120191817161514131211109876543210 rsvd rsvd rsvd in_aux1_28 in_aux1_27 in_aux1_26 in_aux1_25 in_aux1_24 rsvd in_aux1_22 in_aux1_21 in_aux1_20 in_aux1_19 in_aux1_18 in_aux1_17 in_aux1_16 rsvd rsvd rsvd in_aux1_28 in_aux1_27 in_aux1_26 in_aux1_25 in_aux1_24 rsvd in_aux1_22 in_aux1_21 in_aux1_20 in_aux1_19 in_aux1_18 in_aux1_17 in_aux1_16 gpio i/o offset 38h ty p e r / w reset value ffff0000h gpio i/o offset b8h ty p e r / w reset value ffff0000h gpiol_evnt_en register map 313029282726252423222120191817161514131211109876543210 evnt_15 evnt_14 evnt_13 evnt_12 evnt_11 evnt_10 evnt_9 evnt_8 evnt_7 evnt_6 evnt_5 evnt_4 evnt_3 evnt_2 evnt_1 evnt_0 evnt_15 evnt_14 evnt_13 evnt_12 evnt_11 evnt_10 evnt_9 evnt_8 evnt_7 evnt_6 evnt_5 evnt_4 evnt_3 evnt_2 evnt_1 evnt_0 gpioh_evnt_en register map 313029282726252423222120191817161514131211109876543210 rsvd rsvd rsvd evnt_28 evnt_27 evnt_26 evnt_25 evnt_24 rsvd evnt_22 evnt_21 evnt_20 evnt_19 evnt_18 evnt_17 evnt_16 rsvd rsvd rsvd evnt_28 evnt_27 evnt_26 evnt_25 evnt_24 rsvd evnt_22 evnt_21 evnt_20 evnt_19 evnt_18 evnt_17 evnt_16 464 amd geode? cs5535 companion device data book gpio subsystem register descriptions 31506b 6.16.2.15 gpio/in_aux input positive edge enable (gpio[x]_in_posedge_en) these registers control the enabling of the positive edge det ector function for the low (g pio[15:0]) and hi gh (gpio[31:16]) banks of gpios. the positive edge detector function is enabl ed if the feature bit is high. the positive edge detector function is disabled if the feature bit is low. (t hese registers use atomic programming, se e section 6.16.1 on page 454 for details.) gpio low bank input positive edge enable (gpiol_in_posedge_en) gpio high bank input positive edge enable (gpioh_in_posedge_en) 6.16.2.16 gpio/in_aux input negative edge enable (gpio[x]_in_negedge_en) these registers control the enabling of th e negative edge detector function in th e inputs for the low (gpio[15:0]) and high (gpio[31:16]) banks of gpios. the negativ e edge detector function is enabled if t he feature bit is high. the negative edge detector function is disabled if the feature bit is low. (the se registers use atomic programming, see section 6.16.1 on page 454 for details.) gpio low bank input negative edge enable (gpiol_in_negedge_en) gpio high bank input negative edge enable (gpioh_in_negedge_en) gpio i/o offset 40h ty p e r / w reset value ffff0000h gpio i/o offset c0h ty p e r / w reset value ffff0000h gpiol_in_posedge_en register map 313029282726252423222120191817161514131211109876543210 in_pos_15 in_pos_14 in_pos_13 in_pos_12 in_pos_11 in_pos_10 in_pos_9 in_pos_8 in_pos_7 in_pos_6 in_pos_5 in_pos_4 in_pos_3 in_pos_2 in_pos_1 in_pos_0 in_pos_15 in_pos_14 in_pos_13 in_pos_12 in_pos_11 in_pos_10 in_pos_9 in_pos_8 in_pos_7 in_pos_6 in_pos_5 in_pos_4 in_pos_3 in_pos_2 in_pos_1 in_pos_0 gpioh_in_posedge_en register map 313029282726252423222120191817161514131211109876543210 rsvd rsvd rsvd in_pos_28 in_pos_27 in_pos_26 in_pos_25 in_pos_24 rsvd in_pos_22 in_pos_21 in_pos_20 in_pos_19 in_pos_18 in_pos_17 in_pos_16 rsvd rsvd rsvd in_pos_28 in_pos_27 in_pos_26 in_pos_25 in_pos_24 rsvd in_pos_22 in_pos_21 in_pos_20 in_pos_19 in_pos_18 in_pos_17 in_pos_16 gpio i/o offset 44h ty p e r / w reset value ffff0000h gpio i/o offset c4h ty p e r / w reset value ffff0000h gpiol_in_negedge_en register map 313029282726252423222120191817161514131211109876543210 in_neg_15 in_neg_14 in_neg_13 in_neg_12 in_neg_11 in_neg_10 in_neg_9 in_neg_8 in_neg_7 in_neg_6 in_neg_5 in_neg_4 in_neg_3 in_neg_2 in_neg_1 in_neg_0 in_neg_15 in_neg_14 in_neg_13 in_neg_12 in_neg_11 in_neg_10 in_neg_9 in_neg_8 in_neg_7 in_neg_6 in_neg_5 in_neg_4 in_neg_3 in_neg_2 in_neg_1 in_neg_0 gpioh_in_negedge_en register map 313029282726252423222120191817161514131211109876543210 rsvd rsvd rsvd in_neg_28 in_neg_27 in_neg_26 in_neg_25 in_neg_24 rsvd in_neg_22 in_neg_21 in_neg_20 in_neg_19 in_neg_18 in_neg_17 in_neg_16 rsvd rsvd rsvd in_neg_28 in_neg_27 in_neg_26 in_neg_25 in_neg_24 rsvd in_neg_22 in_neg_21 in_neg_20 in_neg_19 in_neg_18 in_neg_17 in_neg_16 amd geode? cs5535 companion device data book 465 gpio subsystem register descriptions 31506b 6.16.2.17 gpio/in_aux input positive edge status (gpio[x]_in_posedge_sts) these registers report the status of the positive edge detectio n function for the low (gpio[ 15:0]) and high (gpio[31:16]) banks of gpios. writing a 1 clears the detected edge and reading returns the curre nt status. (these registers use atomic programming, see section 6.16.1 on page 454 for details.) gpio low bank input positive edge status (gpiol_in_posedge_sts) gpio high bank input positive edge status (gpioh_in_posedge_sts) gpio i/o offset 48h ty p e r / w reset value ffff0000h gpio i/o offset c8h ty p e r / w reset value ffff0000h gpiol_in_posedge_sts register map 313029282726252423222120191817161514131211109876543210 in_pos_sts_15 in_pos_sts_14 in_pos_sts_13 in_pos_sts_12 in_pos_sts_11 in_pos_sts_10 in_pos_sts_9 in_pos_sts_8 in_pos_sts_7 in_pos_sts_6 in_pos_sts_5 in_pos_sts_4 in_pos_sts_3 in_pos_sts_2 in_pos_sts_1 in_pos_sts_0 in_pos_sts_15 in_pos_sts_14 in_pos_sts_13 in_pos_sts_12 in_pos_sts_11 in_pos_sts_10 in_pos_sts_9 in_pos_sts_8 in_pos_sts_7 in_pos_sts_6 in_pos_sts_5 in_pos_sts_4 in_pos_sts_3 in_pos_sts_2 in_pos_sts_1 in_pos_sts_0 gpioh_in_posedge_sts register map 313029282726252423222120191817161514131211109876543210 rsvd rsvd rsvd in_pos_sts_28 in_pos_sts_27 in_pos_sts_26 in_pos_sts_25 in_pos_sts_24 rsvd in_pos_sts_22 in_pos_sts_21 in_pos_sts_20 in_pos_sts_19 in_pos_sts_18 in_pos_sts_17 in_pos_sts_16 rsvd rsvd rsvd in_pos_sts_28 in_pos_sts_27 in_pos_sts_26 in_pos_sts_25 in_pos_sts_24 rsvd in_pos_sts_22 in_pos_sts_21 in_pos_sts_20 in_pos_sts_19 in_pos_sts_18 in_pos_sts_17 in_pos_sts_16 466 amd geode? cs5535 companion device data book gpio subsystem register descriptions 31506b 6.16.2.18 gpio/in_aux input negative edge status (gpio[x]_in_negedge_sts) these registers report the stat us of the negative edge detection function fo r the low (gpio[15:0]) and high (gpio[31:16]) banks of gpios. writing a 1 clears the detected edge and reading returns the curre nt status. (these registers use atomic programming, see section 6.16.1 on page 454 for details.) gpio low bank input negative edge status (gpiol_in_negedge_sts) gpio high bank input negative edge status (gpioh_in_negedge_sts) gpio i/o offset 4ch ty p e r / w reset value ffff0000h gpio i/o offset cch ty p e r / w reset value ffff0000h gpiol_in_negedge_sts register map 313029282726252423222120191817161514131211109876543210 in_neg_sts_15 in_neg_sts_14 in_neg_sts_13 in_neg_sts_12 in_neg_sts_11 in_neg_sts_10 in_neg_sts_9 in_neg_sts_8 in_neg_sts_7 in_neg_sts_6 in_neg_sts_5 in_neg_sts_4 in_neg_sts_3 in_neg_sts_2 in_neg_sts_1 in_neg_sts_0 in_neg_sts_15 in_neg_sts_14 in_neg_sts_13 in_neg_sts_12 in_neg_sts_11 in_neg_sts_10 in_neg_sts_9 in_neg_sts_8 in_neg_sts_7 in_neg_sts_6 in_neg_sts_5 in_neg_sts_4 in_neg_sts_3 in_neg_sts_2 in_neg_sts_1 in_neg_sts_0 gpioh_in_negedge_sts register map 313029282726252423222120191817161514131211109876543210 rsvd rsvd rsvd in_neg_sts_28 in_neg_sts_27 in_neg_sts_26 in_neg_sts_25 in_neg_sts_24 rsvd in_neg_sts_22 in_neg_sts_21 in_neg_sts_20 in_neg_sts_19 in_neg_sts_18 in_neg_sts_17 in_neg_sts_16 rsvd rsvd rsvd in_neg_sts_28 in_neg_sts_27 in_neg_sts_26 in_neg_sts_25 in_neg_sts_24 rsvd in_neg_sts_22 in_neg_sts_21 in_neg_sts_20 in_neg_sts_19 in_neg_sts_18 in_neg_sts_17 in_neg_sts_16 amd geode? cs5535 companion device data book 467 gpio subsystem register descriptions 31506b 6.16.2.19 gpio read back (gpio[x]_read_back) the read back registers provide the current values of the states of each gpio as sent to the ball. the gpio[x]_read_back registers are not based on the atomic programming model since thes e are not control registers. gpio low bank read back (gpiol_read_back) gpio i/o offset 30h ty p e r o reset value 00000000h gpiol_read_back register map 313029282726252423222120191817161514131211109876543210 rsvd rb_15 rb_14 rb_13 rb_12 rb_11 rb_10 rb_9 rb_8 rb_7 rb_6 rb_5 rb_4 rb_3 rb_2 rb_1 rb_0 gpiol_read_back bit descriptions bit name description 31:16 rsvd reserved. reads back 0. 15 rb_15 gpio15 read back value. provides status (1/0) of the associated gpio ball. 14 rb_14 gpio14 read back value. provides status (1/0) of the associated gpio ball. 13 rb_13 gpio13 read back value. provides status (1/0) of the associated gpio ball. 12 rb_12 gpio12 read back value. provides status (1/0) of the associated gpio ball. 11 rb_11 gpio11 read back value. provides status (1/0) of the associated gpio ball. 10 rb_10 gpio10 read back value. provides status (1/0) of the associated gpio ball. 9rb_9 gpio9 read back value. provides status (1/0) of the associated gpio ball. 8rb_8 gpio8 read back value. provides status (1/0) of the associated gpio ball. 7rb_7 gpio7 read back value. provides status (1/0) of the associated gpio ball. 6rb_6 gpio6 read back value. provides status (1/0) of the associated gpio ball. 5rb_5 gpio5 read back value. provides status (1/0) of the associated gpio ball. 4rb_4 gpio4 read back value. provides status (1/0) of the associated gpio ball. 3rb_3 gpio3 read back value. provides status (1/0) of the associated gpio ball. 2rb_2 gpio2 read back value. provides status (1/0) of the associated gpio ball. 1rb_1 gpio1 read back value. provides status (1/0) of the associated gpio ball. 0rb_0 gpio0 read back value. provides status (1/0) of the associated gpio ball. 468 amd geode? cs5535 companion device data book gpio subsystem register descriptions 31506b gpio high bank read back (gpioh_read_back) gpio i/o offset b0h ty p e r o reset value 00000000h gpioh_read_back register map 313029282726252423222120191817161514131211109876543210 rsvd rsvd rsvd rsvd rb_28 rb_27 rb_26 rb_25 rb_24 rsvd rb_22 rb_21 rb_20 rb_19 rb_18 rb_17 rb_16 gpioh_read_back bit descriptions bit name description 31:16 rsvd reserved. reads back 0. 15 rsvd reserved. reads back 0. 14 rsvd reserved. reads back 0. 13 rsvd reserved. reads back 0. 12 rb_28 gpio28 read back value. provides status (1/0) of the associated gpio ball. 11 rb_27 gpio27 read back value. provides status (1/0) of the associated gpio ball. 10 rb_26 gpio26 read back value. provides status (1/0) of the associated gpio ball. 9 rb_25 gpio25 read back value. provides status (1/0) of the associated gpio ball. 8 rb_24 gpio24 read back value. provides status (1/0) of the associated gpio ball. 7 rsvd reserved. reads back 0. 6 rb_22 gpio22 read back value. provides status (1/0) of the associated gpio ball. 5 rb_21 gpio21 read back value. provides status (1/0) of the associated gpio ball. 4 rb_20 gpio20 read back value. provides status (1/0) of the associated gpio ball. 3 rb_19 gpio19 read back value. provides status (1/0) of the associated gpio ball. 2 rb_18 gpio18 read back value. provides status (1/0) of the associated gpio ball. 1 rb_17 gpio17 read back value. provides status (1/0) of the associated gpio ball. 0 rb_16 gpio16 read back value. provides status (1/0) of the associated gpio ball. amd geode? cs5535 companion device data book 469 gpio subsystem register descriptions 31506b 6.16.2.20 gpio/aux lock en able (gpio[x]_lock_en these registers lock the values of f eature bit registers except the gpio[x ]_read_back, gpio[x]_in_posedge_sts, and gpio[x]_in_negedge_sts registers. when set, the indicated feature bits may not be changed. the gpio[x]_lock_en registers are not based on the atomic programming model (i.e., only one bit for control as opposed to two bits). gpio low bank lock enable (gpiol_lock_en) gpio i/o offset 3ch ty p e r / w reset value 00000000h gpiol_lock_en register map 313029282726252423222120191817161514131211109876543210 rsvd lkne lkpe lkip lkia lkee lkfe lkii lkie lkpd lkpu lka2 lka1 lkoi lkod lkoe lkov gpiol_lock_enable bit descriptions bit name description 31:15 rsvd reserved. write to 0. 15 lkne lock gpiol_in_negedge_en. when set, writing to the gpio low bank input neg- ative edge enable register (gpi o i/o offset 44h) is prevented. 14 lkpe lock gpiol_in_posedge_en. when set, writing to the gpio low bank input posi- tive edge enable register (gpi o i/o offset 40h) is prevented. 13 lkip lock gpiol_events_en. when set, writing to the gpio low bank events enable (interrupts &pmes) register (gpio i/o offset 38h) is prevented. 12 lkia lock gpiol_in_aux1_sel. when set, writing to the gpio low bank input auxiliary 1 select register (gpio i/o offset 34h) is prevented. 11 lkee lock gpiol_in_evntcnt_en. when set, writing to the gpio low bank input event count enable register (gpio i/o offset 2ch) is prevented. 10 lkfe lock gpiol_in_fltr_en. when set, writing to the gpio low bank input filter enable register (gpio i/o offset 28h) is prevented. 9lkii lock gpiol_in_invrt_en. when set, writing to the gpio low bank input invert enable register (gpio i/o offset 24h) is prevented. 8lkie lock gpiol_in_en. when set, writing to the gpio low bank input enable register (gpio i/o offset 20h) is prevented. 7 lkpd lock gpiol_pu_en. when set, writing to the gpio low bank pull-down enable reg- ister (gpio i/o offset 1ch) is prevented. 6 lkpu lock gpiol_pu_en. when set, writing to the gpio low bank pull-up enable register (gpio i/o offset 18h) is prevented. 5 lka2 lock gpiol_out_aux2_sel. when set, writing to the gpio low bank output auxil- iary 2 select register (gpio i/o offset 14h) is prevented. 4 lka1 lock gpiol_out_aux1_sel. when set, writing to the gpio low bank output auxil- iary 1 select register (gpio i/o offset 10h) is prevented. 3lkoi lock gpiol_out_invrt_en. when set, writing to the gpio low bank output invert enable register (gpio i/o of fset 0ch) is prevented. 2lkod lock gpiol_out_od_en. when set, writing to the gpio low bank output open- drain enable register (gpio i/ o offset 08h) is prevented. 1lkoe lock gpiol_out_en. when set, writing to the gpio low bank enable register (gpio i/o offset 04h) is prevented. 0lkov lock gpiol_out_val. when set, writing to the gpio low bank output value regis- ter (gpio i/o offset 00h) is prevented. 470 amd geode? cs5535 companion device data book gpio subsystem register descriptions 31506b gpio high bank lock enable (gpioh_lock_en) gpio i/o offset bch ty p e r / w reset value 00000000h gpioh_lock_en register map 313029282726252423222120191817161514131211109876543210 rsvd lkne lkpe lkip lkia lkee lkfe lkii lkie lkpd lkpu lka2 lka1 lkoi lkod lkoe lkov gpioh_lock_en bit descriptions bit name description 31:15 rsvd reserved. write to 0. 15 lkne lock gpioh_in_negedge_ena. when set, writing to the gpio low bank input negative edge enable register (g pio i/o offset c4h) is prevented. 14 lkpe lock gpioh_in_posedge_en. when set, writing to the gpio low bank input posi- tive edge enable register (gpio i/o offset c0h) is prevented. 13 lkip lock gpioh_events_en. when set, writing to the gpio low bank events enable (interrupts &pmes) register (gpio i/o offset b8h) is prevented. 12 lkia lock gpioh_in_aux1_sel. when set, writing to the gpio low bank input auxiliary 1 select register (gpio i/o offset b4h) is prevented. 11 lkee lock gpioh_in_evntcnt_en. when set, writing to the gpio low bank input event count enable register (gpio i/o offset ach) is prevented. 10 lkfe lock gpioh_in_fltr_en. when set, writing to the gpio low bank input filter enable register (gpio i/o offset a8h) is prevented. 9lkii lock gpioh_in_invrt_en. when set, writing to the gpio low bank input invert enable register (gpio i/o offset a4h) is prevented. 8lkie lock gpioh_in_en. when set, writing to the gpio low bank input enable register (gpio i/o offset a0h) is prevented. 7 lkpd lock gpioh_pd_en. when set, writing to the gpio low bank pull-down enable reg- ister (gpio i/o offset 9ch) is prevented. 6 lkpu lock gpioh_pu_en. when set, writing to the gpio low bank pull-up enable regis- ter (gpio i/o offset 98h) is prevented. 5 lka2 lock gpioh_out_aux2_sel. when set, writing to the gpio low bank output aux- iliary 2 select register (gpio i/o offset 94h) is prevented. 4 lka1 lock gpioh_out_aux1_sel. when set, writing to the gpio low bank output aux- iliary 1 select register (gpio i/o offset 90h) is prevented. 3lkoi lock gpioh_out_invrt_en. when set, writing to the gpio low bank output invert enable register (gpio i/o offset 8ch) is prevented. 2lkod lock gpioh_out_od_en. when set, writing to the gpio low bank output open- drain enable register (gpio i/o offset 88h) is prevented. 1lkoe lock gpioh_output_enable. when set, writing to the gpio low bank enable register (gpio i/o offset 84h) is prevented. 0lkov lock gpioh_output_value. when set, writing to the gpio low bank output value register (gpio i/o offset 80h) is prevented. amd geode? cs5535 companion device data book 471 gpio subsystem register descriptions 31506b 6.16.3 gpio input conditioning function registers the geode cs5535 companion device has eight digital filter /event counter pairs (numbered 0 through 7) that can be shared with 28 gpios. there are two 16-bit register s associated with digital f ilter (filter_amount and filter_counter) and two 16-bit regi sters associated with ev ent counter (eventcount and event_comp). the input conditioning function registers are no t based on the atomic programming model. 6.16.3.1 gpio filter amou nt (gpio_fltr[x]_amnt) gpio_filter[x]_amount are 16-bit registers and programmed with a 16-bit filter count value. gpio filter 0 amount (gpio_fltr0_amnt) gpio filter 1 amount (gpio_fltr1_amnt) gpio filter 2 amount (gpio_fltr2_amnt) gpio filter 3 amount (gpio_fltr3_amnt) gpio filter 4 amount (gpio_fltr4_amnt) gpio filter 5 amount (gpio_fltr5_amnt) gpio filter 6 amount (gpio_fltr6_amnt) gpio filter 7 amount (gpio_fltr7_amnt) gpio i/o offset 50h ty p e r / w reset value 0000h gpio i/o offset 58h ty p e r / w reset value 0000h gpio i/o offset 60h ty p e r / w reset value 0000h gpio i/o offset 68h ty p e r / w reset value 0000h gpio i/o offset 70h ty p e r / w reset value 0000h gpio i/o offset 78h ty p e r / w reset value 0000h gpio i/o offset d0h ty p e r / w reset value 0000h gpio i/o offset d8h ty p e r / w reset value 0000h gpio_fltr[x]_amnt register map 1514131211109876543210 filter_amount gpio_fltr[x]_amnt bit descriptions bit name description 15:0 filter_amount filter amount. the associated gpio input must remain stable for a filter_amount number of 32 khz clock edges in order for the output to change. a filter_amount of 0 effectively disables the filtering function because the counter will not roll over from 0 to all 1s. the maximum filter_amount is ffffh. 472 amd geode? cs5535 companion device data book gpio subsystem register descriptions 31506b 6.16.3.2 gpio filter coun t (gpio_filter[x]_count) writing to these 16-bit registers programs the c ounter value. reads provide current counter value. gpio filter 0 count (gpio_fltr0_cnt) gpio filter 1 count (gpio_fltr1_cnt) gpio filter 2 count (gpio_fltr2_cnt) gpio filter 3 count (gpio_fltr3_cnt) gpio filter 4 count (gpio_fltr4_cnt) gpio filter 5 count (gpio_fltr5_cnt) gpio filter 6 count (gpio_fltr6_cnt) gpio filter 7 count (gpio_fltr7_cnt) gpio i/o offset 52h ty p e r / w reset value 0000h gpio i/o offset 5ah ty p e r / w reset value 0000h gpio i/o offset 62h ty p e r / w reset value 0000h gpio i/o offset 6ah ty p e r / w reset value 0000h gpio i/o offset 72h ty p e r / w reset value 0000h gpio i/o offset 7ah ty p e r / w reset value 0000h gpio i/o offset d2h ty p e r / w reset value 0000h gpio i/o offset dah ty p e r / w reset value 0000h gpio_fltr[x]_cnt register map 1514131211109876543210 filter_count gpio_fltr[x]_cnt bit descriptions bit name description 15:0 filter_count filter count. an initial count is loaded into the filter_count via the filter_amount register. direct access to the counter?s state is provided via the filter_count register and may be read at any time to determine the current value of the counter. the filter_count register may also be written to at any time, thereby jamming the counter state forward or backward from the current count. amd geode? cs5535 companion device data book 473 gpio subsystem register descriptions 31506b 6.16.3.3 gpio event coun ter (gpio_evntcnt[x]) writing to these 16-bit registers programs the c ounter value. reads provide current counter value. gpio event counter 0 (gpio_evntcnt0) gpio event counter 1 (gpio_evntcnt1) gpio event counter 2 (gpio_evntcnt2) gpio event counter 3 (gpio_evntcnt3) gpio event counter 4 (gpio_evntcnt4) gpio event counter 5 (gpio_evntcnt5) gpio event counter 6 (gpio_evntcnt6) gpio event counter 7 (gpio_evntcnt7) gpio i/o offset 54h ty p e r / w reset value 0000h gpio i/o offset 5ch ty p e r / w reset value 0000h gpio i/o offset 64h ty p e r / w reset value 0000h gpio i/o offset 6ch ty p e r / w reset value 0000h gpio i/o offset 74h ty p e r / w reset value 0000h gpio i/o offset 7ch ty p e r / w reset value 0000h gpio i/o offset d4h ty p e r / w reset value 0000h gpio i/o offset dch ty p e r / w reset value 0000h gpio_evntcnt[x] register map 1514131211109876543210 event_count gpio_evntcnt_[x] bit descriptions bit name description 15:0 event_count event counter status. direct access to the counter?s stat e is provided via this register and may be read at any time to determine the current value of the co unter. this register may also be written to at any time, thereby jamming the counter state forward or back- ward from the current count. hardware prov isions exist to ensure accurate readings even if a counter edge is in process. 474 amd geode? cs5535 companion device data book gpio subsystem register descriptions 31506b 6.16.3.4 gpio event counter compar e value (gpio_evntcnt[x]_comp) these 16-bit registers are programm ed with event count compare value. gpio event counter 0 compare value (gpio_evntcnt0_comp) gpio event counter 1 compare value (gpio_evntcnt1_comp) gpio event counter 2 compare value (gpio_evntcnt2_comp) gpio event counter 3 compare value (gpio_evntcnt3_comp) gpio event counter 4 compare value (gpio_evntcnt4_comp) gpio event counter 5 compare value (gpio_evntcnt5_comp) gpio event counter 6 compare value (gpio_evntcnt6_comp) gpio event counter 7 compare value (gpio_evntcnt7_comp) gpio i/o offset 56h ty p e r / w reset value 0000h gpio i/o offset 5eh ty p e r / w reset value 0000h gpio i/o offset 66h ty p e r / w reset value 0000h gpio i/o offset 6eh ty p e r / w reset value 0000h gpio i/o offset 76h ty p e r / w reset value 0000h gpio i/o offset 7eh ty p e r / w reset value 0000h gpio i/o offset d6h ty p e r / w reset value 0000h gpio i/o offset deh ty p e r / w reset value 0000h gpio_evntcnt[x]_comp register map 1514131211109876543210 evntcnt_comp gpio_eventcount_[x] bit descriptions bit name description 15:0 evntcnt_comp event counter compare value. this register is used to set the event counter?s com- pare value. the compare value, when exceeded by the event counter, causes the counter to produce a constant (level) output. amd geode? cs5535 companion device data book 475 gpio subsystem register descriptions 31506b 6.16.3.5 gpio filter/event pair selection (g pio_fe[x]_sel) these registers assign any gpio to on e of the eight filter/event pairs; part of the input conditioning functions. gpio filter/event pair 0 selection (gpio_fe0_sel) gpio filter/event pair 1 selection (gpio_fe1_sel) gpio filter/event pair 2 selection (gpio_fe2_sel) gpio filter/event pair 3 selection (gpio_fe3_sel) gpio filter/event pair 4 selection (gpio_fe4_sel) gpio filter/event pair 5 selection (gpio_fe5_sel) gpio filter/event pair 6 selection (gpio_fe6_sel) gpio filter/event pair 7 selection (gpio_fe7_sel) gpio i/o offset f0h ty p e r / w reset value 00h gpio i/o offset f1h ty p e r / w reset value 00h gpio i/o offset f2h ty p e r / w reset value 00h gpio i/o offset f3h ty p e r / w reset value 00h gpio i/o offset f4h ty p e r / w reset value 00h gpio i/o offset f5h ty p e r / w reset value 00h gpio i/o offset f6h ty p e r / w reset value 00h gpio i/o offset f7h ty p e r / w reset value 00h gpio_fe[x]_sel register map 76543210 rsvd fe_sel gpio_fe[x]_sel bit descriptions bit name description 7:5 rsvd reserved. 476 amd geode? cs5535 companion device data book gpio subsystem register descriptions 31506b 4:0 fe_sel filter/event pair select. selects one of 32 gpio inputs, filter enables, event enables, and event counter decrements for filter event pair [x]. 00000: gpio0 is connected to filter event pair [x]. 00001: gpio1 is connected to filter event pair [x]. 00010: gpio2 is connected to filter event pair [x]. 00011: gpio3 is connected to filter event pair [x]. 00100: gpio4 is connected to filter event pair [x]. 00101: gpio5 is connected to filter event pair [x]. 00110: gpio6 is connected to filter event pair [x]. 00111: gpio7 is connected to filter event pair [x]. 01000: gpio8 is connected to filter event pair [x]. 01001: gpio9 is connected to filter event pair [x]. 01010: gpio10 is connected to filter event pair [x]. 01011: gpio11 is connected to filter event pair [x]. 01100: gpio12 is connected to filter event pair [x]. 01101: gpio13 is connected to filter event pair [x]. 01110: gpio14 is connected to filter event pair [x]. 01111: gpio15 is connected to filter event pair [x]. 10000: gpio16 is connected to filter event pair [x]. 10001: gpio17 is connected to filter event pair [x]. 10010: gpio18 is connected to filter event pair [x]. 01011: gpio19 is connected to filter event pair [x]. 10100 gpio20 is connected to filter event pair [x]. 10101: gpio21 is connected to filter event pair [x]. 10110: gpio22 is connected to filter event pair [x]. 10111: reserved. 11000: gpio24 is connected to filter event pair [x]. 11001: gpio25 is connected to filter event pair [x]. 11010: gpio26 is connected to filter event pair [x]. 11011: gpio27 is connected to filter event pair [x]. 11100: gpio28 is connected to filter event pair [x]. 11101: reserved. 11110: reserved. 11111: reserved. gpio_fe[x]_sel bit descriptions (continued) bit name description amd geode? cs5535 companion device data book 477 gpio subsystem register descriptions 31506b 6.16.3.6 gpio event counter decr ement (gpio[x]_evntcnt_dec) there are two 32-bit event counter decrem ent registers one for the lower bank (g pio[15:0]) and one for the higher bank (gpio[31:16]) of gpios.these registers generate one 33 ns wi de pulse when written to it, so multiple successive writes may be performed without waiting for the previous write to ?com plete; in addition, reading these registers always provides 0s. gpio low bank event counter decrement (gpiol_evntcnt_dec) gpio i/o offset f8h ty p e r / w reset value 00000000h gpiol_evntcnt_dec register map 313029282726252423222120191817161514131211109876543210 rsvd ecd_15 ecd_14 ecd_13 ecd_12 ecd_11 ecd_10 ecd_9 ecd_8 ecd_7 ecd_6 ecd_5 ecd_4 ecd_3 ecd_2 ecd_1 ecd_0 gpiol_evntcnt_dec bit descriptions bit name description 31:16 rsvd reserved. write/read as 0. 15 ecd15 gpio15 event counter decrement. writing this bit high generates a decrement pulse to the event counter that has been associated with this gpio. there is no need to write the bit low again. this bit will always read as low. event counters are associated with specific gpios via the gpio_fe[x]_sel register set. 14 ecd14 gpio14 event counter decrement. same as edc15 (bit 15) 13 ecd13 gpio13 event counter decrement. same as edc15 (bit 15) 12 ecd12 gpio12 event counter decrement. same as edc15 (bit 15). 11 ecd11 gpio11 event counter decrement. same as edc15 (bit 15). 10 ecd10 gpio10 event counter decrement. same as edc15 (bit 15). 9 ecd9 gpio9 event counter decrement. same as edc15 (bit 15). 8 ecd8 gpio8 event counter decrement. same as edc15 (bit 15). 7 ecd7 gpio7 event counter decrement. same as edc15 (bit 15). 6 ecd6 gpio6 event counter decrement. same as edc15 (bit 15). 5 ecd5 gpio5 event counter decrement. same as edc15 (bit 15). 4 ecd4 gpio4 event counter decrement. same as edc15 (bit 15). 3 ecd3 gpio3 event counter decrement. same as edc15 (bit 15). 2 ecd2 gpio2 event counter decrement. same as edc15 (bit 15). 1 ecd1 gpio1 event counter decrement. same as edc15 (bit 15). 0 ecd0 gpio0 event counter decrement. same as edc15 (bit 15). 478 amd geode? cs5535 companion device data book gpio subsystem register descriptions 31506b gpio high bank event counter decrement (gpiol_evntcnt_dec) gpio i/o offset fch ty p e r / w reset value 00000000h gpioh_evntcnt_dec register map 313029282726252423222120191817161514131211109876543210 rsvd rsvd rsvd rsvd ecd_28 ecd_27 ecd_26 ecd_25 ecd_24 rsvd ecd_22 ecd_21 ecd_20 ecd_19 ecd_18 ecd_17 ecd_16 gpioh_evntcnt_dec bit descriptions bit name description 31:13 rsvd reserved. write/read as 0. 12 ecd28 gpio28 event counter decrement. writing this bit high generates a decrement pulse to the event counter that has been associated with this gpio. there is no need to write the bit low again. this bit will always read as low. event counters are associated with specific gpios via the gpio_fe[x]_sel register set. 11 ecd27 gpio27 event counter decrement. same as edc28 (bit 12). 10 ecd26 gpio26 event counter decrement. same as edc28 (bit 12). 9 ecd25 gpio25 event counter decrement. same as edc28 (bit 12). 8 ecd24 gpio24 event counter decrement. same as edc28 (bit 12). 7 rsvd reserved. write/read as 0. 6 ecd22 gpio22 event counter decrement. same as edc28 (bit 12). 5 ecd21 gpio21 event counter decrement. same as edc28 (bit 12). 4 ecd20 gpio20 event counter decrement. same as edc28 (bit 12). 3 ecd19 gpio19 event counter decrement. same as edc28 (bit 12). 2 ecd18 gpio18 event counter decrement. same as edc28 (bit 12). 1 ecd17 gpio17 event counter decrement. same as edc28 (bit 12). 0 ecd16 gpio16 event counter decrement. same as edc28 (bit 12). amd geode? cs5535 companion device data book 479 gpio subsystem register descriptions 31506b 6.16.4 gpio interrupt and pme registers there are four 32-bit register s in the mapper used for gpio int (interrupt ) and pme (power management event) mapping. these registers connect any gpio to one of eight pic interrupts or to one of eight pme inputs. 1) gpio_map_w: maps 8 final inputs ([31:24] of 32 final inputs). 2) gpio_map_z: maps 8 final inputs ([23:16] of 32 final inputs). 3) gpio_map_y: maps 8 final input s ([15:8] of 32 final inputs). 4) gpio_map_x: maps 8 final input s ([7:0] of 32 final inputs). the map registers setup the rout ing of the final inputs to either gpio_int[7: 0] or gpio_pme[7:0]. the four registers con- tain 32 4-bit fields, that is a nibble for each final inpu t. each nibble contains the following control bits: pme_sel: located in msb of the nibble and directs the final inpu t to int when low. if high, th e final input is directed to pme outputs. map_sel: these bits determine which bit in the output field the final input is direct ed to (i.e., either (gpio_int[7:0]) or gpio_pme[7:0]). 6.16.4.1 gpio mapper w (gpio_map_w) gpio i/o offset ech ty p e r / w reset value 00000000h gpio_map_w register map 313029282726252423222120191817161514131211109876543210 rsvd pme_sel_28 map_sel_28 pme_sel_27 map_sel_27 pme_sel_26 map_sel_26 pme_sel_25 map_sel_25 pme_sel_24 map_sel_24 gpio_map_w bit descriptions bit name description 31:20 rsvd reserved. write as 0. 19 pme_sel_28 gpio28 pme select. selects where to map gpio28. 0: int (interrupt). 1: pme (power management event). 18:16 map_sel_28 gpio28 map select. selects which bit of in the output field (i.e., int or pme) gpio28 should be mapped to. 000: bit 0 010: bit 2 100: bit 4 110: bit 6 001: bit 1 011: bit 3 101: bit 5 111: bit 7 15 pme_sel_27 gpio27 pme select. selects where to map gpio27. see bit 19 for decode. 14:12 map_sel_27 gpio27 map select. selects which bit of in the output field (i.e., int or pme) gpio27 should be mapped to. see bits [18:16] for decode. 11 pme_sel_26 gpio26 pme select. selects where to map gpio26. see bit 19 for decode. 10:8 map_sel_26 gpio26 map select. selects which bit of in the output field (i.e., int or pme) gpio26 should be mapped to. see bits [18:16] for decode. 7 pme_sel_25 gpio25 pme select. selects where to map gpio25. see bit 19 for decode. 6:4 map_sel_25 gpio25 map select. selects which bit of in the output field (i.e., int or pme) gpio25 should be mapped to. see bits [18:16] for decode. 3 pme_sel_24 gpio24 pme select. selects where to map gpio24. see bit 19 for decode. 2:0 map_sel_24 gpio24 map select. selects which bit of in the output field (i.e., int or pme) gpio24 should be mapped to. see bits [18:16] for decode. 480 amd geode? cs5535 companion device data book gpio subsystem register descriptions 31506b 6.16.4.2 gpio mapper z (gpio_map_z) gpio i/o offset e8h ty p e r / w reset value 00000000h gpio_map_z register map 313029282726252423222120191817161514131211109876543210 rsvd pme_sel_22 map_sel_22 pme_sel_21 map_sel_21 pme_sel_20 map_sel_20 pme_sel_19 map_sel_19 pme_sel_18 map_sel_18 pme_sel_17 map_sel_17 pme_sel_16 map_sel_16 gpio_map_z bit descriptions bit name description 31:28 rsvd reserved. write as 0. 27 pme_sel_22 gpio22 pme select. selects where to map gpio22. 0: int (interrupt). 1: pme (power management event). 26:24 map_sel_22 gpio22 map select. selects which bit of in the output field (i.e., int or pme) gpio22 should be mapped to. 000: bit 0 010: bit 2 100: bit 4 110: bit 6 001: bit 1 011: bit 3 101: bit 5 111: bit 7 23 pme_sel_21 gpio21 pme select. selects where to map gpio21. see bit 27 for decode. 22:20 map_sel_21 gpio21 map select. selects which bit of in the output field (i.e., int or pme) gpio21 should be mapped to. see bits [26:24] for decode. 19 pme_sel_20 gpio20 pme select. selects where to map gpio20. see bit 27 for decode. 18:16 map_sel_20 gpio20 map select. selects which bit of in the output field (i.e., int or pme) gpio20 should be mapped to. see bits [26:24] for decode. 15 pme_sel_19 gpio19 pme select. selects where to map gpio19. see bit 27 for decode. 14:12 map_sel_19 gpio19 map select. selects which bit of in the output field (i.e., int or pme) gpio19 should be mapped to. see bits [26:24] for decode. 11 pme_sel_18 gpio18 pme select. selects where to map gpio18. see bit 27 for decode. 10:8 map_sel_18 gpio18 map select. selects which bit of in the output field (i.e., int or pme) gpio18 should be mapped to. see bits [26:24] for decode. 7 pme_sel_17 gpio17 pme select. selects where to map gpio17. see bit 27 for decode. 6:4 map_sel_17 gpio17 map select. selects which bit of in the output field (i.e., int or pme) gpio17 should be mapped to. see bits [26:24] for decode. 3 pme_sel_16 gpio16 pme select. selects where to map gpio16. see bit 27 for decode. 2:0 map_sel_16 gpio16 map select. selects which bit of in the output field (i.e., int or pme) gpio16 should be mapped to. see bits [26:24] for decode. amd geode? cs5535 companion device data book 481 gpio subsystem register descriptions 31506b 6.16.4.3 gpio mapper y (gpio_map_y) gpio i/o offset e4h ty p e r / w reset value 00000000h gpio_map_y register map 313029282726252423222120191817161514131211109876543210 pme_sel_15 map_sel_15 pme_sel_14 map_sel_14 pme_sel_5 map_sel_13 pme_sel_12 map_sel_12 pme_sel_11 map_sel_11 pme_sel_10 map_sel_10 pme_sel_9 map_sel_9 pme_sel_8 map_sel_8 gpio_map_y bit descriptions bit name description 31 pme_sel_15 gpio15 pme select. selects where to map gpio15. 0: int (interrupt). 1: pme (power management event). 30:28 map_sel_15 gpio15 map select. selects which bit of in the output field (i.e., int or pme) gpio15 should be mapped to. 000: bit 0 010: bit 2 100: bit 4 110: bit 6 001: bit 1 011: bit 3 101: bit 5 111: bit 7 27 pme_sel_14 gpio14 pme select. selects where to map gpio14. see bit 31 for decode. 26:24 map_sel_14 gpio14 map select. selects which bit of in the output field (i.e., int or pme) gpio14 should be mapped to. see bits [30:28] for decode. 23 pme_sel_13 gpio13 pme select. selects where to map gpio13. see bit 31 for decode. 22:20 map_sel_13 gpio13 map select. selects which bit of in the output field (i.e., int or pme) gpio13 should be mapped to. see bits [30:28] for decode. 19 pme_sel_12 gpio12 pme select. selects where to map gpio12. see bit 31 for decode. 18:16 map_sel_12 gpio12 map select. selects which bit of in the output field (i.e., int or pme) gpio12 should be mapped to. see bits [30:28] for decode. 15 pme_sel_11 gpio11 pme select. selects where to map gpio11. see bit 31 for decode. 14:12 map_sel_11 gpio11 map select. selects which bit of in the output field (i.e., int or pme) gpio11 should be mapped to. see bits [30:28] for decode. 11 pme_sel_10 gpio10 pme select. selects where to map gpio10. see bit 31 for decode. 10:8 map_sel_10 gpio10 map select. selects which bit of in the output field (i.e., int or pme) gpio10 should be mapped to. see bits [30:28] for decode. 7 pme_sel_9 gpio9 pme select. selects where to map gpio9. see bit 31 for decode. 6:4 map_sel_9 gpio9 map select. selects which bit of in the output fi eld (i.e., int or pme) gpio9 should be mapped to. see bits [30:28] for decode. 3 pme_sel_8 gpio8 pme select. selects where to map gpio8. see bit 31 for decode. 2:0 map_sel_8 gpio8 map select. selects which bit of in the output fi eld (i.e., int or pme) gpio8 should be mapped to. see bits [30:28] for decode. 482 amd geode? cs5535 companion device data book gpio subsystem register descriptions 31506b 6.16.4.4 gpio mapper x (gpio_map_x) gpio i/o offset e0h ty p e r / w reset value 00000000h gpio_map_x register map 313029282726252423222120191817161514131211109876543210 pme_sel_7 map_sel_7 pme_sel_6 map_sel_6 pme_sel_5 map_sel_5 pme_sel_4 map_sel_4 pme_sel_3 map_sel_3 pme_sel_2 map_sel_2 pme_sel_1 map_sel_1 pme_sel_0 map_sel_0 gpio_map_x bit descriptions bit name description 31 pme_sel_7 gpio7 pme select. selects where to map gpio7. 0: int (interrupt). 1: pme (power management event). 30:28 map_sel_7 gpio7 map select. selects which bit of in the output fi eld (i.e., int or pme) gpio7 should be mapped to. 000: bit 0 010: bit 2 100: bit 4 110: bit 6 001: bit 1 011: bit 3 101: bit 5 111: bit 7 27 pme_sel_6 gpio6 pme select. selects where to map gpio6. see bit 31 for decode. 26:24 map_sel_6 gpio6 map select. selects which bit of in the output fi eld (i.e., int or pme) gpio6 should be mapped to. see bits [30:28] for decode. 23 pme_sel_5 gpio5 pme select. selects where to map gpio5. see bit 31 for decode. 22:20 map_sel_5 gpio5 map select. selects which bit of in the output fi eld (i.e., int or pme) gpio5 should be mapped to. see bits [30:28] for decode. 19 pme_sel_4 gpio4 pme select. selects where to map gpio4. see bit 31 for decode. 18:16 map_sel_4 gpio4 map select. selects which bit of in the output fi eld (i.e., int or pme) gpio4 should be mapped to. see bits [30:28] for decode. 15 pme_sel_3 gpio3 pme select. selects where to map gpio3. see bit 31 for decode. 14:12 map_sel_3 gpio2 map select. selects which bit of in the output fi eld (i.e., int or pme) gpio3 should be mapped to. see bits [30:28] for decode. 11 pme_sel_2 gpio2 pme select. selects where to map gpio2. see bit 31 for decode. 10:8 map_sel_2 gpio2 map select. selects which bit of in the output fi eld (i.e., int or pme) gpio2 should be mapped to. see bits [30:28] for decode. 7 pme_sel_1 gpio1 pme select. selects where to map gpio1. see bit 31 for decode. 6:4 map_sel_1 gpio1 map select. selects which bit of in the output fi eld (i.e., int or pme) gpio1 should be mapped to. see bits [30:28] for decode. 3 pme_sel_0 gpio0 pme select. selects where to map gpio0. see bit 31 for decode. 2:0 map_sel_0 gpio0 map select. selects which bit of in the output fi eld (i.e., int or pme) gpio0 should be mapped to. see bits [30:28] for decode. amd geode? cs5535 companion device data book 483 multi-function general purpose timer register descriptions 31506b 6.17 multi-function general purpose timer register descriptions the registers for the multi-function general purpose timer (mfgpt) are divided into three sets: standard geodelink device (gld) msrs (shared with divil, see section 6.6.1 on page 317.) mfgpt specific msrs mfgpt native registers. the msrs are accessed via the rdmsr and wrmsr pro- cessor instructions. the msr address is derived from the perspective of the cpu core. see section 4.2 "msr addressing" on page 59 for more details. all msrs are 64 bits, however, the mfgpt specific msrs (summarized in table 6-64) are called out as 32 bits. the mfgpt module treats writes to the upper 32 bits (i.e., bits [63:32]) of the 64-bit msrs as don?t cares and always returns 0 on these bits. the native registers associated with the mfgpt (summa- rized in table 6-65) are accessed via a base address reg- ister, msr_lbar_mfgpt (msr 5140000dh), as i/o offsets. (see section 6.6.2.6 on page 329 for bit descrip- tions of the base address register.) the reference column in the summary tables point to the page where the register maps and bit descriptions are listed. table 6-64. mfgpt specific msrs summary msr address type register name reset value reference 51400028h r/w mfgpt irq mask (mfgpt_irq) 00000000h page 484 51400029h r/w mfgpt nmi and reset mask (mfgpt_nr) 00000000h page 487 5140002ah r/w mfgpt reserved (mfgpt_rsvd) 00000000h page 488 5140002bh wo mfgpt clear setup test (mfgpt_setup) 00000000h page 488 table 6-65. mfgpt native registers summary mfgpt i/o offset type width (bits) register name reset value reference 00h r/w 16 mfgpt0 comparator 1 (mfgpt0_cmp1) 0000h page 489 02h r/w 16 mfgpt0 comparator 2 (mfgpt0_cmp2) 0000h page 490 04h r/w 16 mfgpt0 up counter (mfgpt0_cnt) 0000h page 491 06h r/w 16 mfgpt0 setup (mfgpt0_setup) 0000h page 492 08h r/w 16 mfgpt1 comparator 1 (mfgpt1_cmp1) 0000h page 489 0ah r/w 16 mfgpt1 comparator 2 (mfgpt1_cmp2) 0000h page 490 0ch r/w 16 mfgpt1 up counter (mfgpt1_cnt) 0000h page 491 0eh r/w 16 mfgpt1 setup (mfgpt1_setup) 0000h page 492 10h r/w 16 mfgpt2 comparator 1 (mfgpt2_cmp1) 0000h page 489 12h r/w 16 mfgpt2 comparator 2 (mfgpt2_cmp2) 0000h page 490 14h r/w 16 mfgpt2 up counter (mfgpt2_cnt) 0000h page 491 16h r/w 16 mfgpt2 setup (mfgpt2_setup) 0000h page 492 18h r/w 16 mfgpt3 comparator 1 (mfgpt3_cmp1) 0000h page 489 1ah r/w 16 mfgpt3 comparator 2 (mfgpt3_cmp2) 0000h page 490 1ch r/w 16 mfgpt3 up counter (mfgpt3_cnt) 0000h page 491 1eh r/w 16 mfgpt3 setup (mfgpt3_setup) 0000h page 492 20h r/w 16 mfgpt4 comparator 1 (mfgpt4_cmp1) 0000h page 489 22h r/w 16 mfgpt4 comparator 2 (mfgpt4_cmp2) 0000h page 490 24h r/w 16 mfgpt4 up counter (mfgpt4_cnt) 0000h page 491 484 amd geode? cs5535 companion device data book multi-function general purpose timer register descriptions 31506b 6.17.1 mfgpt specific msrs this register connects the mfgpt comparat or 1 and 2 outputs to the interrupt mapper. 6.17.1.1 mfgpt irq mask (mfgpt_irq) 26h r/w 16 mfgpt4 setup (mfgpt4_setup) 0000h page 492 28h r/w 16 mfgpt5 comparator 1 (mfgpt5_cmp1) 0000h page 489 2ah r/w 16 mfgpt5 comparator 2 (mfgpt5_cmp2) 0000h page 490 2ch r/w 16 mfgpt5 up counter (mfgpt5_cnt) 0000h page 491 2eh r/w 16 mfgpt5 setup (mfgpt5_setup) 0000h page 492 30h r/w 16 mfgpt6 comparator 1 (mfgpt6_cmp1) 0000h page 489 32h r/w 16 mfgpt6 comparator 2 (mfgpt6_cmp2) 0000h page 490 34h r/w 16 mfgpt6 up counter (mfgpt6_cnt) 0000h page 491 36h r/w 16 mfgpt6 setup (mfgpt6_setup) 0000h page 492 38h r/w 16 mfgpt7 comparator 1 (mfgpt7_cmp1) 0000h page 489 3ah r/w 16 mfgpt7 comparator 2 (mfgpt7_cmp2) 0000h page 490 3ch r/w 16 mfgpt7 up counter (mfgpt7_cnt) 0000h page 491 3eh r/w 16 mfgpt7 setup (mfgpt7_setup) 0000h page 492 table 6-65. mfgpt native registers summary (continued) mfgpt i/o offset type width (bits) register name reset value reference msr address 51400028h ty p e r / w reset value 00000000h mfgpt_irq register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd mfgpt7_c2_irqm mfgpt6_c2_irqm mfgpt5_c2_irqm mfgpt4_c2_irqm mfgpt3_c2_irqm mfgpt2_c2_irqm mfgpt1_c2_irqm mfgpt0_c2_irqm mfgpt7_c1_irqm mfgpt6_c1_irqm mfgpt5_c1_irqm mfgpt4_c1_irqm mfgpt3_c1_irqm mfgpt2_c1_irqm mfgpt1_c1_irqm mfgpt0_c1_irqm mfgpt_irq bit descriptions bit name description 31:16 rsvd reserved. writes are don?t cares. 15 mfgpt7_c2_irqm enable mfgpt7 comparator 2 ou tput to the interrupt mapper . when set high, this input becomes one of two, ored together, to form ?unrestricted sources z?, bit 7. the other bit in the ored pair is bit 11, mfgpt3_c2_irqm. the unrestricted sources z are detailed in table 5-14 "irq map - unrestricted sources z" on page 113. when cleared low, this mfgpt output does not contribute to the unrestricted sources z interrupt. amd geode? cs5535 companion device data book 485 multi-function general purpose timer register descriptions 31506b 14 mfgpt6_c2_irqm enable mfgpt6 comparator 2 ou tput to the interrupt mapper. when set high, this input becomes one of two, ored together, to form ?unrestricted sources z?, bit 6. the other bit in the ored pair is bit 10, mfgpt2_c2_irqm. the unrestricted sources z are detailed in table 5-14 "irq map - unrestricted sources z" on page 113. when cleared low, this mfgpt output does not contribute to the unrestricted sources z interrupt. 13 mfgpt5_c2_irqm enable mfgpt5 comparator 2 ou tput to the interrupt mapper. when set high, this input becomes one of two, ored together, to form ?unrestricted sources z?, bit 5. the other bit in the ored pair is bit 9, mfgpt1_c2_irqm. the unrestricted sources z are detailed in table 5-14 "irq map - unrestricted sources z" on page 113. when cleared low, this mfgpt output does not contribute to the unrestricted sources z interrupt. 12 mfgpt4_c2_irqm enable mfgpt4 comparator 2 ou tput to the interrupt mapper. when set high, this input becomes one of two, ored together, to form ?unrestricted sources z?, bit 4. the other bit in the ored pair is bit 8, mfgpt0_c2_irqm. the unrestricted sources z are detailed in table 5-14 "irq map - unrestricted sources z" on page 113. when cleared low, this mfgpt output does not contribute to the unrestricted sources z interrupt. 11 mfgpt3_c2_irqm enable mfgpt3 comparator 2 ou tput to the interrupt mapper. when set high, this input becomes one of two, ored together, to form ?unrestricted sources z?, bit 7. the other bit in the ored pair is bit 15, mfgpt7_c2_irqm. the unrestricted sources z are detailed in table 5-14 "irq map - unrestricted sources z" on page 113. when cleared low, this mfgpt output does not contribute to the unrestricted sources z interrupt. 10 mfgpt2_c2_irqm enable mfgpt2 comparator 2 ou tput to the interrupt mapper. when set high, this input becomes one of two, ored together, to form ?unrestricted sources z?, bit 6. the other bit in the ored pair is bit 14, mfgpt6_c2_irqm. the unrestricted sources z are detailed in table 5-14 "irq map - unrestricted sources z" on page 113. when cleared low, this mfgpt output does not contribute to the unrestricted sources z interrupt. 9 mfgpt1_c2_irqm enable mfgpt1 comparator 2 ou tput to the interrupt mapper. when set high, this input becomes one of two, ored together, to form ?unrestricted sources z?, bit 5. the other bit in the ored pair is bit 13, mfgpt5_c2_irqm. the unrestricted sources z are detailed in table 5-14 "irq map - unrestricted sources z" on page 113. when cleared low, this mfgpt output does not contribute to the unrestricted sources z interrupt. 8 mfgpt0_c2_irqm enable mfgpt0 comparator 2 ou tput to the interrupt mapper. when set high, this input becomes one of two, ored together, to form ?unrestricted sources z?, bit 4. the other bit in the ored pair is bit 12, mfgpt4_c2_irqm. the unrestricted sources z are detailed in table 5-14 "irq map - unrestricted sources z" on page 113. when cleared low, this mfgpt output does not contribute to the unrestricted sources z interrupt. 7 mfgpt7_c1_irqm enable mfgpt7 comparator 1 ou tput to the interrupt mapper. when set high, this input becomes one of two, ored together, to form ?unrestricted sources z?, bit 3. the other bit in the ored pair is bit 3, mfgpt3_c1_irqm. the unrestricted sources z are detailed in table 5-14 "irq map - unrestricted sources z" on page 113. when cleared low, this mfgpt output does not contribute to the unrestricted sources z interrupt. mfgpt_irq bit descriptions bit name description 486 amd geode? cs5535 companion device data book multi-function general purpose timer register descriptions 31506b 6 mfgpt6_c1_irqm enable mfgpt6 comparator 1 ou tput to the interrupt mapper. when set high, this input becomes one of two, ored together, to form ?unrestricted sources z?, bit 2. the other bit in the ored pair is bit 2, mfgpt2_c1_irqm. the unrestricted sources z are detailed in table 5-14 "irq map - unrestricted sources z" on page 113. when cleared low, this mfgpt output does not contribute to the unrestricted sources z interrupt. 5 mfgpt5_c1_irqm enable mfgpt5 comparator 1 ou tput to the interrupt mapper. when set high, this input becomes one of two, ored together, to form ?unrestricted sources z?, bit 1. the other bit in the ored pair is bit 1, mfgpt1_c1_irqm. the unrestricted sources z are detailed in table 5-14 "irq map - unrestricted sources z" on page 113. when cleared low, this mfgpt output does not contribute to the unrestricted sources z interrupt. 4 mfgpt4_c1_irqm enable mfgpt4 comparator 1 ou tput to the interrupt mapper. when set high, this input becomes one of two, ored together, to form ?unrestricted sources z?, bit 0. the other bit in the ored pair is bit 0, mfgpt0_c1_irqm. the unrestricted sources z are detailed in table 5-14 "irq map - unrestricted sources z" on page 113. when cleared low, this mfgpt output does not contribute to the unrestricted sources z interrupt. 3 mfgpt3_c1_irqm enable mfgpt3 comparator 1 ou tput to the interrupt mapper. when set high, this input becomes one of two, ored together, to form ?unrestricted sources z?, bit 3. the other bit in the ored pair is bit 7, mfgpt7_c1_irqm. the unrestricted sources z are detailed in table 5-14 "irq map - unrestricted sources z" on page 113. when cleared low, this mfgpt output does not contribute to the unrestricted sources z interrupt. 2 mfgpt2_c1_irqm enable mfgpt2 comparator 1 ou tput to the interrupt mapper. when set high, this input becomes one of two, ored together, to form ?unrestricted sources z?, bit 2. the other bit in the ored pair is bit 6, mfgpt6_c1_irqm. the unrestricted sources z are detailed in table 5-14 "irq map - unrestricted sources z" on page 113. when cleared low, this mfgpt output does not contribute to the unrestricted sources z interrupt. 1 mfgpt1_c1_irqm enable mfgpt1 comparator 1 ou tput to the interrupt mapper. when set high, this input becomes one of two, ored together, to form ?unrestricted sources z?, bit 1. the other bit in the ored pair is bit 5, mfgpt5_c1_irqm. the unrestricted sources z are detailed in table 5-14 "irq map - unrestricted sources z" on page 113. when cleared low, this mfgpt output does not contribute to the unrestricted sources z interrupt. 0 mfgpt0_c1_irqm enable mfgpt0 comparator 1 ou tput to the interrupt mapper. when set high, this input becomes one of two, ored together, to form ?unrestricted sources z?, bit 0. the other bit in the ored pair is bit 4, mfgpt4_c1_irqm. the unrestricted sources z are detailed in table 5-14 "irq map - unrestricted sources z" on page 113. when cleared low, this mfgpt output does not contribute to the unrestricted sources z interrupt. mfgpt_irq bit descriptions bit name description amd geode? cs5535 companion device data book 487 multi-function general purpose timer register descriptions 31506b 6.17.1.2 mfgpt nmi and reset mask (mfgpt_nr) this register enables the mfgp t comparator 1 and 2 outputs to generate resets or nmis. msr address 51400029h ty p e r / w reset value 00000000h mfgpt_nr register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd mfgpt5_c2_rsten mfgpt4_c2_rsten mfgpt3_c2_rsten mfgpt2_c2_rsten mfgpt1_c2_rsten mfgpt0_c2_rsten rsvd nmi_leg mfgpt7_c2_nmim mfgpt6_c2_nmim mfgpt5_c2_nmim mfgpt4_c2_nmim mfgpt3_c2_nmim mfgpt2_c2_nmim mfgpt1_c2_nmim mfgpt0_c2_nmim mfgpt7_c1_nmim mfgpt6_c1_nmim mfgpt5_c1_nmim mfgpt4_c1_nmim mfgpt3_c1_nmim mfgpt2_c1_nmim mfgpt1_c1_nmim mfgpt0_c1_nmim mfgpt_nr bit descriptions bit name description 31:30 rsvd reserved. writes are don?t care; reads return 0. 29 mfgpt5_c2_rsten mfgpt5 comparator 2 reset enable. allow mfgpt5 comparator 2 output to cause a hard reset. 0: disable; 1: enable. 28 mfgpt4_c2_rsten mfgpt4 comparator 2 reset enable. allow mfgpt4 comparator 2 output to cause a hard reset. 0: disable; 1: enable. 27 mfgpt3_c2_rsten mfgpt3 comparator 2 reset enable. allow mfgpt3 comparator 2 output to cause a hard reset. 0: disable; 1: enable. 26 mfgpt2_c2_rsten mfgpt2 comparator 2 reset enable. allow mfgpt2 comparator 2 output to cause a hard reset. 0: disable; 1: enable. 25 mfgpt1_c2_rsten mfgpt1 comparator 2 reset enable. allow mfgpt1 comparator 2 output to cause a hard reset. 0: disable; 1: enable. 24 mfgpt0_c2_rsten mfgpt0 comparator 2 reset enable. allow mfgpt0 comparator 2 output to cause a hard reset. 0: disable; 1: enable. 23:17 rsvd reserved. writes are don?t care; reads return 0. 16 nmi_leg legacy nmi. allow legacy nmi mask bit (bit 7 of rtc register at i/o address 070h) to gate nmi. 0: disable; 1: enable. 15 mfgpt7_c2_nmim mfgpt7 comparator 2 nmi enable. allow mfgpt7 comparator 2 output to cause an nmi. 0: disable; 1: enable. 14 mfgpt6_c2_nmim mfgpt6 comparator 2 nmi enable. allow mfgpt6 comparator 2 output to cause an nmi. 0: disable; 1: enable. 13 mfgpt5_c2_nmim mfgpt5 comparator 2 nmi enable. allow mfgpt5 comparator 2 output to cause an nmi. 0: disable; 1: enable. 12 mfgpt4_c2_nmim mfgpt4 comparator 2 nmi enable. allow mfgpt4 comparator 2 output to cause an nmi. 0: disable; 1: enable. 11 mfgpt3_c2_nmim mfgpt3 comparator 2 nmi enable. allow mfgpt3 comparator 2 output to cause an nmi. 0: disable; 1: enable. 10 mfgpt2_c2_nmim mfgpt2 comparator 2 nmi enable. allow mfgpt2 comparator 2 output to cause an nmi. 0: disable; 1: enable. 9 mfgpt1_c2_nmim mfgpt1 comparator 2 nmi enable. allow mfgpt1 comparator 2 output to cause an nmi. 0: disable; 1: enable. 488 amd geode? cs5535 companion device data book multi-function general purpose timer register descriptions 31506b 6.17.1.3 mfgpt reserved (mfgpt_rsvd) this register is reserved. reads return 0. writes have no effect. 6.17.1.4 mfgpt clear se tup test (mfgpt_setup) 8 mfgpt0_c2_nmim mfgpt0 comparator 2 nmi enable. allow mfgpt0 comparator 2 output to cause an nmi. 0: disable; 1: enable. 7 mfgpt7_c1_nmim mfgpt7 comparator 1 nmi enable. allow mfgpt7 comparator 1 output to cause an nmi. 0: disable; 1: enable. 6 mfgpt6_c1_nmim mfgpt6 comparator 1 nmi enable. allow mfgpt6 comparator 1 output to cause an nmi. 0: disable; 1: enable. 5 mfgpt5_c1_nmim mfgpt5 comparator 1 nmi enable. allow mfgpt5 comparator 1 output to cause an nmi. 0: disable; 1: enable. 4 mfgpt4_c1_nmim mfgpt4 comparator 1 nmi enable. allow mfgpt4 comparator 1 output to cause an nmi. 0: disable; 1: enable. 3 mfgpt3_c1_nmim mfgpt3 comparator 1 nmi enable. allow mfgpt3 comparator 1 output to cause an nmi. 0: disable; 1: enable. 2 mfgpt2_c1_nmim mfgpt2 comparator 1 nmi enable. allow mfgpt2 comparator 1 output to cause an nmi. 0: disable; 1: enable. 1 mfgpt1_c1_nmim mfgpt1 comparator 1 nmi enable. allow mfgpt1 comparator 1 output to cause an nmi. 0: disable; 1: enable. 0 mfgpt0_c1_nmim mfgpt0 comparator 1 nmi enable. allow mfgpt0 comparator 1 output to cause an nmi. 0: disable; 1: enable. msr address 5140002ah ty p e r / w reset value 00000000h msr address 5140002bh ty p e w o reset value 00000000h mfgpt_setup register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd mfgpt_setup bit descriptions bit name description 31:0 rsvd reserved. these bits are reserved for internal testing only. these bits should not be written to. mfgpt_nr bit descriptions bit name description amd geode? cs5535 companion device data book 489 multi-function general purpose timer register descriptions 31506b 6.17.2 mfgpt native registers 6.17.2.1 mfgpt[x] comparator 1 (mfgpt[x]_cmp1) mfgpt0 to mfgpt5 cmp1 registers are in the working po wer domain while mfgpt6 and mfgpt7 cmp1 registers are in the standby power domain. mfgpt0 comparator 1 (mfgpt0_cmp1) mfgpt1 comparator 1 (mfgpt1_cmp1) mfgpt2 comparator 1 (mfgpt2_cmp1) mfgpt3 comparator 1 (mfgpt3_cmp1) mfgpt4 comparator 1 (mfgpt4_cmp1) mfgpt5 comparator 1 (mfgpt5_cmp1) mfgpt6 comparator 1 (mfgpt6_cmp1) mfgpt7 comparator 1 (mfgpt7_cmp1) mfgpt i/o offset 00h ty p e r / w reset value 0000h mfgpt i/o offset 08h ty p e r / w reset value 0000h mfgpt i/o offset 10h ty p e r / w reset value 0000h mfgpt i/o offset 18h ty p e r / w reset value 0000h mfgpt i/o offset 20h ty p e r / w reset value 0000h mfgpt i/o offset 28h ty p e r / w reset value 0000h mfgpt i/o offset 30h ty p e r / w reset value 0000h mfgpt i/o offset 38h ty p e r / w reset value 0000h mfgpt[x]_cmp1 register map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mfgpt_cmp1_val mfgpt[x]_cmp1 bit descriptions bit name description 15:0 mfgpt_cmp1_val comparator 1 comparison value. this 16-bit value is the compare value for comparator 1 of mfgpt[x]. 490 amd geode? cs5535 companion device data book multi-function general purpose timer register descriptions 31506b 6.17.2.2 mfgpt[x] comparat or 2 (mfgpt[x]_cmp2) mfgpt0 to mfgpt5 cmp2 registers are in the working po wer domain while mfgpt6 and mfgpt7 cmp2 registers are in the standby power domain. mfgpt0 comparator 2 (mfgpt0_cmp2) mfgpt1 comparator 2 (mfgpt1_cmp2) mfgpt2 comparator 2 (mfgpt2_cmp2) mfgpt3 comparator 2 (mfgpt3_cmp2) mfgpt4 comparator 2 (mfgpt4_cmp2) mfgpt5 comparator 2 (mfgpt5_cmp2) mfgpt6 comparator 2 (mfgpt6_cmp2) mfgpt7 comparator 2 (mfgpt7_cmp2) mfgpt i/o offset 02h ty p e r / w reset value 0000h mfgpt i/o offset 0ah ty p e r / w reset value 0000h mfgpt i/o offset 12h ty p e r / w reset value 0000h mfgpt i/o offset 1ah ty p e r / w reset value 0000h mfgpt i/o offset 22h ty p e r / w reset value 0000h mfgpt i/o offset 2ah ty p e r / w reset value 0000h mfgpt i/o offset 32h ty p e r / w reset value 0000h mfgpt i/o offset 3ah ty p e r / w reset value 0000h mfgpt[x]_cmp2 register map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mfgpt_cmp2_val mfgpt[x]_cmp2 bit descriptions bit name description 15:0 mfgpt_cmp2_val comparator 2 comparison value. this 16-bit value is the compare value for comparator 2 of mfgpt[x]. amd geode? cs5535 companion device data book 491 multi-function general purpose timer register descriptions 31506b 6.17.2.3 mfgpt[x] up co unter (mfgpt[x]_cnt) mfgpt0 to mfgpt5 up counter registers are in the worki ng power domain while mfgpt6 and mfgpt7 up counter reg- isters are in the standby power domain. mfgpt0 up coun ter (mfgpt0_cnt) mfgpt1 up coun ter (mfgpt1_cnt) mfgpt2 up coun ter (mfgpt2_cnt) mfgpt3 up coun ter (mfgpt3_cnt) mfgpt4 up counter (mfgpt4_cnt) mfgpt5 up counter (mfgpt5_cnt) mfgpt6 up counter (mfgpt6_cnt) mfgpt7 up counter (mfgpt7_cnt) mfgpt i/o offset 04h ty p e r / w reset value 0000h mfgpt i/o offset 0ch ty p e r / w reset value 0000h mfgpt i/o offset 14h ty p e r / w reset value 0000h mfgpt i/o offset 1ch ty p e r / w reset value 0000h mfgpt i/o offset 24h ty p e r / w reset value 0000h mfgpt i/o offset 2ch ty p e r / w reset value 0000h mfgpt i/o offset 34h ty p e r / w reset value 0000h mfgpt i/o offset 3ch ty p e r / w reset value 0000h mfgpt[x]_cnt register map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mfgpt_cnt mfgpt[x]_cnt bit descriptions bit name description 15:0 mfgpt_cnt up counter value. this register contains the current value of the counter of mfgpt[x}. hardware guarantees that reading or writing may be performed at any time without experiencing aliasing or ?intermediate-value? problems. 492 amd geode? cs5535 companion device data book multi-function general purpose timer register descriptions 31506b 6.17.2.4 mfgpt[x] setu p (mfgpt[x]_setup) mfgpt0 to mfgpt5 setup registers are in the working powe r domain while mfgpt6 and mfgpt7 setup registers are in the standby power domain. bits [11:0] are write-once; bit 12 is read-only. mfgpt0 setup (mfgpt0_setup) mfgpt1 setup (mfgpt1_setup) mfgpt2 setup (mfgpt2_setup) mfgpt3 setup (mfgpt3_setup) mfgpt4 setup (mfgpt4_setup) mfgpt5 setup (mfgpt5_setup) mfgpt6 setup (mfgpt6_setup) mfgpt7 setup (mfgpt7_setup) mfgpt i/o offset 06h ty p e r / w reset value 0000h mfgpt i/o offset 0eh ty p e r / w reset value 0000h mfgpt i/o offset 16h ty p e r / w reset value 0000h mfgpt i/o offset 1eh ty p e r / w reset value 0000h mfgpt i/o offset 26h ty p e r / w reset value 0000h mfgpt i/o offset 2eh ty p e r / w reset value 0000h mfgpt i/o offset 36h ty p e r / w reset value 0000h mfgpt i/o offset 3eh ty p e r / w reset value 0000h mfgpt[x]_setup register map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mfgpt_cnt_en mfgpt_cmp2 mfgpt_cmp1 mfgpt_setup mfgpt_stop_en mfgpt_ext_en mfgpt_cmp2 mode mfgpt_cmp1 mode mfgpt_rev_en mfgpt_clksel mfgpt_scale mfgpt[x]_setup bit descriptions bit name description 15 mfgpt_cnt_en counter enable. enable mfgpt for counting. 0: disable; 1: enable. 14 mfgpt_cmp2 compare 2 output status. if conditioning mode is set to event, writing this bit to a 1 clears the event until the next time compare 2 goes from low-to-high; reading returns the event status. for other modes, this bit follows current compare output values and writes to this bit have no effect. when compare 2 value is met, the counter is reset and counting continues. 13 mfgpt_cmp1 compare 1 output status. if conditioning mode is set to event, writing this bit to a 1 clears the event until the next time compare 1 goes from low-to-high; reading returns the event status. for other modes, this bit follows current compare output values and writes to this bit have no effect. when compare 2 value is met, count- ing stops. counter is reset and restarted only by external enable or dis- abling/enabling. 12 mfgpt_setup (ro) setup (read only). any value written to this bit is a ?don?t care?. from reset, this bit is low. if low, it indicates the mfgpt has not been setup and is currently dis- abled. on the first write to this register , bits [11:0] are established per the write and this bit is set to a 1. after this bit is set on the first write, bits [12:0] cannot be changed and subsequent wr ites are ?don?t care?. 11 mfgpt_stop_en stop enable (write once). enable counter to stop on sleep state for mfgpt0 to mfgpt5, or standby state for mfgpt6 and mfgpt7. 0: disable; 1: enable. amd geode? cs5535 companion device data book 493 multi-function general purpose timer register descriptions 31506b 10 mfgpt_ext_en external enable (write once). external pin enabled to be mfgpt clear input. 0: disable; 1: enable. 9:8 mfgpt_cmp2mode compare 2 mode (write once). 00: disable; output always low. 01: compare on equal; output high only on compare equal. 10: compare on ge; output high on compare greater than or equal. 11: event; same as ?compare on ge? but also can activate irq, nmi and reset. 7:6 mfgpt_cmp1mode compare 1 mode (write once). 00: disable; output always low. 01: compare on equal; output high only on compare equal. 10: compare on ge; output high on compare greater than or equal. 11: event; same as ?compare on ge? but also can activate irq, nmi and reset. 5mfgpt_rev_en reverse enable (write once). bit reverse enable for counter output to compare. 0: disable; 1: enable. 4 mfgpt_clksel clock select (write once). for mfgpt0 to mfgpt5 only; no effect on mfgpt6 and mfgpt7. 0: 32 khz clock. 1: 14.318 mhz clock 3:0 mfgpt_scale counter prescaler scale factor (write once). selects input clock divide-by value. 0000: 1 1000: 256 0001: 2 1001: 512 0010: 4 1010: 1024 0011: 8 1011: 2048 0100: 16 1100: 4096 0101: 32 1101: 8192 0110: 64 1110: 16384 0111: 128 1111: 32768 mfgpt[x]_setup bit descriptions (continued) bit name description 494 amd geode? cs5535 companion device data book power management controller register descriptions 31506b 6.18 power management contro ller register descriptions the registers for the power management controller (pmc) are divided into four sets: standard geodelink device (gld) msrs (shared with divil, see secti on 6.6.1 on page 317.) pmc specific msrs acpi registers pm support registers the msrs are accessed via the rdmsr and wrmsr pro- cessor instructions. the msr address is derived from the perspective of the cpu core. see section 4.2 "msr addressing" on page 59 for more details. all msrs are 64 bits, however, the pmc specific msrs (summarized in table 6-66) are called out as 32 bits. the pmc module treats writes to the upper 32 bits (i.e., bits [63:32]) of the 64-bit msrs as don?t cares and always returns 0 on these bits. the configuration registers associated with the pmc are divided into two categories: acpi registers (summarized in table 6-67) and pm support registers (summarized in table 6-68 on page 495): the acpi registers are a ccessed via base address register, msr_lbar_acpi (msr 5140000eh), as i/o offsets. (see section 6.6.2.7 on page 330 for bit descriptions of the base address register.) the pm support registers are accessed via a base address register, msr_lbar_pms (msr 5140000fh), as i/o offsets. (see section 6.6.2.8 on page 331 for bit descriptions of the base address register.) the reference column in the summary tables point to the page where the register maps and bit descriptions are listed. table 6-66. pmc specific msrs summary msr address type register name power domain reset value reference 51400050h r/w pmc logic timer (pmc_ltmr) working 00000000h page 496 51400051h r/w pmc reserved (pmc_rsvd) no f/flops 00000000h page 496 table 6-67. acpi registers summary acpi i/o offset type width (bits) register name power domain reset value reference 00h (word access only) r/w 16 pm status 1 (pm1_sts) (note 1 and note 2) note 1. required acpi register. note 2. both pm1_sts and pm1_en access offset 00h when using 32-bit access. only pm1_sts with a 16-bit access to offset 00h. only pm1_en with a 16-bit access to offset 02h. offset 04h is reserved. reads return 0. standby 0000h page 496 04h r/w 16 pm enable 1 (pm1_en) (note 1 and note 2) standby 0100h page 498 08h r/w 16 pm control 1 (pm1_cnt) (note 1 and note 3) note 3. ssmi may be implemented on this register by decode hardware outside of pm module. working 0000h page 499 0ch r/w 16 pm control 2 (pm2_cnt) (note 4) note 4. optional acpi register. ssmi may be implemented on th is register by decode hardware outside of pm module. working 0000h page 500 10h ro 32 pm timer (pm_tmr) (note 1) working 0000h page 500 14h r/w 32 pm reserved (pm_rsvd) no f/flops 0000h --- 18h r/w 32 general purpose events status 0 (pm_gpe0_sts) (note 5) note 5. required acpi register that can also be implemented via a control method. standby 00000000h page 501 1ch r/w 32 general purpose events enable 0 (pm_gpe0_en) (note 5) standby 00000000h page 503 amd geode? cs5535 companion device data book 495 power management controller register descriptions 31506b table 6-68. pm support registers summary pms i/o offset type width (bits) register name power domain reset value reference 00h r/w 16 pm sleep start delay (pm_ssd) working 0000h page 504 04h r/w 32 pm sleep control x assert delay and enable (pm_scxa) working 00000000h page 505 08h r/w 32 pm sleep control y assert delay and enable (pm_scya) working 00000000h page 505 0ch r/w 32 pm sleep output disable assert delay and enable (pm_out_slpctl) working 00000000h page 506 10h r/w 32 pm sleep clock delay and enable (pm_sclk) working 00000000h page 507 14h r/w 32 pm sleep end delay (pm_sed) working 00000000h page 507 18h r/w 32 pm sleep control x de-assert delay (pm_scxd) working 00000000h page 508 1ch r/w 32 pm sleep control y de-assert delay (pm_scyd) working 00000000h page 509 20h r/w 32 pm pci and ide input sleep control (pm_in_slpctl) working 00000000h page 510 24h-2ch r/w 32 pm reserved (pm_rsvd) (reads as 0.) no f/flops 00000000h --- 30h r/w 32 pm working de-assert delay and enable (pm_wkd) standby 00000000h page 511 34h r/w 32 pm working auxiliary de-assert delay and enable (pm_wkxd) standby 00000000h page 512 38h r/w 32 pm de-assert reset delay from standby (pm_rd) standby 40000100h page 513 3ch r/w 32 pm working auxiliary assert delay from standby wakeup (pm_wkxa) standby 00000000h page 513 40h r/w 32 pm fail-safe delay and enable (pm_fsd) standby 00000000h page 514 44h r/w 32 pm thermal-safe delay and enable (pm_tsd) standby 00000000h page 515 48h r/w 32 pm power-safe delay and enable (pm_psd) standby 00000000h page 515 4ch r/w 32 pm normal work delay and enable (pm_nwkd) standby 00000000h page 516 50h r/w 32 pm abnormal work delay and enable (pm_awkd) standby 00000000h page 517 54h r/w 32 pm standby status and control (pm_ssc) standby 00000001h page 517 58h-7fh r/w 32 pm reserved (pm_rsvd) (reads as 0.) no f/flops 00000000h --- 496 amd geode? cs5535 companion device data book power management controller register descriptions 31506b 6.18.1 pmc specific msrs 6.18.1.1 pmc logic timer (pmc_ltmr) 6.18.1.2 pmc reserved (pmc_rsvd) 6.18.2 acpi registers 6.18.2.1 pm status 1 (pm1_sts) pm1_sts is the status regi ster for timer carry, button, and rtc alarm wakeup events. all bits in this register are cleared by the standby state except bits 15, 10, and 8. they maintain their state through standby. this register must be accessed as word only. byte, non-aligned word, or dword access is not allowed. msr address 51400050h ty p e r / w reset value 00000000h pmc_ltmr register map 313029282726252423222120191817161514131211109876543210 msr_pml_tmr pmc_ltmr bit descriptions bit name description 31:0 msr_pml_tmr legacy power management timer. 32-bit write / read of timer counter. writes initialize the counter value; reads return current timer counter value. msr address 51400051h ty p e r / w reset value 00000000h pmc_rsvd register map 313029282726252423222120191817161514131211109876543210 pmc_rsvd pmc_rsvd bit descriptions bit name description 31:0 pmc_rsvd reserved. this is a reserved register and should not be accessed by user software. by convention write 0, but other values are ?don?t care?. reads always return 0. acpi i/o offset 00h (word access only) ty p e r / w reset value 0000h pm1_sts register map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wak_flag rsvd ignore rtc_flag slpbtn_flag pwrbtn_flag rsvd gbl_flag bm_flag rsvd tmr_flag amd geode? cs5535 companion device data book 497 power management controller register descriptions 31506b pm1_sts bit descriptions bit name description 15 wak_flag (note 1, note 2) note 1. a wakeup event can come from any event enabled by pm1_en (acpi i/o offset 02h) or pm_gpe0_en (acpi i/o offset 1ch). a wakeup will occur even if the sci is not mapped to an asmi or irq. note 2. after starting a sleep sequence, software would norma lly spin by entering a polling loop on the wak_flag. this bit is normally (software has cleared it from last sle ep) 0 before starting a sleep sequence. the sleep sequence puts the processor in suspend while it is spinning. w hen the sequence brings the processor out of suspend, the wak_flag bit is set. the sleep sequence starts when slp_en (acpi i/o offset 08h[13]) is written to a 1. wakeup event flag. this bit is set high by the hardware when any wakeup event occurs. write 1 to clear; writing 0 has no effect. 14:12 rsvd reserved. by convention write 0, but other values are ?don?t care?. reads always return 0. 11 ignore ignore. by acpi convention not used by software. reads always return 0. to support the global status lock flag bit, writing a 1 to this bit sets bit 5. writing a 0 has no effect. 10 rtc_flag real-time clock alarm flag. this bit is set high by the hardware when the rtc gen- erates an alarm. if rtc_en (acpi i/o off set 02h[10]) is high, an sci is generated. write 1 to clear; writing 0 has no effect. 9 slpbtn_flag sleep button flag. this bit is set high by the hardware when the ?sleep button? is pushed. if slpbtn_en (acpi i/o offset 02h[ 9]) is high, an sci is generated. write 1 to clear; writing 0 has no effect. 8pwrbtn_flag power button flag. this bit is set high by the hardware when the ?power button? is pushed. if pwrbtn_en (acpi i/o offset 02h[ 8]) is high, an sci is generated. write 1 to clear; writing 0 has no effect. 7:6 rsvd reserved. by convention write 0, but other values are ?don?t care?. reads always return 0. 5gbl_flag global lock flag. if high, indicates that the bios released control of global lock sta- tus bit. this bit is cleared by writing a 1 to it. this bit is set by writing a 1 to bit 11 (ignore). if glb_en (acp i i/o offset 02h[5]) is high, an sci is generated. 4bm_flag bus master flag. this bit indicates a master has requested the bus. used to indicate a possible incoherent cache when the processor is in state c3. this function is not sup- ported because the geode cs5535 companion device does not support the c3 state. by convention write 0, but other values are ?don?t care?. reads return 0. 3:1 rsvd reserved. by convention write 0, but other values are ?don?t care?. reads always return 0. 0tmr_flag timer carry flag . this bit is set high by the har dware anytime the power management timer rolls over from all 1s back to 0. if tmr_en (acpi i/o offset 02h[0]) is high, an sci is generated when the rollover occurs. write 1 to clear; writing 0 has no effect. 498 amd geode? cs5535 companion device data book power management controller register descriptions 31506b 6.18.2.2 pm enable 1 (pm1_en) pm1_en is the enable register for timer carry, button, and rt c alarm wakeup events. all bits in this register are cleared by the standby state except bits 10 and 8. they maintain their state through standby. all bits in this register return the valu e written when read, except for the reserved bits. if enabled, any of the scis cause a wakeup event if the system state is sleep or st andby (except tmr and gbl). acpi i/o offset 04h ty p e r / w reset value 0100h pm1_en register map 1514131211109 8 76543210 rsvd rtc_en slpbtn_en pwrbtn_en rsvd glb_en rsvd tmr_en pm1_en bit descriptions bit name description 15:11 rsvd reserved. by convention write 0, but other values are ?don?t care?. reads return 0 value. 10 rtc_en real-time clock sci enable. enables generating an sci when rtc_flag (acpi i/o offset 00h[10]) gets set. also enables wakeup from this event. 0: disable; 1: enable. 9 slpbtn_en sleep button sci enable. enables generating an sci when slpbtn_flag (acpi i/o offset 00h[9]) gets set. also enables wakeup from this event. 0: disable; 1: enable. 8 pwrbtn_en power button sci enable. enables generating an sci when pwrbtn_flag (acpi i/o offset 00h[8]) gets set. also enables wakeup from this event. 0: disable; 1: enable (default). 7:6 rsvd reserved. by convention write 0, but other values are ?don?t care?. reads return 0 value. 5 glb_en global enable. enables generating an sci when gl b_flag (acpi i/o offset 00h[5]) gets set. there is no wakeup concept fo r this event. 0: disable; 1: enable. 4:1 rsvd reserved. by convention write 0, but other values are ?don?t care?. reads return 0 value. 0tmr_en timer sci enable. enables generating an sci when tmr_flag (acpi i/o offset 00h[0]) gets set. there is no wakeup conc ept for this event 0: disable; 1: enable. amd geode? cs5535 companion device data book 499 power management controller register descriptions 31506b 6.18.2.3 pm control 1 (pm1_cnt) pm1_cnt is the control register for global and the sleep state settings. acpi i/o offset 08h ty p e r / w reset value 0000h pm1_cnt register map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd slp_en slp_typx ignore rsvd gbl_rls bm_rld sci_en pm1_cnt bit descriptions bit name description 15:14 rsvd reserved. by convention write 0, but other values are ?don?t care?. reads always return 0. 13 slp_en (wo) sleep enable (write only). this is a write-only bit and reads to it always return 0. set- ting this bit causes the system to sequence into the sleep state defined by slp_typx (bits [12:10]). after the delay in slp_delay (pms i/o offse t 00h[11:0]), the system state begins the move from working to sleeping or standby state. the sleep request/sleep acknowl- edge sequenced is started. the sequence ma y be aborted by writing slp_en_indic (pms i/o offset 00h[15]). 12:10 slp_typx sleep type. defines the type of sleep state the system enters when slp_en (bit 13) is set to 1. reads always return the value written. these bits do not directly af fect the internal hardware, but are required by the acpi specification. when th is register is accessed, vsa code traps the access and transfers bits written here to the appropriate loca tions to set up the desired power management mode. the sleep type is directly controlled by glcp settings, individual geodelink device power management msr settings, and pml settings. 9 ignore ignore. by convention not used by acpi software. software always writes 0. if a 1 was written to bit 2 (gbl_rls), this bit is set, that is, a read of this bit returns a 1. write 1 to clear; writing 0 has no effect. 8:3 rsvd reserved. by convention write 0, but other values are ?don?t care?. reads always return 0. 2 gbl_rls global lock release. this is the ?release of global lock? bit. the acpi driver writes this bit to a 1 to rise an event to the bios. the write indicates the release of global lock. reads always return 0. writing a 1 to this bit sets bit 9 (ignore). 1bm_rld bus master rld. when high, this bit allows the ge neration of a bus master request to cause any processor in the c3 state to transition to the c0 state. reads return the value written. in the geode cs5535 companion device, the c3 state is not supported. other than serving as an indicator, this bit does nothing. 0sci_en sci enable. when low, indicates native power management mode. when high, indi- cates acpi mode. reads return the value wr itten. other than serving as an indicator, this bit does not directly affect the hardware. 500 amd geode? cs5535 companion device data book power management controller register descriptions 31506b 6.18.2.4 pm control 2 (pm2_cnt) pm2_cnt is the control r egister for enabling/disabling the system arbiter. this register is not implemented. writes ?don?t care. reads return 0. this register may be accessed with 8-bit or 16-bit i/o. 6.18.2.5 pm timer (pm_tmr) pm_tmr is the data value register for the 32 -bit timer running from the 3.579 mhz clock. acpi i/o offset 0ch ty p e r / w reset value 0000h pm2_cnt register map 1514131211109876543210 rsvd rsvd arb_ dis pm2_cnt bit descriptions bit name description 15:8 rsvd reserved. acpi defines this as an 8-bit register. it has been extended so that all pml registers are at least 16 bits. writes to these bits are a ?don?t care?. reads always return 0. 7:1 rsvd reserved. by convention write 0, but other values are ?don?t care?. reads return 0 value. 0arb_dis system arbiter disable . disables when high. reads return value written. this bit is required by the acpi specification, but internally is not connected to any pm logic. acpi i/o offset 10h ty p e r o reset value 00000000h pm_tmr register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr_val pm_tmr bit descriptions bit name description 31:0 tmr_val (ro) timer value (read only). this read only counter is driven by the 3.579545 mhz clock. writes are always a ?don?t care?. the counter runs continuously as long as the system is in the working state; otherwise, counting is stopped. it stops counting when susp# is asserted and starts counting when suspa# has been de-asserted after having been asserted. the value in this reg- ister is lost in the standby state. amd geode? cs5535 companion device data book 501 power management controller register descriptions 31506b 6.18.2.6 general purpose even ts status 0 (pm_gpe0_sts) pm_gpe0_sts is the status register for general purpose ev ents. status events are cleared by writing a 1 to the appropriate flag bit. writing 0 has no effect. by convention, bits [23:0] are asso ciated with the working domain while bits [31:24] are associated with standby domain. during standby, bits [23:0] are unconditionally cl eared. these events are all individually enabled and then ored together to form the system control interrupt (sci). acpi i/o offset 18h ty p e r / w reset value 00000000h pm_gpe0_sts register map 313029282726252423222120191817161514131211109876543210 gpiom7_pme_flag gpiom6_pme_flag rsvd gpiom5_pme_flag gpiom4_pme_flag gpiom3_pme_flag gpiom2_pme_flag gpiom1_pme_flag gpiom0_pme_flag rsvd usbc2_pme_flag usbc1_pme_flag uart2_pme_flag uart1_pme_flag smb+pme_flag pic_asmi_pme_flag pic_irq_pme_flag pm_gpe0_sts bit descriptions bit name description 31 gpiom7_pme_ flag gpio irq/pme mapper bit 7 pme flag . if high, this bit records that a pme occurred via bit 7 of the gpio irq/pme mapper. both this bit and the corresponding enable bit in pm_gpe0_en (acpi i/o offset 1ch[31]) must be high in order for this pme to be passed on to the system. write 1 to clear; writing 0 has no effect. 30 gpiom6_pme_ flag gpio irq/pme mapper bit 6 pme flag. if high, this bit records that a pme occurred via bit 6 of the gpio irq/pme mapper. both this bit and the corresponding enable bit in pm_gpe0_en (acpi i/o offset 1ch[30]) must be high in order for this pme to be passed on to the system. write 1 to clear; writing 0 has no effect. 29:22 rsvd reserved. reads return 0; writes have no effect 21 gpiom5_pme_ flag gpio irq/pme mapper bit 5 pme flag. if high, this bit records that a pme occurred via bit 5 of the gpio irq/pme mapper. both this bit and the corresponding enable bit in pm_gpe0_en (acpi i/o offset 1ch[21]) must be high in order for this pme to be passed on to the system. write 1 to clear, writing 0 has no effect. 20 gpiom4_pme_ flag gpio irq/pme mapper bit 4 pme flag. if high, this bit records that a pme occurred via bit 4 of the gpio irq/pme mapper. both this bit and the corresponding enable bit in pm_gpe0_en (acpi i/o offset 1ch[20]) must be high in order for this pme to be passed on to the system. write 1 to clear; writing 0 has no effect. 19 gpiom3_pme_ flag gpio irq/pme mapper bit 3 pme flag. if high, this bit records that a pme occurred via bit 3 of the gpio irq/pme mapper. both this bit and the corresponding enable bit in pm_gpe0_en (acpi i/o offset 1ch[19]) must be high in order for this pme to be passed on to the system. write 1 to clear; writing 0 has no effect. 18 gpiom2_pme_ flag gpio irq/pme mapper bit 2 pme flag. if high, this bit records that a pme occurred via bit 2 of the gpio irq/pme mapper. both this bit and the corresponding enable bit in pm_gpe0_en (acpi i/o offset 1ch[18]) must be high in order for this pme to be passed on to the system. write 1 to clear; writing 0 has no effect. 17 gpiom1_pme_ flag gpio irq/pme mapper bit 1 pme flag. if high, this bit records that a pme occurred via bit 1 of the gpio irq/pme mapper. both this bit and the corresponding enable bit in pm_gpe0_en (acpi i/o offset 1ch[17]) must be high in order for this pme to be passed on to the system. write 1 to clear; writing 0 has no effect. 502 amd geode? cs5535 companion device data book power management controller register descriptions 31506b 16 gpiom0_pme_ flag gpio irq/pme mapper bit 0pme flag. if high, this bit record s that a pme occurred via bit 0 of the gpio irq/pme mapper. both this bit and the corresponding enable bit in pm_gpe0_en (acpi i/o offset 1ch[16]) must be high in order for this pme to be passed on to the system. write 1 to clear; writing 0 has no effect. 15:7 rsvd reserved. reads return 0; writes have no effect 6 usbc2_pme_ flag usb controller #2 pme flag. if high, this bit records th at a pme occurred via usb controller #2. both this bit and the corresponding enable bit in pm_gpe0_en (acpi i/o offset 1ch[6]) must be high in order fo r this pme to be passed on to the system. write 1 to clear; writing 0 has no effect. 5 usbc1_pme_ flag usb controller #1 pme flag. if high, this bit records th at a pme occurred via usb controller #1. both this bit and the corresponding enable bit in pm_gpe0_en (acpi i/o offset 1ch[5]) must be high in order fo r this pme to be passed on to the system. write 1 to clear; writing 0 has no effect. 4 uart2_pme_ flag uart #2 pme flag. if high, this bit records that a pme occurred via uart #2. both this bit and the corresponding enable bit in pm_gpe0_en (acpi i/o offset 1ch[4]) must be high in order for this pme to be pa ssed on to the system. writ e 1 to clear; writ- ing 0 has no effect. 3 uart1_pme_ flag uart #1 pme flag. if high, this bit records that a pme occurred via uart #1. both this bit and the corresponding enable bit in pm_gpe0_en (acpi i/o offset 1ch[3]) must be high in order for this pme to be pa ssed on to the system. writ e 1 to clear; writ- ing 0 has no effect. 2 smb_pme_ flag smb pme flag. if high, this bit records that a pme occurred via the smb. both this bit and the corresponding enable bit in pm_gpe0_en (acpi i/o offset 1ch[2]) must be high in order for this pme to be passed on to the system. write 1 to clear; writing 0 has no effect. 1 pic_asmi_pme_ flag pic asmi pme flag. if high, this bit records that a pme occurred due to a pic asmi. both this bit and the corresponding enable bit in pm_gpe0_en (acpi i/o offset 1ch[1]) must be high in order for this pme to be passed on to the system. write 1 to clear; writing 0 has no effect. 0 pic_irq_pme_ flag pic interrupt pme flag. if high, this bit records that a pme occurred due to a pic interrupt. both this bit and the corresponding enable bit in pm_gpe0_en (acpi i/o offset 1ch[0]) must be high in order for th is pme to be passed on to the system. write 1 to clear; writing 0 has no effect. pm_gpe0_sts bit descriptions bit name description amd geode? cs5535 companion device data book 503 power management controller register descriptions 31506b 6.18.2.7 general purpose even ts enable 0 (pm_gpe0_en) pm_gpe0_en is the enable register for general purpose events. reads always return the value written. by convention, bits [23:0] are associated with the working domain while bits [31:24] are associated with the standby domain. during standby, bits [23:0] are unconditional ly cleared. pme status can be read via the corresponding flag bit in the pm_gpe0_sts register (acpi i/o offset 18h). acpi i/o offset 1ch ty p e r / w reset value 00000000h pm_gpe0_en register map 313029282726252423222120191817161514131211109876543210 gpiom7_pme_en gpiom6_pme_en rsvd gpiom5_pme_en gpiom4_pme_en gpiom3_pme_en gpiom2_pme_en gpiom1_pme_en gpiom0_pme_en rsvd usbc2_pme_en usbc1_pme_en uart2_pme_en uart1_pme_en smb+pme_en pic_asmi_pme_en pic_irq_pme_en pm_gpe0_en bit descriptions bit name description 31 gpiom7_pme_ en gpio irq/pme mapper bit 7 pme enable. when set high, this bit enables the gener- ation of a pme to the system if a pme occurs via bit 7 of the gpio irq/pme mapper. write this bit low to disable the generation of a pme from this source. 30 gpiom6_pme_ en gpio irq/pme mapper bit 6 pme enable. when set high, this bit enables the gener- ation of a pme to the system if a pme occurs via bit 6 of the gpio irq/pme mapper. write this bit low to disable the generation of a pme from this source. 29:22 rsvd reserved. reads return 0; writes have no effect 21 gpiom5_pme_ en gpio irq/pme mapper bit 5 pme enable. when set high, this bit enables the gener- ation of a pme to the system if a pme occurs via bit 5 of the gpio irq/pme mapper. write this bit low to disable the generation of a pme from this source. 20 gpiom4_pme_ en gpio irq/pme mapper bit 4 pme enable. when set high, this bit enables the gener- ation of a pme to the system if a pme occurs via bit 4 of the gpio irq/pme mapper. write this bit low to disable the generation of a pme from this source. 19 gpiom3_pme_ en gpio irq/pme mapper bit 3 pme enable. when set high, this bit enables the gener- ation of a pme to the system if a pme occurs via bit 3 of the gpio irq/pme mapper. write this bit low to disable the generation of a pme from this source. 18 gpiom2_pme_ en gpio irq/pme mapper bit 2 pme enable. when set high, this bit enables the gener- ation of a pme to the system if a pme occurs via bit 2 of the gpio irq/pme mapper. write this bit low to disable the generation of a pme from this source. 17 gpiom1_pme_ en gpio irq/pme mapper bit 1 pme enable. when set high, this bit enables the gener- ation of a pme to the system if a pme occurs via bit 1 of the gpio irq/pme mapper. write this bit low to disable the generation of a pme from this source. 16 gpiom0_pme_ en gpio irq/pme mapper bit 0 pme enable. when set high, this bit enables the gener- ation of a pme to the system if a pme occurs via bit 0 of the gpio irq/pme mapper. write this bit low to disable the generation of a pme from this source. 15:7 rsvd reserved. reads return 0; writes have no effect 6 usbc2_pme_en usb controller #2 pme enable. when set high, this bit enables the generation of a pme to the system if a pme occurs via usb co ntroller #2. write this bit low to disable the generation of a pme from this source. 5 usbc1_pme_en usb controller #1pme enable. when set high, this bit enables the generation of a pme to the system if a pme occurs via usb co ntroller #2. write this bit low to disable the generation of a pme from this source. 504 amd geode? cs5535 companion device data book power management controller register descriptions 31506b 6.18.3 pm support registers the registers listed in this sub-section are not acpi regi sters, but are used to support power management implementation. 6.18.3.1 pm sleep st art delay (pm_ssd) 4 uart2_pme_en uart #2 pme enable. when set high, this bit enables the generation of a pme to the system if a pme occurs via uart #2. write th is bit low to disabl e the generation of a pme from this source. 3 uart1_pme_en uart #1 pme enable. when set high, this bit enables the generation of a pme to the system if a pme occurs via uart #2. write th is bit low to disabl e the generation of a pme from this source. 2 smb_pme_en smb pme enable. when set high, this bit enables the generation of a pme to the sys- tem if a pme occurs via the smb. write this bit low to disable the generation of a pme from this source. 1 pic_asmi_pme_ en pic asmi pme enable. when set high, this bit enables the generation of a pme to the system if a pme occurs due to a pic asmi. wr ite this bit low to disable the generation of a pme from this source. 0 pic_irq_pme_ en pic interrupt pme enable. when set high, this bit enables the generation of a pme to the system if a pme occurs due to a pic inte rrupt. write this bit low to disable the gen- eration of a pme from this source pm_gpe0_en bit descriptions (continued) bit name description pms i/o offset 00h ty p e r / w reset value 0000h pm_ssd register map 1514131211109876543210 slp_en_indic rsvd slp_wrt_en slp_delay_en slp_delay pm_ssd bit descriptions bit name description 15 slp_en_indic sleep enable indicator. if slp_en (acpi i/o offset 08h[13]) was written to a 1, then this bit reads high. if this bit is written to a 1, the sleep sequence is aborted. writing a 0 to this bit has no effect. this bit always clears on a sleep or standby wakeup. 14 rsvd reserved. by convention write 0. reads return value written. 13 slp_wrt_en sleep write enable. must be high in order to change bits 12 and [11:0] (slp_delay_en and slp_delay). reads of this bit always return 0. 12 slp_delay_en sleep delay enable. must be high to enable the de lay specified in bits [11:0] (slp_delay). reads return value written. 11:0 slp_delay sleep delay. indicates the number of 3.57954 mhz clock edges to wait before begin- ning the sleep or standby process as defined by slp_en (acpi i/o offset 08h[13]). bit 12 (slp_delay_en) must be high to enable this delay. reads return the value writ- ten. amd geode? cs5535 companion device data book 505 power management controller register descriptions 31506b 6.18.3.2 pm sleep control x assert delay and enable (pm_scxa) reads always return the value written. 6.18.3.3 pm sleep control y assert delay and enable (pm_scya) reads always return the value written. pms i/o offset 04h ty p e r / w reset value 00000000h pm_scxa register map 313029282726252423222120191817161514131211109876543210 rsvd slpx_en slpx_delay pm_scxa bit descriptions bit name description 31 rsvd reserved. by convention write 0, but may write anything. 30 slpx_en sleep x assert and delay enable. must be high to assert the sleep_x ball and to enable its assert delay specified in bits [29:0] (slpx_delay). 29:0 slpx_delay sleep x assert delay. indicates the number of 3.57954 mhz clock edges to wait from the assertion of suspa# before asserting the sleep_x ball. bit 30 (slpx_en) must be high to enable this delay. sleep_x is not allowed to assert if this delay is larger than slpclk_delay (pms i/o offset 10h[29:0]). this is only true if slpclk_en is enabled (pms i/o offset 10h[30] = 1). pms i/o offset 08h ty p e r / w reset value 00000000h pm_scya register map 313029282726252423222120191817161514131211109876543210 rsvd slpy_en slpy_delay pm_scya bit descriptions bit name description 31 rsvd reserved. by convention write 0, but may write anything. 30 slpy_en sleep y assert and delay enable. must be high to assert sleep_y and enable its assert delay specified in bits [29:0] (slpy_delay). 29:0 slpy_delay sleep y assert delay. indicates the number of 3.57954 mhz clock edges to wait from the assertion of suspa# before asserting the sleep_y ball. bit 30 (slpy_en) must be high to enable this delay. sleep_y is not allowed to assert if this delay is larger than slpclk_delay (pms i/o offset 10h[29:0]). this is only true if slpclk_en is enabled (pms i/o offset 10h[30] = 1). 506 amd geode? cs5535 companion device data book power management controller register descriptions 31506b 6.18.3.4 pm sleep outp ut disable assert delay and enable (pm_out_slpctl) reads always return the value written. pms i/o offset 0ch ty p e r / w reset value 00000000h pm_out_slpctl register map 313029282726252423222120191817161514131211109876543210 rsvd pci_ide_out_slp pci_ide_out_slp_delay pm_out_slpctl bit descriptions bit name description 31 rsvd reserved. by convention write 0, but may write anything. 30 pci_ide_out_ slp pci/ide output sleep control. allows the delay specified in bits [29:0] (pci_ide_out_slp_delay) to turn off pci/ide outputs as listed in table 4-11 "sleep driven pci signals" and table 4-12 "sleep driven ide signals" on page 79. individual enables exist for pci (pci gld_msr_pm, msr 51000004h[49:48]) and ide (ide gld_msr_pm, msr 51300004h[49: 48]). output control immediately enables the pci/ide outputs when susp# de-asserts. 0: disable. 1: enable. 29:0 pci_ide_out_ slp_delay pci/ide output sleep control delay. indicates the number of 3.57954 mhz clock edges to wait from sleep wakeup before pci/ide outputs are disabled. bit 30 (pci_ide_out_slp) must be high to enable this delay. the pci/ide outputs will not turn off if this delay is larger than slpclk_delay (pms i/o offset 10h[29:0]). this is only true if slpclk_en is enabled (pms i/o offset 10h[30] = 1). amd geode? cs5535 companion device data book 507 power management controller register descriptions 31506b 6.18.3.5 pm sleep clock delay and enable (pm_sclk) reads always return the value written. 6.18.3.6 pm sleep en d delay (pm_sed) reads always return the value written. pms i/o offset 10h ty p e r / w reset value 00000000h pm_sclk register map 313029282726252423222120191817161514131211109876543210 rsvd slpclk_en slpclk_delay pm_sclk bit descriptions bit name description 31 rsvd reserved. by convention write 0, but may write anything. 30 slpclk_en sleep clock delay enable. must be high to assert slp_clk_en# and enable its assert delay specified in bits [29:0] (slp clk_delay). use of this control is required but not sufficient to enter the standby state. warning : using this control immediately turns off all system clocks except the 32 khz rtc clock. 29:0 slpclk_delay sleep clock assert delay. indicates the number of 3.57954 mhz clock edges to wait from the assertion of suspa# before asserting slp_clk_en#. bit 30 (slpclk_en) must be high to enable this delay. there is not a de-assert delay. the wakeup event causes slp_clk_en# to de- assert combinatorially from the wakeup event. this event is called sleep wakeup. the concept of a sleep wakeup applies even if sleep clock is not used. pms i/o offset 14h ty p e r / w reset value 00000000h pm_sed register map 313029282726252423222120191817161514131211109876543210 rsvd slpend_en slpend_delay 508 amd geode? cs5535 companion device data book power management controller register descriptions 31506b 6.18.3.7 pm sleep control x de-assert delay (pm_scxd) reads always return the value written. pm_sed bit descriptions bit name description 31 rsvd reserved. by convention write 0, but may write anything. 30 slpend_en sleep end delay enable. must be high to enable the de lay specified in bits [29:0] (slpend_delay). 29:0 slpend_delay sleep end delay. indicates the number of 3.57954 mhz clock edges to wait from sleep wakeup before de-asserting susp#. bit 30 (slpend_en) must be high to enable this delay. if pci_ide_in_slp is not enabled (pms i/o offset 20h[30] = 0) or the delay is less than slpend_delay, susp# de-asserts at the same time the pci/ide inputs are re- enabled. pms i/o offset 18h ty p e r / w reset value 00000000h pm_scxd register map 313029282726252423222120191817161514131211109876543210 rsvd slpx_end_en slpx_end_delay pm_scxd bit descriptions bit name description 31 rsvd reserved. by convention write 0, but may write anything. 30 slpx_end_en sleep x de-assert and delay enable. must be high to de-assert sleep_x and enable the delay specified in bi ts [29:0] (slpx_end_delay). 29:0 slpx_end_ delay sleep x de-assert delay. indicates the number of 3.57954 mhz clock edges to wait from sleep wakeup before de-asserti ng the sleep_x ball. bit 30 (slpx_end_en) must be high to enable this delay. if pci_ide_in_slp is not enabled (pms i/ o offset 20h[30] = 0) or is less than the slpx_end_delay, sleep_x de-asserts at the same time the pci /ide inputs are re- enabled. amd geode? cs5535 companion device data book 509 power management controller register descriptions 31506b 6.18.3.8 pm sleep control y de-assert delay (pm_scyd) reads always return the value written. pms i/o offset 1ch ty p e r / w reset value 00000000h pm_scyd register map 313029282726252423222120191817161514131211109876543210 rsvd slpy_end_en slpy_end_delay pm_scyd bit descriptions bit name description 31 rsvd reserved. by convention write 0, but may write anything. 30 slpy_end_en sleep y de-assert and delay enable. must be high to de-assert sleep_y and enable the delay specified in bi ts [29:0] (slpy_end_delay). 29:0 slpy_end_ delay sleep control y de-assert delay. indicates the number of 3.57954 mhz clock edges to wait from sleep wakeup before de-asserting the sleep_y ball. bit 30 (slpy_end_en) must be high to enable this delay. if pci_ide_in_slp is not enabled (pms i/ o offset 20h[30] = 0) or is less than the slpy_end_delay, sleep_y de-asserts at the same time the pci/ide inputs are re- enabled. 510 amd geode? cs5535 companion device data book power management controller register descriptions 31506b 6.18.3.9 pm pci and ide input sleep control (pm_in_slpctl) reads always return the value written. pms i/o offset 20h ty p e r / w reset value 00000000h pm_in_slpctl register map 313029282726252423222120191817161514131211109876543210 rsvd pci_ide_in_slp pci_ide_in_slp_delay pm_in_slpctl bit descriptions bit name description 31 rsvd reserved. by convention write 0, but may write anything. 30 pci_ide_in_slp pci/ide input sleep control. allows the delay specified in bits [29:0] (pci_ide_in_slp_delay) to turn off pci/ide inputs as listed in table 4-11 "sleep driven pci signals" and table 4-12 "sleep driven ide signals" on page 79. individual enables exist for pci (pci gld_msr_pm, msr 51000004h[49:48]) and ide (ide gld_msr_pm, msr 51300004h[49:48]). 0: disable. 1: enable. 29:0 pci_ide_in_slp _delay pci/ide input sleep control delay. indicates the number of 3.57954 mhz clock edges to wait from sleep wakeup before pci/ide inputs are disabled. bit 30 (pci_ide_in_slp) must be high to enable this delay. amd geode? cs5535 companion device data book 511 power management controller register descriptions 31506b 6.18.3.10 pm working de-assert delay and enable (pm_wkd) reads always return the value writte n, except for rsvd bits [29:20]. pms i/o offset 30h ty p e r / w reset value 00000000h pm_wkd register map 313029282726252423222120191817161514131211109876543210 rsvd working_deassert_en rsvd working_deassert_delay pm_wkd bit descriptions bit name description 31 rsvd reserved. by convention write 0, but may write anything. 30 working_ deassert_en working de-assert and delay enable. must be high to de-assert the working out- put and to enable its delay specified in bits [19:0] (working_deassert_delay). use of this control implies a system sequ ence into the standby state. the pmc dis- ables its interfaces to non-standby portions of the component and only considers wakeup events from standby circuits. the pmc also immediately asserts system reset when slp_clk_en# is asserted regardless of the value of working_deassert_delay (bits [19:0]). reset remains asserted throughout the standby state. there is not an assert delay. the wakeup event causes the working output to assert. this event is called standby wakeup. on wakeup, reset will continue to be applie d to all non-standby circuits for the length of time specified in the reset_d elay (pms i/o of fset 38h[19:0]). enabling this function and/or the function in pm_wkxd (pms i/o offset 34h[30] = 1) causes the same standby state events. standby state is not entered unless slp_clk_en# is asserted. 29:20 rsvd reserved. by convention write 0, but may write anything. reads return 0. 19:0 working_ deassert_ delay working de-assert delay. indicates the number of 32 khz clock edges to wait from the assertion of slp_clk_en# before de-asserting the working output. bit 30 (working_deassert_en) must be high to enable this delay. 512 amd geode? cs5535 companion device data book power management controller register descriptions 31506b 6.18.3.11 pm working auxiliary de- assert delay and enable (pm_wkxd) reads always return the value writte n, except for rsvd bits [29:20]. pms i/o offset 34h ty p e r / w reset value 00000000h pm_wkxd register map 313029282726252423222120191817161514131211109876543210 rsvd work_aux_deassert_en rsvd work_aux_deassert_delay pm_wkxd bit descriptions bit name description 31 rsvd reserved. by convention write 0, but may write anything. 30 work_aux_ deassert_en working auxiliary de-assert and delay enable. must be high to de-assert the work_aux output and enable its delay specified in bits [19:0] (work_aux_deassert_delay). use of this control implies a system sequ ence into the standby state. the pmc dis- ables its interfaces to non-standby portions of the component and only considers wakeup events from standby circuits. the pmc also immediately asserts system reset when slp_clk_en# is asserted regardless of the value of work_aux_deassert_delay (bits [19:0]). re set remains asserted throughout the standby state. there is not an assert delay. the wakeup event causes the work_aux output to assert. this event is called standby wakeup. on wakeup, reset continues to be applied to all non-standby circuits for the length of time specified in reset_delay (pms i/o offset 38h[19:0]). enabling this function and/or the function in pm_wkd (pms i/o offset 30h[30] = 1) causes the same standby state events. standby state is not entered unless slp_clk_en# is asserted. 29:20 rsvd reserved. by convention write 0, but may write anything. reads return 0. 19:0 work_aux_ deassert_ delay work_aux de-assert delay. indicates the number of 32 khz clock edges to wait from the assertion of slp_clk_en# before de-asserting the work_aux output. bit 30 (work_aux_deassert_en) must be high to enable this delay. amd geode? cs5535 companion device data book 513 power management controller register descriptions 31506b 6.18.3.12 pm de-assert reset delay from standby (pm_rd) reads always return the value writte n, except for rsvd bits [29:20]. 6.18.3.13 pm working auxiliary assert de lay from standby wakeup (pm_wkxa) reads always return the value writte n, except for rsvd bits [29:20]. pms i/o offset 38h ty p e r / w reset value 40000100h pm_rd register map 313029282726252423222120191817161514131211109876543210 reset_lock reset_en rsvd reset_delay pm_rd bit descriptions bit name description 31 reset_lock reset lock. after this bit is set, the value of pm_rd can not be changed until reset_stand# is applied. 30 reset_en reset delay enable. must be high for the reset_out # output de-assert delay spec- ified in bits [19:0] (reset_delay ) to be applied. (default = 1.) 29:20 rsvd reserved. by convention write 0, but may write anything. reads return 0. 19:0 reset_delay reset de-assert delay. indicates the number of 32 khz clock edges to continue asserting reset_out# from standby wakeup. default value is 8 ms. this delay starts only if the reset_work# input is de-asserted and the internal low voltage detect circuit detects normal operating voltages on v core . (default = 00100h.) (see section 4.6 "reset considerations" on page 65 for further details regarding reset conditions.) bit 30 (reset_en) must be high to enable this delay. reset will be applied to the system for the longer of this value or until the internal low voltage detect circuit detects normal operating voltages on v core pms i/o offset 3ch ty p e r / w reset value 00000000h pm_wkxa register map 313029282726252423222120191817161514131211109876543210 work_aux_lock work_aux_en rsvd work_aux_delay 514 amd geode? cs5535 companion device data book power management controller register descriptions 31506b 6.18.3.14 pm fail-safe de lay and enable (pm_fsd) reads always return the value writte n, except for rsvd bits [29:20]. pm_wkxa bit descriptions bit name description 31 work_aux_ lock working auxiliary lock. after this bit is set, the value in this register can not be changed until reset_stand# is applied. 30 work_aux_en working auxiliary delay enable. must be high to enable the delay specified in bits [19:0] (work_aux_delay). if this bit is low, the work_aux output is uncondition- ally asserted at standby wakeup. if work_aux was not de-asserted going into standby, then this control is a ?don?t care?. 29:20 rsvd reserved. by convention write 0, but may write anything. reads return 0. 19:0 work_aux_ delay working auxiliary assert delay. indicates the number of 32 khz clock edges to wait from standby wakeup before asserting the work_aux output. bit 30 (work_aux_en) must be high to enable this delay. may be programmed to assert before or after reset_out# de-asserts. the standby wakeup event is not recognized until normal (nwkd) or abnormal (awkd) to work delay expires, if those delays are enabled. (see pms i/o offset 4ch and 50h for details regarding the nwkd and awkd registers.) pms i/o offset 40h ty p e r / w reset value 00000000h pm_fsd register map 313029282726252423222120191817161514131211109876543210 pwrbut_lock pwrbut_en rsvd pwrbut_delay pm_fsd bit descriptions bit name description 31 pwrbut_lock power button lock. after this bit is set, the value in this register can not be changed until reset_stand # is applied. 30 pwrbut_en power button enable. must be high to enable the fail-safe function. 29:20 rsvd reserved. by convention write 0, but may write anything. reads return 0. 19:0 pwrbut_delay power button delay. if the power button (pwr_but#) input signal is asserted for pwrbut_delay number of 32 khz clock edges, then unconditionally de-assert working and work_aux to remove working power. if pwr_but# is still asserted at wakeup, hold in standby state until de-asserted. pwr_but# needs to be asserted for at least one 32 khz clock edge for this function to work properly. a less than one 32 khz clock edge pulse on pwr_but# may not be registered. the delay restarts if pwr_but# de-asserts and then asserts again. if pwr_but# is already asserted, the delay restarts anytim e pwrbut_delay (this field) is written. amd geode? cs5535 companion device data book 515 power management controller register descriptions 31506b 6.18.3.15 pm thermal-safe delay and enable (pm_tsd) reads always return the value writte n, except for rsvd bits [29:20]. 6.18.3.16 pm power-safe delay and enable (pm_psd) reads always return the value writte n, except for rsvd bits [29:20]. pms i/o offset 44h ty p e r / w reset value 00000000h pm_tsd register map 313029282726252423222120191817161514131211109876543210 thrm_lock thrm_en rsvd thrm_delay pm_tsd bit descriptions bit name description 31 thrm_lock thermal lock. after this bit is set, the value in this register can not be changed until reset_stand# is applied. 30 thrm_en thermal enable. must be high to enable the thermal alarm function. 29:20 rsvd reserved. by convention write 0, but may write anything. reads return 0 value. 19:0 thrm_delay thermal delay. if the thermal alarm (thrm_alrm#) input signal is asserted for thrm_delay number of 32 khz clock edges, then unconditionally de-assert work- ing and work_aux to remove working power. if thrm_alrm# is still asserted at wakeup, hold in standby state until thrm_alrm# is de-asserted. thrm_alrm# needs to be asserted for at least one 32 khz clock edge for this func- tion to work properly. a less than one 32 khz clock edge pulse on thrm_alrm# may not be registered. the delay restarts if thrm_alrm# de-asserts and then asserts again. if thrm_alrm# is asserted, the delay restarts anytime thrm_delay (this bit) is writ- ten. since the thermal alarm resides in the wo rking domain, the thrm_alrm# input sig- nal is blocked (de-asserted) when in standby state. the result is the standby state could not be held if the thermal alarm is still asserted at wakeup. once out of standby, the thermal alarm again comes into play. if it is still asserted, its timer would start again. pms i/o offset 48h ty p e r / w reset value 00000000h pm_psd register map 313029282726252423222120191817161514131211109876543210 lowbat_lock lowbat_en rsvd lowbat_delay 516 amd geode? cs5535 companion device data book power management controller register descriptions 31506b 6.18.3.17 pm normal work delay and enable (pm_nwkd) reads always return the value written, except for rsvd bits [29:20]. this register applies to normal standby state entry. pm_psd bit descriptions bit name description 31 lowbat_lock low battery lock. after this bit is set, the value in this register can not be changed until reset_stand # is applied. 30 lowbat_en low battery enable. must be high to enable this function. 29:20 rsvd reserved. by convention write 0, but may write anything. reads return 0. 19:0 lowbat_delay low battery delay. if the low battery input low_bat# (gpio25) is asserted for lowbat_delay number of 32 khz clock edges, then unconditionally de-assert working and work_aux to remove working power. if low_bat# is still asserted at wakeup, hold in standby state until low_bat# is de-asserted. low_bat# needs to be asserted for at least one 32 khz clock edge for this function to work properly. a less than one 32 khz clock edge pulse on the low_bat# input may not be registered. the delay restarts if low_bat# de-asserts and then asserts again. if low_bat# is already asserted, the delay restarts anytim e lowbat_delay (this field) is written. pms i/o offset 4ch ty p e r / w reset value 00000000h pm_nwkd register map 313029282726252423222120191817161514131211109876543210 nwkd_lock nwkd_en rsvd nwkd_delay pm_nwkd bit descriptions bit name description 31 nwkd_lock normal work delay lock. after this bit is set, the valu e in this register can not be changed until reset_stand# is applied. 30 nwkd_en normal work delay enable. must be high to enable this function. 29:20 rsvd reserved. by convention write 0, but may write anything. reads return 0. 19:0 nwkd_delay normal work delay delay. if the standby state is entered normally, nwkd_delay number of 32 khz clock edges must pass before the working state is allowed to be entered again, that is, a standby wakeup recognized. amd geode? cs5535 companion device data book 517 power management controller register descriptions 31506b 6.18.3.18 pm abnormal work delay and enable (pm_awkd) reads always return the value written, except for rsvd bits [29:20]. this register applies to abnormal standby state entry. 6.18.3.19 pm standby stat us and control (pm_ssc) pms i/o offset 50h ty p e r / w reset value 00000000h pm_awkd register map 313029282726252423222120191817161514131211109876543210 awkd_lock awkd_en rsvd awkd_delay pm_awkd bit descriptions bit name description 31 awkd_lock abnormal work delay lock. after this bit is set, the value in this register can not be changed until reset_stand# is applied. 30 awkd_en abnormal work delay enable. must be high to enable this function. 29:20 rsvd reserved. by convention write 0, but may write anything. reads return 0. 19:0 awkd_delay abnormal work delay delay. if the standby state is entered abnormally, awkd _ delay number of 32 khz clock edges must pass before the working state is allowed to be entered again, that is, a standby wakeup recognized. pms i/o offset 54h ty p e r / w reset value 00000001h pm_ssc register map 313029282726252423222120191817161514131211109876543210 rsvd pi clear_pi set_pi rsvd bad_pack_rst_flag glcp_sft_rst_flag watchdog_rst_flag shtdwn_rst_flag sft_rst_flag rsvd hrd_rst_flag lowbat_flag thrm_flag pwrbtn_flag lv d _ f l ag norm_flag off_flag 518 amd geode? cs5535 companion device data book power management controller register descriptions 31506b pm_ssc bit descriptions bit name description 31:19 rsvd reserved. reads return 0; writes are don?t care. 18 pi (ro) power immediate (read only). reads return current value of power immediate bit. 17 clear_pi clear power immediate. write 1 to clear the read only power immediate bit (bit 18). writing 0 has no effect. reads return 0. 16 set_pi set power immediate. write 1 to set the read only power immediate bit (bit 18). writ- ing 0 has no effect. reads return 0. 15:13 rsvd reserved. reads return 0; writes are don?t care. 12 badpack_ rst_flag bad packet reset flag. if set, indicates that the last standby state was entered from bad packet type reset. returns to working state when abnormal work delay expires. (note 1) note 1. standby status. these bits are cleared each time the power ma nagement logic enters the standby state except for the bit that caused the entry . write 1 to the bit to clear the bit; writing 0 has no effect. bits [ 12:8,6] do not result in working or work_aux being de-asserted. 11 glcp_sft_ rst_flag glcp soft reset flag. if set, indicates that the last standby state was entered from a glcp soft reset. returns to working state when abnormal work delay expires. (note 1) 10 watchdog_ rst_flag watchdog reset flag . if set, indicates that the last standby state was entered from a watchdog reset. returns to working state when abnormal work delay expires. (note 1) 9 shtdwn_rst_ flag shutdown reset flag . if set, indicates that the last standby state was entered from shutdown reset. returns to working state when abnormal work delay expires. (note 1) 8sft_rst_ flag soft reset flag. if set, indicates that the last standby state was entered from a soft- ware reset. returns to working state when abnormal work delay expires. (note 1) 7 rsvd reserved. reads return 0; writes are don?t care. 6 hrd_rst_flag hard reset flag . if set, indicates that the last standby state was entered due to the unexpected assertion of working reset. returns to working state when hard reset is de-asserted and abnormal work delay expires. (note 1) 5 lowbat_flag low battery flag. if set, indicates that the last standby state was entered due to a low power shutdown. returns to working state due to default wakeup. (note 1) 4thrm_flag thermal flag. if set, indicates that the last standby state was entered due to a thermal shutdown. returns to working state due to default wakeup. (note 1) 3pwrbtn_flag power button flag. if set, indicates that the last standby state was entered via a fail- safe power off sequence. user held down the power button. pm1_cnt was not used. returns to working state due to default wakeup. (note 1) 2 lvd_flag working power fail. if set, indicates that the last standby state was entered via an unexpected loss of working power as detected with the on-chip low voltage detect cir- cuit. returns to working state due to default wakeup. (note 1) 1norm_flag normal flag. if set, indicates that the last stand by state was entered under program control through use of pm1_cnt. returns to working state due to programmed wakeup. see pm1_sts (acpi i/o offset 00h) and pm_gpe0_sts (acpi i/o offset 18h) for wakeup source. (note 1) 0 off_flag off flag (no previous). if set, indicates that the circ uits of the standby power domain have been reset. entry was from the power off state. returns to working state due to default wakeup. (note 1) amd geode? cs5535 companion device data book 519 flash controller register descriptions 31506b 6.19 flash controller register descriptions the registers for the flash controller are divided into three sets: standard geodelink device (gld) msrs (shared with divil, see secti on 6.6.1 on page 317.) flash controller specific msrs flash controller native registers the msrs are accessed via the rdmsr and wrmsr pro- cessor instructions. the msr address is derived from the perspective of the cpu core. see section 4.2 "msr addressing" on page 59 for more details. all msrs are 64 bits, however, the flash controller spe- cific msrs (summarized in table 6-69) are called out as 32 bits. the flash controller treats writes to the upper 32 bits (i.e., bits [63:32]) of the 64-bit msrs as don?t cares and always returns 0 on these bits. the native registers associated with the flash controller are nand configuration registers, summarized in table 6- 70. the nand native regist ers are 4-kbyte memory mapped or 16-byte i/o mapped. the base address is defined by lbar in diverse device and can be located at any 4-kbyte boundaries if it is memory mapped, any 16- byte boundary if it is i/o mapped. the nand flash con- troller is a 32-bit wide device present in diverse device without burst capability. to access the msr registers in the nand flash controller, a 32-bit wide bus is used as the lbus interface. for nand command/address, data write and read modes, the nand flash controller provides the valid data on the least significant nibbles of the lbus data ports. there are no nor control regi sters located in i/o or mem- ory space. all nor timing control functions are located in the flash specific msrs. additionally, the diverse device lbar msrs associates up to four chip selects for four flash devices (see section 6.6.2.9 "local bar - flash chip select (divil_lbar_flsh[x])" on page 332 bit details). msr_lbar_flsh0 (msr 51400010h) for use with flash_cs0#. msr_lbar_flsh1 (msr 51400011h) for use with flash_cs1#. msr_lbar_flsh2 (msr 51400012h) for use with flash_cs2#. msr_lbar_flsh3 (msr 51400013h) for use with flash_cs3#. after the msr setup is complete, a nor flash device can be associated with a block of system memory using up to 28 address bits (a[27:0]). the reference column in the summary tables point to the page where the register maps and bit descriptions are listed. table 6-69. flash controller specific msrs summary msr address type register name reset value reference 51400018h r/w nor flash control (norf_ctl) 00000000h page 520 51400019h r/w nor flash timing for chip se lects 0 and 1 (nortf_t01) 07770777h page 522 5140001ah r/w nor flash timing for chip se lects 2 and 3 (nortf_t23) 07770777h page 523 5140001bh r/w nand flash data timing msr (nandf_data) 07770777h page 523 5140001ch r/w nand flash control timing (nandf_ctl) 00000777h page 523 5140001dh r/w flash reserved (nandf_rsvd) 00000000h page 523 520 amd geode? cs5535 companion device data book flash controller register descriptions 31506b 6.19.1 flash controller specific msrs 6.19.1.1 nor flash control (norf_ctl) table 6-70. flash controller native registers summary flash memory offset flash i/o offset type width (bits) register name reset value reference 000h-7ffh 00h-03h r/w 8 nand device data (nand_data) undefined page 526 any even address between 800h-80eh 04h r/w 8 nand control register (nand_ctl) 01h page 526 any odd address between 801h-80fh 05h r/w 8 nand i/o (nand_io) 00h page 527 810h 06h r/w 8 nand status (nand_sts) 0xh page 527 815h 08h r/w 8 nand ecc control (nand_ecc_ctl) 04h page 528 811h 09h r/w 8 nand ecc lsb line parity (nand_ecc_lsb) ffh page 529 812h 0ah r/w 8 nand ecc msb line parity (nand_ecc_msb) ffh page 529 813h 0bh r/w 8 nand ecc column parity (nand_ecc_col) ffh page 529 814h 0ch r/w 8 nand line address counter (nand_lac) 00h page 530 816h-fffh 07h, 0dh-0fh --- --- reserved. reads return 0. writes have no effect. --- --- msr address 51400018h ty p e r / w reset value 00000000h norf_ctl register map 313029282726252423222120191817161514131211109876543210 rsvd chk_iochrdy3 chk_iochrdy2 chk_iochrdy1 chk_iochrdy0 we_cs3 we_cs2 we_cs1 we_cs0 amd geode? cs5535 companion device data book 521 flash controller register descriptions 31506b norf_ctl bit descriptions bit name description 31:8 rsvd reserved 7 chk_iochrdy3 (note 1) note 1. if any chk_iochrdy[x] bit (bits [7:4 ]) is high, and the corresponding chip select (flash_cs[x]#) is low, then signal flash_iochrdy is checked to determine when to de-assert the re# or we # strobe. the re# or we# strobe pulse width will be the programmed valu e (msr_nortf_t01[22:20], msr_nortf_t01[6:4], msr_nortf_t23[22:20] and msr_nortf_t23[6:4] ) increased by at least two lo cal bus clock (33 mhz) cycles. if no chk_iochrdy[x] bit (bits [7:4]) is high, or if no chk_iordy[x] bit is high that has a corresponding active (low) chip select (flash_cs[x]#) , then signal flash_iochrdy is i gnored and the nor controller?s we# and re# strobe pulse widths will be the values programmed in the nor msr registers (msr_nortf_t01[22:20], msr_nortf_t01[6:4], msr_nortf_t 23[22:20] and msr_nortf_t23[6:4] ). in this case, if the pulse width of we# and re# in the nor msr registers is programmed as 0, then the nor controller ?s we# and re# generation will use 16 as the count value of nor pulse width. check i/o channel ready 3. check flash_iochrdy signal for nor chip select #3 (flash_cs3#) 0: ignore iochrdy signal. no wait states will be inserted. 1: check iochrdy before finishing the chip select strobe pulse. 6 chk_iochrdy2 (note 1) check i/o channel ready 2. check flash_iochrdy signal for nor chip select #2 (flash_cs2#) 0: ignore iochrdy signal. no wait states will be inserted. 1: check iochrdy before finishing the chip select strobe pulse. 5 chk_iochrdy1 (note 1) check i/o channel ready 1. check flash_iochrdy signal for nor chip select #1 (flash_cs1#) 0: ignore iochrdy signal. no wait states will be inserted. 1: check iochrdy before finishing the chip select strobe pulse. 4 chk_iochrdy0 (note 1) check i/o channel ready 0. check flash_iochrdy signal for nor chip select #0 (flash_cs0#) 0: ignore iochrdy signal. no wait states will be inserted. 1: check iochrdy before finishing the chip select strobe pulse. 3we_cs3 write enable for cs3#. write enable for nor chip select #3 (flash_cs3#) 0: no write cycles go out to nor flash interface via cs3#. 1: allow write cycles to go out to nor flash interface. 2we_cs2 write enable for cs2#. write enable for nor chip select #2 (flash_cs2#) 0: no write cycles go out to nor flash interface via cs2#. 1: allow write cycles to go out to nor flash interface. 1we_cs1 write enable for cs1#. write enable for nor chip select #1 (flash_cs1#) 0: no write cycles go out to nor flash interface via cs1#. 1: allow write cycles to go out to nor flash interface. 0we_cs0 write enable for cs0#. write enable for nor chip select #0 (flash_cs0#) 0: no write cycles go out to nor flash interface via cs0#. 1: allow write cycles to go out to nor flash interface. 522 amd geode? cs5535 companion device data book flash controller register descriptions 31506b 6.19.1.2 nor flash timing msrs the nor flash controller is used for nor fl ash or gpcs. the timing is different from device to device, so separate timing registers are used for each device. nor flash timing for chip selects 0 and 1 (nortf_t01) msr address 51400019h ty p e r / w reset value 07770777h nortf_t01 register map 313029282726252423222120191817161514131211109876543210 rsvd th1 rsvd tp1 rsvd ts1 rsvd th0 rsvd tp0 rsvd ts0 nortf_t01 bit descriptions bit name description 31:27 rsvd reserved. reads return value written. 26:24 th1 (note 1) note 1. the valid range for the count values of setup time, a nd hold time in nor msr registers is 1 through 7 (local bus clock cycles or lpc clock cycles) when a general purpose devi ce is used (with nor c ontroller). if signal flash_iochrdy is not used by the g eneral purpose device, then the valid range for the count value of pulse width in nor msr registers is 1 thr ough 7 (local bus clock cycles or lpc clock cycles). if flash_iochrdy is used by the general purpose device, then the valid range for the count value of pulse width in nor msr registers is 2 through 7 (local bus clock cycles or lpc clock cycles). in the case of nor devices, as nor controller doesn?t support the use of flash_iochrdy (explained in section 5.18.2 "nor flash controller/general purpose chip select" on page 186),the valid range fo r the count values of setup time, pulse width, and hold time in nor msr registers is 1 through 7 (local bus clock cycles or lpc cl ock cycles).in the case of no r controller?s we# and re# strobe pulse widths, if nor control msr register bits[7:4] (chkrd y[3:0]) are enabled (active high) in the case of general purpose devices then the gener ated pulse widths will be longer than programmed count value. if setup or hold time in nor msr registers is programmed as 0, then the nor controller?s we# and re# generation will use 16 as the count value of nor setup or hold time. hold time for nor chip select 1. hold from we# or re# rising edge to chip select. refer to figure 5-58 "nor flash wit h wait states timing" on page 188. 23 rsvd reserved. reads return value written 22:20 tp1 strobe pulse width for nor chip select 1. re# and we# strobe pulse width. at the end of the tp, sample the iochrdy pin to see if a wait state is needed. refer to figure 5-58 "nor flash with wait states timing" on page 188. 19 rsvd reserved. reads return value written. 18:16 ts1 (note 1) setup time for nor chip select 1. chip select to we# or re# falling edge setup time. refer to figure 5-58 "nor flash wit h wait states timing" on page 188. 15:11 rsvd reserved. reads return value written. 10:8 th0 (note 1) hold time for nor chip select 0. hold from we# or re# rising edge to chip select. refer to figure 5-58 "nor flash with wait states timing" on page 188. 7 rsvd reserved. reads return value written. 6:4 tp0 strobe pulse width for nor chip select 0. re# and we# strobe pulse width. at the end of the tp, sample the iochrdy pin to see if a wait state is needed. refer to figure 5-58 "nor flash with wait states timing" on page 188. 3 rsvd reserved. reads return value written. 2:0 ts0 (note 1) setup time for nor chip select 0. chip select to we# or re# falling edge setup time. refer to figure 5-58 "nor flash wit h wait states timing" on page 188. amd geode? cs5535 companion device data book 523 flash controller register descriptions 31506b nor flash timing for chip selects 2 and 3 (nortf_t23) msr address 5140001ah ty p e r / w reset value 07770777h nortf_t23 register map 313029282726252423222120191817161514131211109876543210 rsvd th3 rsvd tp3 rsvd ts3 rsvd th2 rsvd tp2 rsvd ts2 nortf_t23 bit descriptions bit name description 31:27 rsvd reserved. reads return value written. 26:24 th3 (note 1) note 1. the valid range for the count values of setup time , and hold time in nor msr registers is 1 through 7 when a general purpose device is used (with nor controller). if signal flash_iochrdy is not used by the general pur- pose device, then the valid range for the count value of pulse width in nor msr registers is 1 through 7. if flash_iochrdy is used by the general purpose device, t hen the valid range for the count value of pulse width in nor msr registers is 2 through 7. in the case of nor devices, as nor controller doesn?t support the use of flash_iochrdy (explained in section 5.18.2 "nor flas h controller/general purpose chip select" on page 186),the valid range for the count values of setup time, pulse width, and hold time in nor msr registers is 1 through 7.in the case of nor controller?s we# and re# st robe pulse widths, if nor control msr register bits[7:4] (chkrdy[3:0]) are enabled (active high) in the case of general purpose devices then the generated pulse widths will be longer than programmed count value. if setup or hol d time in nor msr registers is programmed as 0, then the nor controller?s we# and re# generation will use 16 as the count value of nor setup or hold time. hold time for nor chip select 3. hold from we# or re# rising edge to chip select. refer to figure 5-58 "nor flash wit h wait states timing" on page 188. 23 rsvd reserved. reads return value written. 22:20 tp3 strobe pulse width for nor chip select 3. re# and we# strobe pulse width. at the end of the tp, sample the flash_ iochrdy si gnal to see if a wait state is needed. refer to figure 5-58 "nor flash wit h wait states timing" on page 188. 19 rsvd reserved. reads return value written. 18:16 ts3 (note 1) setup time for nor chip select 3. chip select to we# or re# falling edge setup time. refer to figure 5-58 "nor flas h with wait states timing" on page 188. 15:11 rsvd reserved. reads return value written . 10:8 th2 (note 1) hold time for nor chip select 2. hold from we# or re# rising edge to chip select. refer to figure 5-58. 7 rsvd reserved. reads return value written. 6:4 tp2 strobe pulse width for nor chip select 2. re# and we# strobe pulse width. at the end of the tp, sample the flash_iochrdy signal to see if a wait state is needed. refer to figure 5-58 "nor flash wit h wait states timing" on page 188. 3 rsvd reserved. reads return value written. 2:0 ts2 (note 1) setup time for nor chip select 2. chip select to we# or re# falling edge setup time. refer to figure 5-58 "nor flas h with wait states timing" on page 188. 524 amd geode? cs5535 companion device data book flash controller register descriptions 31506b 6.19.1.3 nand flash data timing msr (nandf_data) most nand devices have similar timing. all nand devices shar e the timing registers. the valid range for the count values of setup time and hold time in nand msrs is 0 through 7 local bus clock (?lb_c?) cycles or lpc clock (?lpc_c?) cycles and the valid range for the count values of pulse width in nand msrs is 1 through 7 local bus clock (?lb_c?) cycles or lpc clock (?lpc_c?) cycles. msr address 5140001bh ty p e r / w reset value 07770777h nandf_data register map 313029282726252423222120191817161514131211109876543210 rsvd trh rsvd trp rsvd trs rsvd twh rsvd twp rsvd tws nandf_data bit descriptions bit name description 31:27 rsvd reserved. reads return value written. 26:24 trh data read hold time. this timing is just for internal state machine; no external refer- ence point. can be set to 0 if the hold time is not needed. range = 0h to 7h. refer to figure 5-61 "nand data timing with wait states" on page 190. 23 rsvd reserved. reads return value written. 22:20 trp data read pulse width. the re# active pulse width in data read phase. range = 1h to 7h. refer to figure 5-61 "nand data timing with wait states" on page 190. 19 rsvd reserved. reads return value written. 18:16 trs data read setup time. this timing is just for internal state machine; no external refer- ence point. can be set to 0 if the setup time is not needed. range = 0h to 7h. refer to figure 5-61 "nand data timing with wait states" on page 190. 15:11 rsvd reserved. reads return value written. 10:8 twh data write hold time. the hold time from we# rising edge to i/o bus is turned off. range = 0h to 7h. refer to figure 5-61 "nand data timing with wait states" on page 190. 7 rsvd reserved. reads return value written. 6:4 twp data write pulse width. the we# active pulse width in data write phase. note that the data byte is put on the i/o bus at the same time the we# is asserted. range = 1h to 7h. refer to figure 5-61 "nand data timing with wait states" on page 190. 3 rsvd reserved. reads return value written. 2:0 tws data write setup time. this timing is just for internal state machine; no external refer- ence point. can be set to 0 if the setup time is not needed. range = 0h to 7h. refer to figure 5-61 "nand data timing with wait states" on page 190. amd geode? cs5535 companion device data book 525 flash controller register descriptions 31506b 6.19.1.4 nand flash contro l timing (nandf_ctl) 6.19.1.5 flash reserved (nandf_rsvd) this register is reserved. reads return 0. writes have no effect. msr address 5140001ch ty p e r / w reset value 00000777h nandf_ctl register map 313029282726252423222120191817161514131211109876543210 rsvd tch rsvd tcp rsvd tcs nandf_ctl bit descriptions bit name description 31:11 rsvd reserved. reads return value written. 10:8 tch control hold time. the hold time from the rising edge of we# to the toggle of control signals. note that the i/o bus is turned off when the tch expires. range = 0h to 7h. refer to figure 5-59 "nand flash command/address timing" on page 189. 7 rsvd reserved. reads return value written. 6:4 tcp control pulse width. the we# active pulse width in command/address phase. note that the command/address byte is put on the i/o bus at the same time that the we# is asserted. range = 1h to 7h. refer to figure 5-59 "nand flash command/address timing" on page 189. 3 rsvd reserved. reads return value written. 2:0 tcs control setup time. the setup time from the toggle of the control signals to the we# falling edge. range = 0h to 7h. refer to figure 5-59 "nand flash command/address timing" on page 189. msr address 5140001dh ty p e r / w reset value 00000000h 526 amd geode? cs5535 companion device data book flash controller register descriptions 31506b 6.19.2 flash controller native registers 6.19.2.1 nand device data (nand_data) reading or writing to this range accesses the same nand device data. 6.19.2.2 nand control re gister (nand_ctl) flash memory offset 000h-7ffh flash i/o offset 00h-03h ty p e r / w reset value undefined nand_data register map 76543210 data nand_data bit descriptions bit name description 7:0 data nand device data. no default value. this address space is not to be read from until data is read from the nand flash device. th e system will hang if a read is done from this address space without a prior read from nand flash device. flash memory offset any even address between 800h-80eh flash i/o offset 04h ty p e r / w reset value 01h nand_ctl register map 76543210 rsvd dist_en rdy_int_ mask ale cle ce# nand_ctl bit descriptions bit name description 7:5 rsvd (ro) reserved (read only). returns 0 when read. 4dist_en nand distract interrupt enable. 0: disables the generation of nand distract interrupt. 1: enables the generation of nand distract interrupt. 3 rdy_int_mask nand ready interrupt mask. 0: interrupt is masked. 1: enable nand flash device?s rdy/busy# signal to generate an interrupt. 2ale address latch enable. flash_ale output signal reflects the value of this bit. 1cle command latch enable. flash_cle output signal reflec ts the value of this bit. 0ce# chip enable. ce# signal reflects the value of this bit. the nand_cs signals from the diverse device determine which ce# is asserted. keep this bit low during entire nand cycle. writing a 1 to this bi t resets the nand controller. amd geode? cs5535 companion device data book 527 flash controller register descriptions 31506b 6.19.2.3 nand i/o (nand_io) 6.19.2.4 nand status (nand_sts) flash memory offset any odd address between 801h-80fh flash i/o offset 05h ty p e r / w reset value 00h nand_io register map 76543210 io nand_io bit descriptions bit name description 7:0 io i/o register. writing to this register triggers a command/address p hase sub-cycle on the nand flash interface. the data written to this register is put on the i/o bus during the sub-cycle. it returns previous written value when read. note: before writing to this register check for ctlr_busy bit (flash memory offset 810h[2]/flash i/o offset 06h[2]) in nand_sts register to be 0. flash memory offset 810h flash i/o offset 06h ty p e r / w reset value 0xh nand_sts register map 76543210 rsvd flash_rdy ctlr_busy cmd_comp dist_st nand_sts bit descriptions bit name description 7:4 rsvd (ro) reserved (read only). returns 0 when read. 3flash_rdy (ro) flash ready (read only). double synchronized output (with respect to local bus clock) of the nand flash device?s rdy/busy#. 2 ctlr_busy (ro) nand controller busy (read only). when high, indicates that the nand controller?s state machines are busy. 1cmd_comp nand command complete. when high, indicates that the most recent nand com- mand has completed. may be read anytime. wr ite 1 to clear this bit. writing 0 has no effect. 0dist_st nand distract status. occurrence of a nor interruption during a nand transaction sets this bit. write 1 to clear this bit. writing 0 has no effect. a nand transaction is started as soon as ce# goes low. it is stopped when ce# goes high. typically, a nand transaction needs multiple software commands (from 6 to ~500). since the flash interface is shared between nand and nor flash controllers and the nor flash controller gets priority to use the flash interface, a nand transac- tion may be interrupted by a nor transaction. dist_st bit is set to record this event. nand flash software must take necessary actions to recover the uncompleted trans- action. 528 amd geode? cs5535 companion device data book flash controller register descriptions 31506b 6.19.2.5 nand ecc control (nand_ecc_ctl) flash memory offset 815h flash i/o offset 08h ty p e r / w reset value 04h nand_ecc_ctl register map 76543210 rsvd parity clrecc enecc nand_ecc_ctl bit descriptions bit name description 7:3 rsvd reserved. reads return value written . 2parity parity. 0: ecc parity registers are even parity. 1: ecc parity registers are odd parity. in the case of odd ecc parity, the value read from nand_ecc_lsb (flash memory offset 811h/flash i/o offset 09h), na nd_ecc_msb (flash memory offset 812h/flash i/o offset 0ah), and nand_ecc_col (flash memory offset 813h/flash i/o offset 0bh) parity registers will be comple ment of the value writ ten into these regis- ters (except for lsb two bits of the nand_ecc_col register, they are always 11b for odd parity). 1clrecc clear ecc engine. write 1 to clear ecc parity registers (nand_ecc_lsb, nand_ecc_msb, and nand_ecc_col), nand line address counter register (nand_lac) and reset the ecc engine. writing 0 has no effect. the ecc engine contains an 8-bit line address counter (lac) to keep track of data that has been read from or written into the nand flash. software has to reset the counter by writing a 1 to the clrecc bit before transferring data to/from the nand flash. every data byte transferred to/from the nand flash controller increments the lac. the nand_lac (flash memory offset 814h/flash i/o offset 0ch) register reports the current count of the lac. 0 enecc enable ecc calculation engine. 0: disable ecc engine. ecc engine holds previous value. 1: enable ecc engine. every data byte transferred to/from the nand flash controller will be counted in ecc calculation. amd geode? cs5535 companion device data book 529 flash controller register descriptions 31506b 6.19.2.6 nand ecc pa rity registers ecc parity registers contain 22 parity bits. the bit location and definition follows the smartmedia physical format specifi- cations. nand ecc lsb line parity (nand_ecc_lsb) nand ecc msb line parity (nand_ecc_msb) nand ecc column parity (nand_ecc_col) flash memory offset 811h flash i/o offset 09h ty p e r / w reset value ffh nand_ecc_lsb register map 76543210 lp[7:0] nand_ecc_lsb bit descriptions bit name description 7:0 lp[7:0] line parity bits 7 through 0. flash memory offset 812h flash i/o offset 0ah ty p e r / w reset value ffh nand_ecc_msb register map 76543210 lp[15:8] nand_ecc_msb bit descriptions bit name description 7:0 lp[15:8] line parity bits 15 through 8. flash memory offset 813h flash i/o offset 0bh ty p e r / w reset value ffh nand_ecc_col register map 76543210 cp[5:0] rsvd nand_ecc_col bit descriptions bit name description 7:2 cp[5:0] column parity bi ts 5 through 0. 1:0 rsvd (ro) reserved. always returns 11 for odd ecc parity and 00 for even ecc parity. 530 amd geode? cs5535 companion device data book flash controller register descriptions 31506b 6.19.2.7 nand line addr ess counter (nand_lac) flash memory offset 814h flash i/o offset 0ch ty p e r / w reset value 00h nand_lac register map 76543210 lac nand_lac bit descriptions bit name description 7:0 lac line address counter value. the ecc engine contains an 8-bit line address counter (lac) to keep track of data that has been read from or written into the nand flash. software has to reset the counter by writing a 1 to the clrecc bit (flash mem- ory offset 815h[1]/flash i/o offset 08h[1] ) before transferring data to/from the nand flash. every data byte exchanged betwe en nand flash controller and geodelink adapter increments the lac. the nand_lac r egister reports the current count of the lac. amd geode? cs5535 companion device data book 531 geodelink? control processor register descriptions 31506b 6.20 geodelink? control pr ocessor register descriptions the geodelink control processor?s (glpc) register set consists of: standard geodelink device (gld) msrs glcp specific msrs the msrs (both standard and glpc specific) are accessed via the rdmsr and wrmsr processor instruc- tions. the msr address is derived from the perspective of the cpu core. see section 4.2 "msr addressing" on page 59 for more details. the tables that follow are register summary tables that include reset values and page references where the bit descriptions are provided. table 6-71. standard geodelink? device msrs summary msr address type register reset value reference 51700000h ro gld capabilities msr (glcp_gld_msr_cap) 00000000_002021xxh page 532 51700001h r/w gld master configuration msr (glcp_gld_msr_config) 00000000_00000000h page 532 51700002h r/w gld smi msr (glcp_gld_msr_smi) 00000000_00000003h page 532 51700003h r/w gld error msr (glcp_gld_msr_error) 00000000_00000000h page 534 51700004h r/w gld power management msr (glcp_gld_msr_pm) 00000000_00000000h page 535 51700005h r/w gld diagnostic msr (glcp_gld_msr_diag) 00000000_00000000h page 535 table 6-72. glpc specific msrs summary msr address type register reset value reference 51700008h r/w glcp clock disable delay value (glcp_clk_dis_delay) 00000000_00000000h page 537 51700009h r/w glcp clock mask for sleep request (glcp_pmclkdisable) 00000000_00000000h page 537 5170000ah ro glcp fabrication (glcp_fab) 00000000_00000002h page 538 5170000bh r/w glcp global power management control (glcp_glb_pm) 00000000_00000000h page 538 5170000ch r/w glcp debug output from chip (glcp_dbgout) 00000000_00000000h page 539 5170000dh r/w reserved registers (glpc_rsvd) 00000000_00000000h --- 5170000eh r/w software communication register (glcp_dowser) 00000000_00000000h page 539 5170000fh r/w glcp reserved register (glpc_rsvd) 00000000_00000000h --- 51700010h r/w glcp clock control (glcp_clkoff) 00000000_00000000h page 540 51700011h ro glcp clock active (glcp_clkactive) 0000000x_xxxxxxxxxh page 540 51700012h r/w glcp clock mask for debug clock stop action (glcp_clkdisable) 00000000_00000000h page 540 51700013h r/w glcp clock active mask for suspend acknowledge (glcp_clk4ack) 00000000_00000000h page 541 51700014h r/w glcp system reset control (glcp_sys_rst) 00000000_00000000h page 542 51700015h r/w reserved registers (glpc_rsvd) 00000000_00000000h --- 51700016h r/w glcp debug clock control (glcp_dbgclkctl) 00000000_00000002h page 542 51700017h ro chip revision id (glcp_chip_rev_id) 00000000_000000xxh page 543 51700018h- 517000ffh r/w reserved registers (glpc_rsvd) - reserved for internal testing. do not write to these registers. xxxxxxxx_xxxxxxxxh --- 532 amd geode? cs5535 companion device data book geodelink? control processor register descriptions 31506b 6.20.1 standard geodelink? device (gld) msrs 6.20.1.1 gld capabilities msr (glcp_gld_msr_cap) 6.20.1.2 gld master configurat ion msr (glcp_gld_msr_config) 6.20.1.3 gld smi msr (glcp_gld_msr_smi) the flags are set by internal conditions. the internal conditions are enabled if the en bit is 0. reading the flag bit returns the value; writing 1 clears the flag; writ ing 0 has no effect. (see section 4.8.3 "msr address 2: smi control" on page 74 for further smi/asmi generation details.) msr address 51700000h ty p e r o reset value 00000000_002021xxh glcp_gld_msr_cap register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd devid revid glcp_gld_msr_cap bit descriptions bit name description 63:24 rsvd reserved. reads as 0. 23:8 dev_id device id. identifies module (2021h). 7:0 rev_id revision id. identifies module revision. see amd geode? cs5535 companion device specification update document for value. msr address 51700001h ty p e r / w reset value 00000000_00000000h glcp_gld_msr_config register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd pid glcp_gld_msr_config bit descriptions bit name description 63:3 rsvd reserved. always write 0. 2:0 pid priority id. always write 0. msr address 51700002h ty p e r / w reset value 00000000_00000003h amd geode? cs5535 companion device data book 533 geodelink? control processor register descriptions 31506b glcp_gld_msr_smi register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd dbg_asmi_flag err_asmi_flag rsvd dbg_asmi_en err_asmi_en glcp_gld_msr_smi bit descriptions bit name description 63:18 rsvd reserved. reads as 0. 17 dbg_asmi_ flag debug asmi flag. if high, records that an asmi was generated and applied to the sys- tem, due to a debug event. write 1 to clear; writing 0 has no effect. dbg_asmi_en (bit 1) must be low to enable this flag. 16 err_asmi_flag error asmi flag. if high, records that an asmi was generated and applied to the sys- tem due to err signal. write 1 to clear; wr iting 0 has no effect. err_asmi_en (bit 0) must be low to enable this flag. 15:2 rsvd reserved. reads as 0. 1 dbg_asmi_en debug asmi enable. write 0 to enable dbg_asmi_flag (bit 17). write 1 to disable the flag and asmi generation. 0 err_asmi_en error asmi enable. write 0 to enable err_asmi_flag (bit 16). write 1 to disable the flag and asmi generation 534 amd geode? cs5535 companion device data book geodelink? control processor register descriptions 31506b 6.20.1.4 gld error msr (glcp_gld_msr_error) the flags are set by internal conditions. the internal conditions are enabled if the en bit is 0. reading the flag bit returns the value; writing 1 clears the flag; writing 0 has no effect. (see section 4.8.4 "msr address 3: error control" on page 78 for further err generation details.) msr address 51700003h ty p e r / w reset value 00000000_00000000h glcp_gld_msr_error register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd size_err_flag unexp_type_err_flag 313029282726252423222120191817161514131211109876543210 rsvd size_err_en unexp_type_err_en glcp_gld_msr_error bit descriptions bit name description 63:34 rsvd reserved. reads as 0. 33 size_err_flag size error flag. the gliu interface detected a read or write of more than 1 data packet (size = 16 or 32 bytes). if a response packet is expected, the excep bit of the response packet will be set; in all cases the asynchronous error signal will be set. write 1 to clear; writing 0 has no effect. 32 unexp_type_ err_flag unexpected type error flag. an unexpected type was sent to the glcp geodelink interface (start request with bex type, s noop, peek_write, debu g_req, or null type). if a response packet is expected, the excep bi t of the response packet will be set; in all cases the asynchronous error signal will be set. write 1 to clear; writing 0 has no effect. 31:2 rsvd reserved. reads as 0. 1 size_err_en size error enable. write 0 to enable the flag (bit 33) and allow the size error event to generate an asynchronous error to the system. 0 unexp_type_ err_en unexpected type error enable. write 0 to enable the flag (bit 32) and allow the unexpected type event to generate an asynchronous error to the system. amd geode? cs5535 companion device data book 535 geodelink? control processor register descriptions 31506b 6.20.1.5 gld power manageme nt msr (glcp_gld_msr_pm) 6.20.1.6 gld diagnostic msr (glcp_gld_msr_diag) this register is reserved for internal use by amd and should not be written to. msr address 51700004h ty p e r / w reset value 00000000_00000000h glcp_gld_msr_pm register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd pmode1 pmode0 glcp_gld_msr_pm bit descriptions bit name description 63:4 rsvd reserved. reads as 0. 3:2 pmode1 power mode 1. power mode for clock domain 1 (debug). 00: disable clock gating. clocks are always on. 01: enable active hardware clock gating. clock goes off whenever this module?s cir- cuits are not busy. 10: reserved. 11: reserved. 1:0 pmode0 power mode 0. power mode for clock domain 0 (gliu). 00: disable clock gating. clocks are always on. 01: enable active hardware clock gating. clock goes off whenever this module?s cir- cuits are not busy. 10: reserved. 11: reserved. msr address 51700005h ty p e r / w reset value 00000000_00000000h 536 amd geode? cs5535 companion device data book geodelink? control processor register descriptions 31506b 6.20.2 glcp specific msrs these registers are used for power man agement, and facilitate some clock and re set functions. the ?clk? associated reg- isters (i.e., clkactive, clkoff, clkdisable, clk4ack and pmclkdisable) have the same layout where each bit is associated with a clock domain. the layout and recommended operating values for the ?clk? associated registers is shown in table 6-73. for additional discussion on clock ma nagement considerations, see section 4.5 "clock consider- ations" on page 63. table 6-73. clock mapping / operational settings msr bit name/description glcp register clk active clk off clk disable clk 4ack pm clk disable clk[63:34] rsvd. reserved for future use by amd. ro0000 clk33 glcp_pci. glcp pci clock. ro0000 clk32 glcp_dbg. glcp dbg logic clock. ro 0000 clk31 glcp_gliu. glcp geodelink clock. ro 0000 clk30 divil_mfgpt_32k_std. mfgpt 32 khz standby clock entering divil. ro0000 clk29 divil_mfgpt_14m. mfgpt 14 mhz clock entering divil. ro0000 clk28 divil_mfgpt_32k. mfgpt 32 khz clock entering divil. ro0000 clk27 divil_gpio_std. gpio standby clock entering divil. ro 0000 clk26 divil_gpio. gpio clock entering divil. ro0000 clk25 divil_pmc_std. pmc standby clock. ro0000 clk24 divil_pmc. pmc working logic clock. ro 0000 clk23 divil_uart2. uart2 clock entering divil. ro0010 clk22 divil_uart1. uart1 clock entering divil. ro0010 clk21 divil_pit. pit clock entering divil. ro0000 clk20 divil_smb. smb clock entering divil. ro0010 clk19 divil_dma. dma clock entering divil. ro0010 clk18 divil_lpc. lpc clock entering divil. ro0010 clk17 divil_lb. lbus clock entering divil. ro0010 clk16 divil_gliu. geodelink (gliu) clock entering divil. ro 0010 clk15 acc_bit. ac97 clock entering acc. ro0000 clk14 acc_lb. 33 mhz clock entering acc. ro0010 clk13 acc_gliu. geodelink (gliu) clock entering acc. ro 0010 clk12 atac_lb. 66 mhz clock entering atac. ro0010 clk11 atac_gliu. geodelink (gliu) clock entering atac. ro 0010 clk10 usb2_48m. 48 mhz clock entering usb (ports 3 & 4). ro0010 clk9 usb1_48m. 48 mhz clock entering usb (ports 1 & 2). ro0010 clk8 usb2_lb. 33 mhz clock entering usb (ports 3 & 4). ro0010 clk7 usb1_lb. 33 mhz clock entering usb (ports 1 & 2). ro0010 clk6 usb2_gliu. geodelink (gliu) clock entering usb (ports 3 & 4). ro 0010 clk5 usb1_gliu. geodelink (gliu) clock entering usb (ports 1 & 2). ro 0010 clk4 glpci_pcif. fast pci clock for chip i/o interface. ro0000 clk3 glpci_pci. normal pci clock for glpci_sb logic. ro0010 clk2 glpci_gliu. geodelink (gliu) clock entering glpci_sb. ro 0010 clk1 gl0_1. geodelink (gliu) operat ional logic clock. ro 0010 clk0 gl0_0. geodelink (gliu) cloc k to timer logic. ro 0000 amd geode? cs5535 companion device data book 537 geodelink? control processor register descriptions 31506b 6.20.2.1 glcp clock disable dela y value (glcp_clk_dis_delay) this register has bits that, when set, disable clocks. 6.20.2.2 glcp clock mask for sl eep request (glcp_pmclkdisable) msr address 51700008h ty p e r / w reset value 00000000_00000000h glcp_clk_dis_delay register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd clk_delay glcp_clk_dis_delay bit descriptions bit name description 63:24 rsvd reserved. reads as 0 23:0 clk_delay clock disable delay. if enabled in glcp_glb_pm (msr 5170000bh[1] = 1), this field indicates the period to wait from the assertion of suspa# before gating-off clocks speci- fied in glcp_pmclkdisable (msr 51700009h). if th is delay is enabled, it overrides or disables the function of glcp_clk4ack (msr 51700013h). if glcp_glb_pm enable bit is not set (msr 5170000bh[1] = 0), but this register (glcp_clk_dis_delay) is non- zero, then this register behaves as a timeout for the clk4ack behavior. note that this number is in terms of pci clock cycles, divided by 16. msr address 51700009h ty p e r / w reset value 00000000_00000000h glcp_pmclkdisable register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd clk33 clk32 313029282726252423222120191817161514131211109876543210 clk31 clk30 clk29 clk28 clk27 clk26 clk25 clk24 clk23 clk22 clk21 clk20 clk19 clk18 clk17 clk16 clk15 clk14 clk13 clk12 clk11 clk10 clk9 clk8 clk7 clk6 clk5 clk4 clk3 clk2 clk1 clk0 glcp_pmclkdisable bit descriptions bit name description 63:34 rsvd reserved 33:0 clk_dis clock disable. the bits in this field correspond to the clock off (clk_off) bits in glcp_clkoff (msr 51700010h). if a bit in this field is set, then the corresponding clk_off bit will be set when the power management circuitry disables clocks when entering sleep. for bit-to-clock correspondences and recommended operational settings see table 6-73 on page 536. 538 amd geode? cs5535 companion device data book geodelink? control processor register descriptions 31506b 6.20.2.3 glcp fabrication (glcp_fab) this is a read only register used to track various fab processes and product family parameters. it is meant for amd internal use only. 6.20.2.4 glcp global power mana gement control (glcp_glb_pm) msr address 5170000ah ty p e r o reset value 00000000_00000002h glcp_fab register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd glcp_fab bit descriptions bit name description 63:0 rsvd reserved. reads return reset value. msr address 5170000bh ty p e r / w reset value 00000000_00000000h glcp_glb_pm register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd clk_dly_en rsvd glcp_glb_pm bit descriptions bit name description 63:2 rsvd reserved 1 clk_dly_en clock delay enable. write 1 to enable gating-off cloc k enables from a delay rather than from glcp_clk4ack (msr 51700013h). 0 rsvd reserved. must be written 0. amd geode? cs5535 companion device data book 539 geodelink? control processor register descriptions 31506b 6.20.2.5 glcp debug output from chip (glcp_dbgout) 6.20.2.6 software communicatio n register (glcp_dowser) this register is a free 64-bit read/w rite register that can be used by software, for example, to store flags. msr address 5170000ch ty p e r / w reset value 00000000_00000000h glcp_dbgout re gister map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd glcp_dbgout bit descriptions bit name description 63:0 rsvd reserved. these bits are reserved for internal testing only. these bits should not be written to. msr address 5170000eh ty p e r / w reset value 00000000_00000000h glcp_dowser register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 val 313029282726252423222120191817161514131211109876543210 val glcp_dowser bit descriptions bit name description 63:0 val value. this 64-bit scratchpad register was sp ecifically added for sw debugger use (dowser). the register resets to 00000000_00000000h with both hard and soft resets. 540 amd geode? cs5535 companion device data book geodelink? control processor register descriptions 31506b 6.20.2.7 glcp clock control (glcp_clkoff) this register has bits that, when set, disable clocks immediately. it is not intended for normal use, only as a debug tool. 6.20.2.8 glcp clock active (glcp_clkactive) msr address 51700010h ty p e r / w reset value 00000000_00000000h glcp_clkoff register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd clk33 clk32 313029282726252423222120191817161514131211109876543210 clk31 clk30 clk29 clk28 clk27 clk26 clk25 clk24 clk23 clk22 clk21 clk20 clk19 clk18 clk17 clk16 clk15 clk14 clk13 clk12 clk11 clk10 clk9 clk8 clk7 clk6 clk5 clk4 clk3 clk2 clk1 clk0 glcp_clkoff bit descriptions bit name description 63:34 rsvd reserved 33:0 clk_off clock off. a 1 in any bit position causes the corresponding clock to be immediately and unconditionally shut off. it is not in tended for normal operational use, only as a debug tool. for bit-to-clock correspondences and recommended operational settings see table 6-73 on page 536. msr address 51700011h ty p e r o reset value 0000000x_xxxxxxxxxh glcp_clkactive register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd clk33 clk32 313029282726252423222120191817161514131211109876543210 clk31 clk30 clk29 clk28 clk27 clk26 clk25 clk24 clk23 clk22 clk21 clk20 clk19 clk18 clk17 clk16 clk15 clk14 clk13 clk12 clk11 clk10 clk9 clk8 clk7 clk6 clk5 clk4 clk3 clk2 clk1 clk0 glcp_clkactive bit descriptions bit name description 63:34 rsvd (ro) reserved (read only). reads as 0. 33:0 clk_act (ro) clock active (read only). this register reports the status, active or inactive, of each clock. when set, each bit indicates that a block is internally enabling its own clock. the actual clock can be off even though the clk_act bit is set, if the corresponding clk_off bit is set in glcp_clkoff (msr 51700010h). for bit-to-clock correspon- dences and recommended operational settings see table 6-73 on page 536. amd geode? cs5535 companion device data book 541 geodelink? control processor register descriptions 31506b 6.20.2.9 glcp clock mask for debug cl ock stop action (glcp_clkdisable) 6.20.2.10 glcp clock active mask for suspend acknowledge (glcp_clk4ack) this register has bits that correspond to the clock acti ve (clk_act) bits in glcp_clkactive (msr 51700011h). if the bit in glcp_clk4ack is set, then the suspa# signal w ill not go low unless all the marked clocks are inactive. msr address 51700012h ty p e r / w reset value 00000000_00000000h glcp_clkdisable register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd glcp_clkdisable bit descriptions bit name description 63:0 rsvd reserved. this register is reserved for internal testing only. these bits should not be written to. msr address 51700013h ty p e r / w reset value 00000000_00000000h glcp_clk4ack register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd clk33 clk32 313029282726252423222120191817161514131211109876543210 clk31 clk30 clk29 clk28 clk27 clk26 clk25 clk24 clk23 clk22 clk21 clk20 clk19 clk18 clk17 clk16 clk15 clk14 clk13 clk12 clk11 clk10 clk9 clk8 clk7 clk6 clk5 clk4 clk3 clk2 clk1 clk0 glcp_clk4ack bit descriptions bit name description 63:34 rsvd reserved 33:0 clkact_en_slp clock active enable for sleep. a 1 in any bit position indicates the corresponding clock is to be monitored during a power management sleep operation. when all the clocks with associated 1s become inactive, the glcp sends a suspend acknowledge (suspa#) to the power management logic to begin the transition to the sleep state. use of this register during sleep sequences requires the clk_dly_en bit (msr 5170000bh[1]) to be 0. for bit-to-clock correspondences and recommended operational settings see table 6-73 on page 536. 542 amd geode? cs5535 companion device data book geodelink? control processor register descriptions 31506b 6.20.2.11 glcp system reset control (glcp_sys_rst) writing 1 to the chip_reset bit creates a chip-wide reset and in turn, resets this register. writing this register with the chip_reset bit set will never send a write -response over the gliu in terface (this allows halting bus traffic before the reset occurs). 6.20.2.12 glcp debug clock control (glcp_dbgclkctl) this register is reserved for internal testing only. these bits should not be written to. msr address 51700014h ty p e r / w reset value 00000000_00000000h glcp_sys_rst register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd rsvd chip_reset glcp_sys_rst bit descriptions bit name description 63:24 rsvd reserved. reads as 0. 23:1 rsvd reserved. these bits can be read/written bu t should not be used; write to 0. 0 chip_reset chip reset. when written to a 1, the geode cs5535 companion device enters reset, which in turn resets this register. jtag logic is not reset by chip_reset, but other- wise the entire chip is reset. (default = 0.) msr address 51700016h ty p e r / w reset value 00000000_00000002h glcp_dbgclkctl register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd glcp_dbgclkctl bit descriptions bit name description 63:0 rsvd reserved. this register is reserved for internal testing only. these bits should not be written to. amd geode? cs5535 companion device data book 543 geodelink? control processor register descriptions 31506b 6.20.2.13 chip revision id (glcp_chip_rev_id) msr address 51700017h ty p e r o reset value 00000000_000000xxh chip_rev_id register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd maj min chip_rev_id bit descriptions bit name description 63:8 rsvd reserved 7:4 maj major revision. identifies major silicon revision. see amd geode? cs5535 compan- ion device specification update document for value. 3:0 min minor revision. identifies minor silicon revision. see amd geode? cs5535 com- panion device specification update document for value. 544 amd geode? cs5535 companion device data book geodelink? control processor register descriptions 31506b amd geode? cs5535 companion device data book 545 7 electrical specifications 31506b 7.0 electrical specifications this chapter provides information about: general specifications dc characteristics ac characteristics throughout this section, the following abbreviations apply: c degrees centigrade ma milli amps mhz mega hertz ms milli seconds mv milli volts na not applicable ns nano seconds pf pico farads t enable time enable t hold time hold t setup time setup t val time valid vvolts a micro amps s micro seconds 7.1 general specifications 7.1.1 electro static discharge (esd) this device is a high performance integrated circuit and is esd sensitive. handling and assembly of this device should be performed at esd free workstations. table 7-1 lists the esd ratings of the amd geode? cs5535 com- panion device. 7.1.2 power/ground connections and decoupling when testing and operating th is component, use standard high frequency techniques to reduce parasitic effects. for example: filter the dc power leads with low-inductance decou- pling capacitors. use low-impedance wiring. utilize all power and ground connections. 7.1.3 absolute maximum ratings stresses beyond those indicated in table 7-2 may cause permanent damage to the component, reduce device reli- ability, and result in premature failure, even when there is no immediately apparent sign of failure. prolonged expo- sure to conditions at or near the absolute maximum ratings may also result in reduced device life span and reduced reliability. note: the values in the table 7-2 are stress ratings only. they do not imply that operation under these con- ditions is possible. table 7-1. electro static discharge (esd) parameter units human body model (hbm) 2000v esd machine model (mm) 200v esd table 7-2. absolute maximum ratings parameter min max units comment operating case temperature -65 110 c power applied and no clocks. storage temperature -65 150 c no power applied. core supply 1.6 v i/o supply 3.6 v voltage on non-5v tolerant balls -0.5 3.6 v voltage on 5v tolerant balls -0.5 5.5 v 546 amd geode? cs5535 companion device data book electrical specifications 31506b 7.1.4 recommended operating conditions 7.1.5 current consumption table 7-3. recommended operating conditions symbol parameter min typ max units v core core supply voltage, working domain (note 1) 1.14 1.2 or 1.5 1.58 v v core_vsb core supply voltage, standby domain (note 1) 1.14 1.2 or 1.5 1.58 v v io i/o supply voltage, working domain 3.14 3.3 3.46 v v io_vsb i/o supply voltage, standby domain 3.14 3.3 3.46 v a vdd_usb usb transceiver supply voltage 3.14 3.3 3.46 v v bat real-time clock battery 2.4 3.0 3.6 v t case case temperature of package 0 85 c input timing input rise and fall times (unless otherwise indicated) see figure 7-1 "clock reference definition" on page 550 for rise and fall definition. 0.5 5 ns note 1. the geode? cs5535 companion device is designed to be used with the geode gx processor; as such, their core voltage ranges are compatible. table 7-4. current consumption symbol description typ avg abs max units comments i core_on core plus standby core current 60 125 ma cpu mode = full on typ = typical operating conditions, clock gating on max =maximum operating condi- tions, clock gating off i io_on i/o plus standby i/o current 12 25 ma cpu mode = full on typ = typical operating conditions, clock gating on max =maximum operating condi- tions, clock gating off i vdd_usb usb current 4 5 ma i core_sleep core plus standby core current 21 ma suspa# active all clocks stopped all i/os driven low or tri-state i io_sleep i/o plus standby i/o current 5 ma i core_vsb_standby standby core current <1 ma all operating conditions. i io_vsb_standby standby i/o current <1 ma no v io_vsb powered output sourcing current. i bat battery current @ v bat = 3.0v (nominal), 25c 5 a use for battery life calculation. when off, system quickly reaches ambient temperature. battery current @ v bat = 3.0v (max), 85c 10 a amd geode? cs5535 companion device data book 547 electrical specifications 31506b 7.2 dc characteristics all dc parameters and current specifications in this section are specified under the operating conditions listed in table 7-3 on page 546 (i.e., v core and v core_vsb = all; v io and v io_vsb = all; t case = all) unless otherwise specified. for a detailed explanation of buffer types for the parame- ters listed in table 7-5 on page 547, see table 3-4 "buffer type characteristics" on page 33. table 7-5. dc characteristics symbol buffer type min typ max units comment/condition v il low level input voltage q3, q5, q7 -0.3 0.5 0.8 v pci -0.3 0.5 0.3*v io v ide -0.3 0.5 0.8 v smb -0.3 0.5 0.8 v usb receiver -0.3 0.8 single ended operation. note 1, and note 2. reset_stand# (bare_wire) -0.3 0.5 0.8 v v ih high level input voltage q3, q5, q7 2.0 3.0 v io +0.3 v pci 0.5*v io 3.0 v io +0.3 v ide 2.0 3.0 v io +0.3 v smb 2.1 3.0 5.5 v 5v tolerant, backdrive (back- powered) protected. note 3. usb receiver 2.0 a vdd_usb +0.3 v single ended operation. note 1 and note 2. reset_stand# (bare_wire) 2.0 3.0 v io +0.3 v v ol low level output voltage q3, q5, q7 0.4 v i ol = 24 ma. pci 0.1*v io vi ol = 1.5 ma. ide 0.4 v i ol = 16 ma. smb 0.4 v i ol = 4 ma. usb driver 0.3 v 1.5 k ? resister to av dd_usb . dp or dn of each differential pair. note 2 v oh high level output voltage q3, q5, q7 2.4 v at i oh = -24 ma. pci 0.9*v io vat i oh = -500 a. ide 2.4 v at i oh = -16 ma. smb na open-drain. usb driver 2.8 v 15 k ? resister to ground. dp or dn of each differential pair. note 2 548 amd geode? cs5535 companion device data book electrical specifications 31506b i ileak (note 4) input leakage current q3, q5, q7 na +/- 3 a driver output disabled. vpad = 0 to v io . pci na +/- 5 a driver output disabled. vpad = 0 to v io . ide na +/- 2 a driver output disabled. vpad = 0 to v io . smb na +/- 5 a driver output disabled. vpad = 0 to v io . na 5 a driver output disabled. note 3. vpad = v io to 5.5. na 5 a note 3 and note 5. vpad = 0 to 5.5. usb na +/- 3 a driver output disabled. note 2 and note 6. vpad = 0 to a vdd_usb . reset_stand# (bare_wire) na +/- 3 a vpad = 0 to v io . i pu (note 7) pull-up current q3, q5, q7 -50 100 -150 a pull-up on and pull-down off. output tri-state and vpad = 0. i pd (note 7) pull-down current q3, q5, q7 20 45 130 a pull-up off and pull-down on. output tri-state and vpad = v io . note 1. actual value is adjustable. values in this table require vadj[2:0] = 4 (011b): --rcvr2_vadj: usbc1 msr 51600008h[16 :14] and usbc2 msr 51200008h[16:14]; --(rcvr1_vadj: usbc1 msr 51600008h[7:5] and usbc2 msr 51200008h[7:5]. the single ended receiver incorporates hysteresis for more reliable operation. under any mode of operation, the usb inputs do not me et the requirements of ?figure 7-1 maximum input wave- form for usb signaling? from the usb specification v1.1 . the maximum voltage can not exceed the value above. note 2. usb v1.1 compliance is achieved with external crimp protection diodes. note 3. the following smb i/os are limited to an input high max of v io : func_test, smb_clk, and smb_data. note 4. this parameter is sometime s referred to as tri-state leakage. note 5. v core and v core_vsb = 0, v io and v io_vsb = 0, t case = all. note 6. a vdd_usb from 0 to a vdd_usb_max . note 7. no pull-ups/downs on pci, ide, and smb i/o cell types. table 7-5. dc characteristics (continued) symbol buffer type min typ max units comment/condition amd geode? cs5535 companion device data book 549 electrical specifications 31506b table 7-6. other usb dc parameters signal parameter min max units comment/condition differential pair: usb1_1_datpos usb1_1_datneg differential pair: usb1_2_datpos usb1_2_datneg differential pair: usb2_1_datpos usb2_1_datneg differential pair: usb2_2_datpos usb2_2_datneg output v crs (cross over) 1.3 2.0 v same for low and full speed. note 1. input differential voltage sensitivity 200 mv same for low and full speed. note 2 and note 3. note 1. crossover voltage defined in figure 7-8 "usb output parameter definition" on page 560. note 2. see figure 7-9 "usb input parameter definition" on page 561. note 3. when both differential data inputs are in t he differential input voltage common mode range (v cm ) of 0.8v to 2.5v as illustrated in figure 7-10 "usb differential input sensitivity range" on page 561. 550 amd geode? cs5535 companion device data book electrical specifications 31506b 7.3 ac characteristics unless otherwise indicated, no inputs have a specified hysteresis. figure 7-1 and figure 7-2 provide reference definitions used in this section. figure 7-1. clock reference definition figure 7-2. ac reference timing and test definition cycle time high time 2.40v 0.40v rise time low time fall time v ref = 1.2v or 1.5v t val clock t setup t hold input valid t float output driving tri-state t enable output driving 0.0 v 3.0 v v oh v ol v ih v il v oh v ol v ref = 1.2v or 1.5v v ref = 1.2v or 1.5v tri-state defined as output current less than or equal to leakage current amd geode? cs5535 companion device data book 551 electrical specifications 31506b figure 7-3. output reference timing and test definition figure 7-4. input reference timing and test definition v ref = 1.2v or 1.5v output reference signal t val_m (minus) t val_p (plus) output valid v ref = 1.2v or 1.5v v oh v ol v oh v ol v ref = 1.2v or 1.5v input reference signal t setup t hold input valid v ref = 1.2v or 1.5v v ih v il v ih v il 552 amd geode? cs5535 companion device data book electrical specifications 31506b 7.3.1 clock inputs all of the clocks in table 7-7 indicate a minimum frequency of zero. specifically, there are no dynamic circuits with min- imum clock speeds. additionally, active hardware clock gating (ahcg) (see section 4.9 "power management" on page 79) will turn off all or some of the system clocks at selected points in time to save power. the khz32_xci/kh32xco being the one exception to ?off all?. it always runs. while the above discussion is accurate, there are minimum clock requirements for proper system operati on. these are indicated in the notes for each clock in table 7-7. table 7-7. clock timing parameters signal parameter min typ max units comment/condition mhz66_clk frequency 0 66.00 66.50 mhz note 1 and note 2. rise/fall time 0.5 2 ns high/low time 6 none ns note 3. pci_clk frequency 0 33 or 66 67.50 mhz note 1 and note 4. rise/fall time 0.5 2 ns high/low time 6 none ns note 3. mhz48_clk frequency 0 48.00 49.25 mhz note 1 and note 5. rise/fall time 0.5 2 ns high/low time 6 none ns note 3. lpc_clk frequency 0 33 34 mhz note 1, note 4, and note 6. rise/fall time 0.5 2 ns high/low time 6 none ns note 3. mhz14_clk frequency 0 14.31818 15.00 mhz note 1 and note 7. rise/fall time 0.5 2 ns high/low time 6 none ns note 3. ac_clk frequency 0 12.239 13.00 mhz note 1 and note 8. rise/fall time 0.5 2 ns high/low time 6 none ns note 3. tck frequency 0 4.0 15.00 mhz note 1. rise/fall time 0.5 2 ns high/low time 6 none ns note 3. khz32_xci khz32_xco frequency 0 32.768 1000 khz note 1 and note 9. high/low time 0.5 none s note 3. note 1. signal parameters are defined in figure 7-1 "clock reference definition" on page 550. note 2. operationally, the minimum clock is 64.50 mhz. operation out of the 66 mhz range indicated causes the geode cs5535 companion device ata controller to operate out of ata specification limits. note 3. clock duty cycles not 100% tested. guaranteed by design. note 4. for maximum system performance, this clock should be as high as possible up to the maximum indicated. note 5. the usb spec requires a controller accuracy of +/- 0.05% (500 ppm). note 6. must be greater than half the mhz14_clk frequency. must be at least four times fa ster than the khz32_xci frequency. note 7. this clock is used as the system time base a nd hence should have the ?typ ical? frequency indicated. note 8. this clock should be connected to the external code c output that is half the codec input clock of 24.478 mhz. note 9. typically, connect these pins to a 32.768 khz crystal. however, an external oscillator may be connected to the khz32_xci pin and driven to the maximum rate shown for testing. when operated with an external oscillator, leave the khz32_xco pin open. when operatin g with an external oscillator, inpu t voltage on khz32_xci (khz32_xci) should swing rail-to-rail, that is, zero-to-v io_vsb . with external oscillator, the input voltage high should always be at least 3.0 volts. amd geode? cs5535 companion device data book 553 electrical specifications 31506b 7.3.2 reset and test inputs table 7-8. reset and test timing parameters signal parameter min max units comment/condition reset_work# rise/fall time 0.5 5 ns note 1. low time 3 none ns time required to detect a reset. high time 3 none ns cycle time does not apply. once the component has started a reset operation, cycling this input generally does not apply. reset_stand# rise/fall time 0.5 5 ns note 1. low time 3 none ns time required to detect a reset. high time 3 none ns cycle time does not apply. once the component has started a reset operation, cycling this input generally does not apply. lvd_en# static signal. tie high or low as indicated in the signal description. test_mode static signal. operationally, always tie low. func_test static signal. operationally, always tie low. note 1. signal parameters are defined in figure 7-1 "clock reference definition" on page 550. 554 amd geode? cs5535 companion device data book electrical specifications 31506b 7.3.3 pci and related signals the signals detailed in this sub-section use a ?pci? buffer type except susp#, susp a#, and reset_out# they use types ?q3? and ?q7? respectively. for a detailed expla- nation of buffer types, see t able 3-4 "buffer type charac- teristics" on page 33. in this subsection, unless otherwise noted: all timing specifications are specified under the oper- ating conditions listed in table 7-3 on page 546 (i.e., v core and v core_vsb = all; v io and v io_vsb = all; t case = all). signals are referenced to pci_clk low-to-high edge. signal and test parameter s are defined in figure 7-2 "ac reference timing and test definition" on page 550. table 7-9. pci, susp#, suspa#, and reset_out# timing parameters signal parameter min max units comment/condition pci_inta# (gpio0) pci_intb# (gpio7) async input na na ns no clock reference. see section 7.3.13 "gpio signaling" on page 568. req# t val 2 6 ns note 1. gnt# t setup 5nans t hold 0nans cbe[3:0]#, devsel#, frame#, trdy#, irdy#, stop#, pa r , ad[31:0] t val 2 6 ns applies when signal is an output. note 1. t float na 8 ns applies when signal is an output. note 2. t enable 2 na ns applies when signal is an output. note 3. t setup 3 na ns applies when signal is an output. t hold 0nans susp# t val 1 6 ns note 1. reset_out# t val 3 10 ns note 4. suspa# t setup 3nans t hold 0nans note 1. t val min times with load of: 10 pf cap to ground. t val max times with load of: 35 pf cap to ground. note 2. t float with the load of: 10 pf cap to ground. note 3. t enable with the load of: 10 pf cap to ground. note 4. t val min times with load of: 10 pf cap to ground t val max times with load of: 50 pf cap to ground. amd geode? cs5535 companion device data book 555 electrical specifications 31506b 7.3.4 ide signals in ide mode the signals detailed in this sub-section use an ?ide? buffer type. for a detailed explanation of buffer types, see table 3-4 "buffer type characteristics" on page 33. in this subsection, unless otherwise noted: all timing specifications are specified under the oper- ating conditions listed in table 7-3 on page 546 (i.e., v core and v core_vsb = all; v io and v io_vsb = all; t case = all). signals are referenced to mhz66_clk low-to-high edge. signal and test parameter s are defined in figure 7-2 "ac reference timing and test definition" on page 550. table 7-10. ide register, pio, and multiword dma timing parameters signal parameter min max units comment/condition ide_cs[1:0]#, ide_iow0, ide_ad[2:0], ide_rst#, ide_dack0# t val 2 10 ns ide_dack0# is only used for dma. note 1 and note 2. ide_ior0# t val 3 13 ns note 1 and note 2. ide_data[15:0] for write note 3. ide_data[15:0] for read note 4 and note 5. ide_rdy0, ide_irq0, ide_dreq0# async input na na ns no clock reference. note 6. ide_irq0 and ide_dreq0# are only used for dma. note 1. per the ata/atapi-5 spec, these signals utilize output reference timing (see figure 7-3 on page 551) relative to ide_ior0# and ide_iow0#. however, the ide controller uses the mhz66_clk edges to make output changes, that when taken together, meet all the timing r equirements of the refere nced spec. therefore, t val times are spec- ified and tested relative to the mhz66_clk. note 2. t val min times with load of: 15 pf cap to ground. t val max times with load of: 40 pf cap to ground. note 3. per the ata/atapi-5 spec, ide_data write signals utilize output reference timing (see figure 7-3 on page 551) relative to ide_iow0#. however, the ide controller us es the mhz66_clk edges to make output changes, and when taken together, meet all the timi ng requirements of the referenced spec . see figure 7-5 "ide data in timing non-ultradma" on page 556. note 4. per the ata/atapi-5 spec, these signals utilize input reference timing (see figure 7-4 on page 551) relative to ide_ior0#. however, the ide controller samples the inputs with the mhz66_clk at the appropriate points in time to meet all the timing requirements of the referenced spec. note 5. see figure 7-5 "ide data in timing non-ultradma". as in dicated in note 4, ide_data[1 5:0] read input is specified relative to the low-to-high edge of ide_ior0#. however, the implementation meets a tighter test spec referenced to the low-to-high edge of the mhz66_clk. note 6. for ide_irq0, gpio2 configured: aux in and input e nable = 1; output enable, aux out 1, and aux out 2 = 0. 556 amd geode? cs5535 companion device data book electrical specifications 31506b figure 7-5. ide data in timing non-ultradma t setup t hold mhz66_clk ide_ior0# ide_data[15:0] (read) read operations write operations t setup t hold mhz66_clk ide_iow0# ide_data[15:0] (write) ide_data enable driving ata-spec = 20 to 60 ns depending on mode ata-spec = 10 to 30 ns ata-spec = 20 to 60 ns depending on mode ata-spec = 5 ns depending on mode 15 ns (approximate minimum clock period. seetable 7-7). 15 ns (approximate minimum clock period. see table 7-7). ide_data tri-state depending on mode amd geode? cs5535 companion device data book 557 electrical specifications 31506b figure 7-6. ide ultradma data out timing table 7-11. ide ultradma da ta out timing parameters signal parameter min max units comment/condition ide_dack0# ide_hdma_ds, ide_stop, ide_iow0# t val 2 10 ns in ultra dma/33 mode, the ide_ior0# signal is redefined as ide_hdma_ds. note 1 and note 2. ide_data[15:0] t val see notes ns note 2 and note 3. ide_dreq0 async input na na ns no clock reference. note 4. ide_ddma_rdy async input na na ns in ultra dma/33 mode, the ide_rdy0 signal is redefined as ide_ddma_rdy . note 4. ide_irq0 async input na na ns note 4 and note 5. note 1. per the ata/atapi-5 spec, these signals utilize output reference timing (see figure 7-3 on page 551) relative to ide_ior0# and ide_iow0#. however, the ide controller uses the mhz66_clk edges to make output changes, that when taken together, meet all the timing r equirements of the refere nced spec. therefore, t val times are spec- ified and tested relative to the mhz66_clk. note 2. t val min times with load of: 15 pf cap to ground. t val max times with load of: 40 pf cap to ground. note 3. this signal uses output reference timing (see figure 7-3 on page 551). figure 7-6 illustrates ide_hdma_ds and ide_data[15:0] relationship. note 4. per the ata/atapi-5 spec, these signals utilize input reference timing (see figure 7-4 on page 551) relative to ide_ior0#. however, the ide controller samples the inputs with the mhz66_clk at the appropriate points in time to meet all the timing requirements of the referenced spec. note 5. for ide_irq0, gpio2 configured: in_aux1 and inpu t enable = 1; output enable, out_aux1, and out_aux2 = 0. ide_hdma_ds ide_data[15:0] t val_m = 6 ns t val_p = 6 ns 558 amd geode? cs5535 companion device data book electrical specifications 31506b figure 7-7. ide ultradma data in timing table 7-12. ide ultradma data in timing parameters signal parameter min max units comment/condition ide_dack0#, ide_hdma_rdy, ide_stop, ide_iow0 t val 2 10 ns in ultra dma/33 mode, the ide_ior0# signal is redefined as ide_hdma_rdy. note 1 and note 2. ide_ddma_ds async input na na ns in ultra dma/33 mode, the ide_rdy0 signal is redefined as ide_ddma_ds . note 3. ide_data[15:0] sync to ide_ddma_ds see note ns note 3. ide_dreq0# async input na na ns no clock reference. note 4. ide_irq0 async input na na ns note 4 and note 5. note 1. per the ata/atapi-5 spec, these signals utilize output reference timing (see figure 7-3 on page 551) relative to ide_ior0# and ide_iow0#. however, the ide controller uses the mhz66_clk edges to make output changes, that when taken together, meet all the timing r equirements of the refere nced spec. therefore, t val times are spec- ified and tested relative to the mhz66_clk. note 2. t val min times with load of: 15 pf cap to ground. t val max times with load of: 40 pf cap to ground. note 3. these signals use input reference timing (see figure 7-4 on page 551). figure 7-7 illustrates their relationship and specified setup and hold times. note 4. per the ata/atapi-5 spec, these signals utilize input reference timing (see figure 7-4 on page 551) relative to ide_ior0#. however, the ide controller samples the inputs with the mhz66_clk at the appropriate points in time to meet all the timing requirements of the referenced spec. note 5. for ide_irq0, gpio2 configured: in_aux1 and inpu t enable = 1; output enable, out_aux1, and out_aux2 = 0. t setup = 5 ns t hold = 5 ns ide_device_data_strobe ide_data[15:0] amd geode? cs5535 companion device data book 559 electrical specifications 31506b 7.3.5 ide signals in flash mode the signals detailed in this sub-section use an ?ide? buffer type. for a detailed explanation of buffer types, see table 3-4 "buffer type characteristics" on page 33. in this subsection, unless otherwise noted: all timing specifications are specified under the oper- ating conditions listed in table 7-3 on page 546 (i.e., v core and v core_vsb = all; v io and v io_vsb = all; t case = all). signals are referenced to lpc_clk. signal parameters are defined in figure 7-2 "ac refer- ence timing and test definition" on page 550. table 7-13. flash timing parameters signal parameter min max units comment/condition flash_cs[3:0]#, flash_re#, flash_we, flash_ale, flash_cle, flash_ad[9:0], flash_io[7:0] signals and i/os in flash output mode t val 2 9 ns note 1. flash_io[7:0] signals and i/os in flash input mode except flash_iochrdy t setup 8nans t hold 0nans flash_iochrdy async input na na ns no clock reference. note 1. t val min times with load of: 10 pf cap to ground. t val max times with load of: 50 pf cap to ground. 560 amd geode? cs5535 companion device data book electrical specifications 31506b 7.3.6 usb signals all signals detailed in this sub-section use an ?ide? buffer type. for a detailed explanation of buffer types, see table 3-4 "buffer type characteristics" on page 33. in this subsection, unless otherwise noted: all timing specifications are specified under the oper- ating conditions listed in table 7-3 on page 546 (i.e., v core and v core_vsb = all; v io and v io_vsb = all; t case = all). figure 7-8. usb output parameter definition table 7-14. usb timing parameters signal parameter min max units comment/condition usb_pwr_en1, usb_pwr_en2 usb_oc_sens# differential pair: usb1_1_datpos, usb1_1_datneg, differential pair: usb1_2_datpos, usb1_2_datneg, differential pair: usb2_1_datpos, usb2_1_datneg usb2_portdn1 differential pair: usb2_2_datpos, usb2_2_datneg async output or level na na ns no clock reference. async input na na ns no clock reference. output rise and fall times (full speed) 4 20 ns note 1, note 2, and note 3. output rise and fall times (low speed) 75 300 ns note 1, note 2, a nd note 4. measured at the downstream host end. note 1. rise time and fall time defined in figure 7- 8 "usb output parameter definition" on page 560. note 2. the rise and fall time values for a given differential pair are matched within 10%. edges are monotonic. note 3. actual value is adjustable. values in this table require cadj[4:0] = 0x10b: --xmit2_cadj: usbc1 msr 51600008h[13: 9] and usbc2 msr 51200008h[4:0]; --(xmit1_cadj: usbc1 msr 51600008h[ 7:5] and usbc2 msr 51200008h[7:5]. note 4. the rise and fall time values for a given differential pair are matched within 20%. edges are monotonic. 90% v hl output crossover voltage (v crs ) 10% v ol rise time fall time v oh v ol amd geode? cs5535 companion device data book 561 electrical specifications 31506b figure 7-9. usb input parameter definition figure 7-10. usb differential input sensitivity range d+ d- input crossover voltage (v crs ) input differential voltage differential input voltage common mode range (v cm ) differential output 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 crossover voltage range 562 amd geode? cs5535 companion device data book electrical specifications 31506b 7.3.7 system management bus (smb) signals the signals detailed in this sub-section use an ?smb? buffer type. for a detailed explanation of buffer types, see table 3-4 "buffer type characteristics" on page 33. the smb utilizes a two-wire asynchronous protocol. mas- ter and slave devices are connected open-drain with an external pull-up resistor. the smb_clk is not a free run- ning fixed frequency signal, but rather a cooperatively gen- erated signal with a minimum low time of 4.7 s, minimum high time of 4.0 s, and 100 khz frequency limit. the mini- mum frequency is 10 khz. the smb_data signal is also cooperatively driven. communication on the smb is via rel- ative manipulation of these two signals. the smb control- ler and i/o cell incorporated within the geode cs5535 companion device fu lly meets the requirements of the smb specification version 2.0. in this subsection, unless otherwise noted: all timing specifications are specified under the oper- ating conditions listed in table 7-3 on page 546 (i.e., v core and v core_vsb = all; v io and v io_vsb = all; t case = all). table 7-15. smb timing parameters signal parameter min max units comment/condition bidirectional smb_clk (gpio14), smb_data (gpio15) async output or level na na ns no clock reference. async input na na ns no clock reference. amd geode? cs5535 companion device data book 563 electrical specifications 31506b 7.3.8 ac97 codec signals the signals detailed in this sub-section use a ?q7? buffer type. for a detailed explanation of buffer types, see table 3-4 "buffer type characteristics" on page 33. in this subsection, unless otherwise noted: all timing specifications are specified under the oper- ating conditions listed in table 7-3 on page 546 (i.e., v core and v core_vsb = all; v io and v io_vsb = all; t case = all). signals are referenced to ac_clk low-to-high edge. signal parameters are defined in figure 7-2 "ac refer- ence timing and test definition" on page 550. table 7-16. ac97 codec timing parameters signal parameter min max units comment/condition ac_s_out, ac_s_sync t val 2 15 ns note 1. ac_s_in, ac_s_in2 (gpio12) t setup 10 na ns note 2 and note 3. t hold 10 na ns ac_beep (gpio1) t val 2 25 ns note 1, note 4. and note 5. note 1. t val min times with load of: 10 pf cap to ground. t val max times with load of: 50 pf cap ground. note 2. signals are referenced to ac_clk high-to-low edge. note 3. for ac_s_in2, gpio12 configured: (aux in) and in put enable = 1; output enable, out_aux1, and out_aux2 = 0. note 4. signal is referenced to lpc_clk low-to-high edge. note 5. for ac_beep, gpio1 configured: out_aux1 and ou tput enable = 1; open-drain, out_aux2, and input enable = 0. 564 amd geode? cs5535 companion device data book electrical specifications 31506b 7.3.9 low pin count (lpc) signals the signals detailed in this sub-section use a ?pci? buffer type except for lcp_clk. lpc_clk uses a ?q7? buffer. for a detailed explanation of buffer types, see table 3-4 "buffer type characteristics" on page 33. in this subsection, unless otherwise noted: all timing specifications are specified under the oper- ating conditions listed in table 7-3 on page 546 (i.e., v core and v core_vsb = all; v io and v io_vsb = all; t case = all). signals are referenced to lpc_clk low-to-high edge. signal parameters are defined in figure 7-2 "ac refer- ence timing and test definition" on page 550. table 7-17. lpc timing parameters signal parameter min max units comment/condition lpc_frame#, lpc_ad[3:0], lpc_drq#, lpc_serirq t val when signal is an output 2 11 ns note 1 and note 2. t float when signal is an output na 11 ns note 2 and note 3. t enable when signal is an output 2 na ns note 2 and note 4. t setup when signal is an input 7 na ns note 2. t hold when signal is an input 0 na ns note 2. note 1. t val min times with load of: 10 pf cap to ground. t val max times with load of: 50 pf cap to ground. note 2. all information in this table applies when the following control bits are high in table 3-6 "divil_ball_opt (msr 51400015h)" on page 34: pin_opt_ldrq, pin_opt_lirq, and pin_opt_lall. note 3. t float with the load of: 10 pf cap to ground. note 4. t enable with the load of: 10 pf cap to ground. amd geode? cs5535 companion device data book 565 electrical specifications 31506b 7.3.10 power management and processor control signals the power management controller (pmc) signals detailed in this sub-section use various types of buffers depending upon chip configuration. for a detailed explanation of buffer types, see table 3-4 "buffer type characteristics" on page 33. in this subsection, unless otherwise noted: all timing specifications are specified under the oper- ating conditions listed in table 7-3 on page 546 (i.e., v core and v core_vsb = all; v io and v io_vsb = all; t case = all). no clock reference. table 7-18. power management and processor control timing parameters signal parameter min max units comment/condition working async output or level na na ns from pmc. reset_out# sync output to pci_cl k na na ns see reset_out# in table 7- 9 on page 554. thrm_alrm# (gpio10) async i nput na na ns note 1. to pmc. slp_clk_en (gpio11) asyn c output or level na na ns note 2. from pmc. work_aux (gpio24) async output or level na na ns note 2. from pmc. low_bat# (gpio25) async input na na ns note 1. to pmc. pwr_but# (gpio28) async i nput na na ns note 1. to pmc. , suspa# sync to pci_clk na na ns see table 7-9 on page 554 for , suspa# data. irq13 async input na na ns to pic subsystem. sleep_x (gpio7) async output or level na na ns note 3. from pmc. sleep_y (gpio12) async ou tput or level na na ns note 3. from pmc. sleep_but (gpio13) async i nput na na ns note 1. to pmc. note 1. gpio configured: in_aux1 and input enable = 1; output enable, out_aux1, and out_aux2 = 0. note 2. gpio configured: in_aux1 and input enable = 0; output enable and out_aux1 = 1; open-drain and out_aux2 = 0. note 3. gpio configured: in_aux1 and input enable = 0; output enable and out_aux2 = 1; open-drain and out_aux1 = 0. 566 amd geode? cs5535 companion device data book electrical specifications 31506b 7.3.11 miscellaneous signals the ?recommended use? for gpio3 and gpio4 is ddc support signals ddc_scl and ddc_sda, because these two gpios have a high drive capacity, open-drain output. they use an ?smb? buffer type. the 32 khz clock output is a mux option on gpio27 and uses a ?q7? buffer. for a detailed explanation of buffer types, see table 3-4 "buffer type characteristics" on page 33. in this subsection, unless otherwise noted: all timing specifications are specified under the oper- ating conditions listed in table 7-3 on page 546 (i.e., v core and v core_vsb = all; v io and v io_vsb = all; t case = all). signals are referenced to khz32_xci high-to-low edge. signal parameters are defined in figure 7-2 "ac refer- ence timing and test definition" on page 550. table 7-19. miscellaneous signals except uart timing parameters signal parameter min max units comment/condition ddc_scl (gpio3) ddc_sda (gpio4) na na na ns see section 7.3.13 "gpio signaling" on page 568. 32khz (gpio27) t val 2 15 ns note 1 and note 2. note 1. t val min times with load of: 10 pf cap to ground. t val max times with load of: 50 pf cap to ground. note 2. gpio27 configured: in_aux1 and input enable = 0; output enable and out_aux2 = 1; open-drain and out_aux1 = 0. amd geode? cs5535 companion device data book 567 electrical specifications 31506b 7.3.12 uart and ir signaling the uart support signals detailed in this sub-section use various types of buffers depending upon chip configuration. for a detailed explanation of buffer types, see table 3-4 "buffer type characteristics" on page 33. in this subsection, unless otherwise noted: all timing specifications are specified under the oper- ating conditions listed in table 7-3 on page 546 (i.e., v core and v core_vsb = all; v io and v io_vsb = all; t case = all). no clock reference. table 7-20. uart timing parameters signal parameter min max units comment/condition uart1_tx (gpio8) async output or level na na ns note 1. uart1_ir_tx (gpio8) async out put or level na na ns note 2. uart1_rx (gpio9) async input na na ns note 3. uart2_tx (gpio4) async output or level na na ns note 1. uart2_rx (gpio3) async input na na ns note 3 note 1. gpio configured: in_aux1 and input enable = 0; output enable and out_aux1 = 1; open-drain and out_aux2 = 0. note 2. gpio configured: in_aux1 and input enable = 0; output enable and out_aux2 = 1; open-drain and out_aux1 = 0. note 3. gpio configured: in_aux1 and input enable = 1; output enable, out_aux1, and out_aux2 = 0. 568 amd geode? cs5535 companion device data book electrical specifications 31506b 7.3.13 gpio signaling the gpio signals detailed in this sub-section use various types of buffers depending upon chip configuration. for a detailed explanation of buffer types, see table 3-4 "buffer type characteristics" on page 33. in this subsection, unless otherwise noted: all timing specifications are specified under the oper- ating conditions listed in table 7-3 on page 546 (i.e., v core and v core_vsb = all; v io and v io_vsb = all; t case = all). gpio[22:0] signals are referenced to lpc_clk and gpio[28:24] signals are referenced to khz32_xci. use low-to-high edge if lpc clock; use high-to-low edge if 32khz clock. gpio signal parameters are defined in figure 7-2 "ac reference timing and test definition" on page 550. table 7-21. gpio signaling signal gpio[28:24, 22:0] parameter mi n max units comment/condition gpio input [all] async input na na ns no clock reference. can be read via programmed i/o. can be used as an interrupt or pme. note 1 and note 2. gpio output [22:16, 13:5, 2:0] t val 2 20 ns note 2, note 3, and note 4. (lpc_clk) gpio output [28:25] t val 4 20 ns note 2, note 3, and note 4. (khz32_xci) gpio od output high-to-low data [15:14, 4:3] t val 2 25 ns note 2, note 4, and note 5. (lpc_clk) gpio od output high-to-low data [24] t val 4 25 ns note 2, note 4, and note 5. (khz32_xci) gpio od output low-to-high data [15:14, 4:3] t val na 28 ns note 2, note 4, and note 5 (lpc_clk) gpio od output low-to-high data [24] t val na 28 ns note 2, note 4, and note 5. (khz32_xci) note 1. gpio configured: input enable = 1; in_aux 1, output enable, out_aux1, and out_aux2 = 0. note 2. pin_opt_lall = 0 in table 3-6 "divil_ball_opt (msr 51400015h)" on page 34. note 3. t val min times with load of: 10 pf cap to ground. t val max times with load of: 50 pf cap to ground. note 4. gpio configured: in_aux1, input enable, out_au x1, out_aux2 = 0; output enable = 1; open-drain = 0. note 5. load per table 7-15 "smb timing parameters" on page 562. amd geode? cs5535 companion device data book 569 electrical specifications 31506b 7.3.14 mfgpt signaling the mfgpt signals detailed in this sub-section use vari- ous types of buffers depending upon chip configuration. for a detailed explanation of buffer types, see table 3-4 "buffer type characteristics" on page 33. in this subsection, unless otherwise noted: all timing specifications are specified under the oper- ating conditions listed in table 7-3 on page 546 (i.e., v core and v core_vsb = all; v io and v io_vsb = all; t case = all). mfgpt signals are referenced to khz32_xci or mhz14_clk depending on mfgpt clock configuration. use low-to-high edge if mhz14_clk; use high-to-low edge if khz32_xci. mfgp t7 supports khz32_xci only. mfgpt signal parameters are defined in figure 7-2 "ac reference timing and test definition" on page 550. table 7-22. mfgpt signaling signal parameter min max units comment/condition inputs: mfgpt0 (gpio6) mfgpt1 (gpio5) mfgpt2 (gpio21) mfgpt7 (gpio26) async input na na ns no clock reference. restarts the mfgpt. note 1 and note 2. outputs: mfgpt0_c1 (gpio5) mfgpt1_c1 (gpio6) mfgpt2_c1 (gpio7) mfgpt7_c1 (gpio27) t val if mhz14_clk 2 20 ns note 2, note 3, and note 4. t val if khz32_xci 2 20 ns outputs: mfgpt0_c2 (gpio1) mfgpt1_c2 (gpio11) mfgpt2_c2 (gpio6) mfgpt7_c2 (gpio25) t val if mhz14_clk 2 20 ns note 2, note 3, and note 5. t val if khz32_xci 2 20 ns note 1. gpio configured: input enable and in_aux1 = 1; output enable, out_aux1, and out_aux2 = 0. note 2. pin_opt_lall = 0 in table 3-6 "div il_ball_opt (msr 51400015h)" on page 34. note 3. t val min times with load of: 10 pf cap to ground. t val max times with load of: 50 pf cap to ground. note 4. gpio configured: in_aux1, input enable = 0; output enable = 1; open-drain = 0; out_aux1 =1; out_aux2 = 0. note 5. gpio configured: in_aux1, input enable = 0; output enable = 1; open-drain = 0; out_aux1 = 0; out_aux2 = 1. 570 amd geode? cs5535 companion device data book electrical specifications 31506b 7.3.15 jtag signals the tdi and tdo jtag signals use a ?q5? buffer type while the tms signal uses a ?q7?. for a detailed explana- tion of buffer types, see table 3-4 "buffer type character- istics" on page 33. in this subsection, unless otherwise noted: all timing specifications are specified under the oper- ating conditions listed in table 7-3 on page 546 (i.e., v core and v core_vsb = all; v io and v io_vsb = all; t case = all). signals are referenced to tck low-to-high edge. signal parameters are defined in figure 7-2 "ac refer- ence timing and test definition" on page 550. table 7-23. jtag timing parameters signal parameter min max units comment/condition tdo t val 2 16 ns note 1 and note 2. tms, tdi t setup 10 na ns t hold 2nans note 1. t val min times with load of: 10 pf cap to ground. t val max times with load of: 50 pf cap to ground. note 2. signal is referenced to tck high-to-low edge. amd geode? cs5535 companion device data book 571 electrical specifications 31506b 7.4 power supply s equence requirements the voltages applied to the geode cs5535 companion device are subject to the r equirements listed below as well as the requirements of table 7-3 "recommended operat- ing conditions" on page 546. reference values ?minimum? and ?maximum? below should be taken from table 7-3. note that the information below is provided for complete- ness. since the specified margins are very wide, the typical power supply implementation meets them without problem. if these requirements are no t observed, the rtc circuit and/or the lvd circuit may not operate correctly. 1) v core and v io may come up in any order but must meet their respective minimum values within 100 ms of each other. 2) from zero volts, v core and v io must ramp up mono- tonically and reach 90% of their respective minimum values no sooner that 10 s and no later than 1 sec- ond. 3) from their respective minimum values, v core and v io must ramp down to within 0.4 volts of ground no sooner than 100 ms and no later than 5 seconds. 4) same as requirement 1, but for v core_vsb and v io_vsb . 5) same as requirement 2, but for v core_vsb (vdd_vsb) and v io_vsb . 6) same as requirement 3 but for v core_vsb and v io_vsb . 7) the absolute value of the delta between v core and v core_vsb must not exceed 0.25 volts. 8) the absolute value of the delta between v io and v io_vsb must not exceed 0.25 volts. 572 amd geode? cs5535 companion device data book electrical specifications 31506b 7.5 low voltage detect (lvd) parameters the lvd electrical parameters are defined in figure 7-11 and listed in table 7-24. use of internal signals power good standby and power good working is illustrated in figure 4-6 "reset logic" on page 66. in this subsection, unless otherwise noted: all timing specifications are specified under the oper- ating conditions listed in table 7-3 on page 546 (i.e., v core and v core_vsb = all; v io and v io_vsb = all; t case = all). the lvd circuit incorporates no clock signals. figure 7-11. lvd electrical parameters table 7-24. lvd parameters signal parameter min max units comment/condition power good standby v rising_trip_core_vsb 0.80 1.00 v v falling_trip_core_vsb 0.72 0.90 v v hysteresis_core_vsb 23 110 mv note 1. v rising_trip_io_vsb 2.15 3.05 v v falling_trip_io_vsb 2.32 3.05 v v hysteresis_io_vsb 100 580 mv note 1. power good working v rising_trip_core 0.80 1.00 v v falling_trip_core 0.72 0.90 v v hysteresis_core 23 110 mv note 1. note 1. the resulting circuit has high noise immunity. any glitch es less than 150 ns are reje cted. hysteresis is guaranteed by design. v = v operating v = v rising_trip v = v falling_trip v = 0 v = 0 power_good ~= v core_vsb power_good ~= v ss amd geode? cs5535 companion device data book 573 electrical specifications 31506b 7.6 skip parameter the skip electrical parameters are defined in figure 7-12 and listed in table 7-25. in this subsection, unless other- wise noted: all timing specific ations are specified under the operating conditions listed in table 7-3 on page 546 (i.e., v core and v core_vsb = all; v io and v io_vsb = all; t case = all). figure 7-12. skip electrical parameters table 7-25. skip parameters parameter min max units comment/condition v rising_trip_io_vsb 2.15 3.05 v pwr_but# high 0 1 s to enable skip, tie pwr_but# to ground. to disable skip, pwr_but# must be high. pwr_but# 1 s v rising_trip_io_vsb 574 amd geode? cs5535 companion device data book electrical specifications 31506b amd geode? cs5535 companion device data book 575 8 package specifications 31506b 8.0 package specifications amd geode? c5535 companion device is packaged in a 208-terminal pbga (plastic ball grid array). figure 8-1 provides the mechanical dimensions of the package. figure 8-1. 208-terminal pbga package (body size: 23x23x2.13 mm; pitch: 1.27 mm) notes: unless otherwise specified. 1) pbga with lead (pb): a) solder ball composition: sn 63%, pb 37%. b) soldering profile: 220o c. 2) pbga lead (pb) free: a) solder ball composition: sn 96.5%, ag 3.5%. b) soldering profile: 260o c 3) dimension is measured at the maximum solder ball diameter, parallel to primary datum n. 4) the mold surface area may include dimple for a1 ball corner identification. 5) reference jedec registration mo-151, variation baj-2. 576 amd geode? cs5535 companion device data book package specifications 31506b a amd geode? cs5535 companion device data book 577 appendix a: support documentation 31506b appendix a support documentation a.1 order information a.2 data book revision history this document is a report of the revision/creation proc ess of the data book for the amd geode? cs5535 companion device. any revision (i.e., additions, deletions, parameter corrections, etc.) are recorded in the table(s) below. order number core voltage (v core ) temperature (degree c) package CS5535-UDC 1.2v or 1.5v 0 - 85 pbga CS5535-UDCf lead free pbga 1 1. note 1. as of this publication date, a lead free package ve rsion may not be available. check with your local amd sales representative for availability. see section 8.0 "package specifications" on page 575 for details on the lead free part. table a-1. revision history revision # (pdf date) revisions / comments 0.1 (10/23/01) first-pass draft for team to review. 0.2 (11/18/01) incorporat ed teams edits. first-pass release to customers. 0.3 (03/04/02) first-pass draft of co mplete data book for team review. 0.4 (03/12/02) second-pass of complete data book for team review. 0.41 (03/18/02) third-pass of comp lete data book for team review. 0.42 (03/21/02) fourth-pass of co mplete data book for team review. 0.43 (03/22/02) final corrections. this interim data book was released. 0.44 (06/18/02) corrections and updates following additional review and feedback. 0.5 (07/22/02) significant corrections and updates have been made to the section 4.0 "global concepts and fea- tures" and section 7.0 "e lectrical specifications". all outstanding corrections and additions have been made to: section 6.0 "register descriptions". 0.6 (12/23/02) first-pass of f unctional and register chapters formatting/re- write by tme and tech writer. text desig- nated in blue denotes that the tw needs to discu ss with the tme (or vice-versa) regarding consis- tency. 0.7 (2/21/03) changed table 3-3 "ball assignments: sorted alphabetically by signal name" to be broken out more (i.e., all signals even if muxed). focused on exp anding/detailing section 6.0 "register descriptions" and section 4.0 "global concepts and features" chap ters. text designated in blue denotes that the tw needs to discuss with the tme (or vice-versa) regarding consistency. 578 amd geode? cs5535 companion device data book appendix a: data book revision history 31506b 0.8 (7/28/03) design team reviewed tme/tech writer edits in rev 0.70. made adjust ments accordingly - mostly expanding/correcting register descriptions. tme/tech writer rewrote many functional sections of the data book. this revision has changed considerably (no functional changes were made, just the description of the modules and registers were m odified) and any old revisions should be discarded. 31506a (5/24/04) rev 0.9 was not released. changed name of processor from gx2 to geode gx processor and added engineering edits. 31506b (02/16/05) engineering edits. see table a-2 for details. table a-2. edits to current revision section revision all sections changed v core from 1.5v to 1.2v or 1.5v. multi-function general purpose timer was in correctly abbreviated as mfpgt. corrected all occurrences. section 3.0 "signal definitions" fixed typo for uart2_tx in table 3-9 on page 49. changed uart1 to uart2. section 5.0 "module functional descriptions" section 5.2 "geodelink? pci south bridge" changed asmi# to smi# for bit position 8, mode c in table 5-3 on page 87 and in third bullet explaining mode c. added # signs to active low signals in section 5.2.14 on page 87. section 6.0 "register descriptions" section 6.4 "ata-5 controller register descriptions" edited bit descriptions of bits [8 , 1] in section 6.4.1.4 on page 266. section 6.6 "diverse integration logic reg- ister descriptions" corrected typo in bit description for bit[22:20] in section 6.6.2.10 on page 334. changed uart1 to uart2. section 6.7 "floppy port register descrip- tions" corrected register name for msr address 51400032h. changed from flpy_3f2_shdw to flpy_372_shdw. section 6.13 "direct memory access reg- ister descriptions" corrected bit number for auto_init in bit descriptions table in section 6.13.2.6 on page 425. changed from 5 to 4. section 6.16 "gpio subsystem register descriptions" corrected bit name in bit description for bit[10:8] in section 6.16.4.1 on page 479. changed from gpio18 map select to gpio26 map select. section 6.17 "multi- function general pur- pose timer register descriptions" section 6.17.2.4 on page 492: ? bits[14:13] - edited bit descriptions. ? added write once to descriptions of bits[11:0]. ? corrected typo for bits[9:6] - had setting 00 twice, changed to 11. table a-1. revision history (continued) revision # (pdf date) revisions / comments one amd place p.o. box 3453 sunnyvale, ca 94088-3453 usa tel: 408-749-4000 or 800-538-8450 twx: 910-339-9280 telex: 3 4-6306 www.amd.com |
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